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author | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-09 08:33:21 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-09 08:33:21 +0000 |
commit | e80aa7c783ab27711505b540597d83e038fc6900 (patch) | |
tree | b738f9d5de86da71b1e295a4429ba9f4f0704a1d /test/CodeGen | |
parent | a3706d6754e972c4339e4495a18d803027bb9195 (diff) | |
download | external_llvm-e80aa7c783ab27711505b540597d83e038fc6900.zip external_llvm-e80aa7c783ab27711505b540597d83e038fc6900.tar.gz external_llvm-e80aa7c783ab27711505b540597d83e038fc6900.tar.bz2 |
Lower some x86 shuffle sequences to the vblend family of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154313 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/X86/avx-shuffle.ll | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll index 4885842..f323f3f 100644 --- a/test/CodeGen/X86/avx-shuffle.ll +++ b/test/CodeGen/X86/avx-shuffle.ll @@ -162,3 +162,43 @@ i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 62> ret <32 x i8> %0 } + +; CHECK: blend1 +; CHECK: vblendvps +; CHECK: ret +define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline { + %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> + ret <4 x i32> %t +} + +; CHECK: blend2 +; CHECK: vblendvps +; CHECK: ret +define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline { + %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x i32> %t +} + +; CHECK: blend2a +; CHECK: vblendvps +; CHECK: ret +define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinline { + %t = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x float> %t +} + +; CHECK: blend3 +; CHECK-NOT: vblendvps +; CHECK: ret +define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline { + %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 2, i32 7> + ret <4 x i32> %t +} + +; CHECK: blend4 +; CHECK: vblendvpd +; CHECK: ret +define <4 x i64> @blend4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline { + %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> + ret <4 x i64> %t +} |