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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-01 21:40:54 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-01 21:40:54 +0000 |
| commit | 1307d8300f6fe97059998480c42b44faefbc9b99 (patch) | |
| tree | aa96625b4ffc7739df065a5b144ffc610c1a7d2b /test/DebugInfo/PowerPC/tls.ll | |
| parent | bde84a96ea67737e275d2adee2da86a0fa875785 (diff) | |
| download | external_llvm-1307d8300f6fe97059998480c42b44faefbc9b99.zip external_llvm-1307d8300f6fe97059998480c42b44faefbc9b99.tar.gz external_llvm-1307d8300f6fe97059998480c42b44faefbc9b99.tar.bz2 | |
[PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/DebugInfo/PowerPC/tls.ll')
0 files changed, 0 insertions, 0 deletions