AArch64: add initial NEON support

Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 57 insertions, 0 deletions

diff --git a/test/MC/AArch64/neon-rounding-shift.s b/test/MC/AArch64/neon-rounding-shift.s
new file mode 100644
index 0000000..f3c70d7
--- /dev/null
+++ b/test/MC/AArch64/neon-rounding-shift.s
@@ -0,0 +1,57 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Rounding Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         srshl v0.8b, v1.8b, v2.8b
+         srshl v0.16b, v1.16b, v2.16b
+         srshl v0.4h, v1.4h, v2.4h
+         srshl v0.8h, v1.8h, v2.8h
+         srshl v0.2s, v1.2s, v2.2s
+         srshl v0.4s, v1.4s, v2.4s
+         srshl v0.2d, v1.2d, v2.2d
+
+// CHECK: srshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x54,0x22,0x0e]
+// CHECK: srshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x54,0x22,0x4e]
+// CHECK: srshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x54,0x62,0x0e]
+// CHECK: srshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x54,0x62,0x4e]
+// CHECK: srshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x54,0xa2,0x0e]
+// CHECK: srshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x54,0xa2,0x4e]
+// CHECK: srshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x54,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Rounding Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         urshl v0.8b, v1.8b, v2.8b
+         urshl v0.16b, v1.16b, v2.16b
+         urshl v0.4h, v1.4h, v2.4h
+         urshl v0.8h, v1.8h, v2.8h
+         urshl v0.2s, v1.2s, v2.2s
+         urshl v0.4s, v1.4s, v2.4s
+         urshl v0.2d, v1.2d, v2.2d
+
+// CHECK: urshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x54,0x22,0x2e]
+// CHECK: urshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x54,0x22,0x6e]
+// CHECK: urshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x54,0x62,0x2e]
+// CHECK: urshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x54,0x62,0x6e]
+// CHECK: urshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x54,0xa2,0x2e]
+// CHECK: urshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x54,0xa2,0x6e]
+// CHECK: urshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x54,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Rounding Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         srshl d17, d31, d8
+
+// CHECK: srshl d17, d31, d8      // encoding: [0xf1,0x57,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Rounding Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         urshl d17, d31, d8
+
+// CHECK: urshl d17, d31, d8      // encoding: [0xf1,0x57,0xe8,0x7e]
+