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| author | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-14 01:57:32 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-14 01:57:32 +0000 |
| commit | 082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17 (patch) | |
| tree | b00ca0129ad9280fe864b875e93ea6e5f9c6d01d /test/MC/AArch64 | |
| parent | 2999b2f2ccc3a48c834dffe19bb39c67641a3afd (diff) | |
| download | external_llvm-082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17.zip external_llvm-082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17.tar.gz external_llvm-082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17.tar.bz2 | |
Implement AArch64 NEON instruction set AdvSIMD (table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/AArch64')
| -rw-r--r-- | test/MC/AArch64/neon-diagnostics.s | 48 | ||||
| -rw-r--r-- | test/MC/AArch64/neon-tbl.s | 56 |
2 files changed, 104 insertions, 0 deletions
diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index 0a2332b..12d56a5 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -5928,3 +5928,51 @@ // CHECK-ERROR: error: lane number incompatible with layout // CHECK-ERROR: dup b1, v3.b[16] // CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Table look up +//---------------------------------------------------------------------- + + tbl v0.8b, {v1.8b}, v2.8b + tbl v0.8b, {v1.8b, v2.8b}, v2.8b + tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b + tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b, v2.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b +// CHECK-ERROR: ^ + + tbx v0.8b, {v1.8b}, v2.8b + tbx v0.8b, {v1.8b, v2.8b}, v2.8b + tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b + tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b, v2.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b +// CHECK-ERROR: ^ diff --git a/test/MC/AArch64/neon-tbl.s b/test/MC/AArch64/neon-tbl.s new file mode 100644 index 0000000..ff3e86b --- /dev/null +++ b/test/MC/AArch64/neon-tbl.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions across vector registers +//------------------------------------------------------------------------------ + + tbl v0.8b, {v1.16b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b + tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b + +// CHECK: tbl v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x00,0x02,0x0e] +// CHECK: tbl v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x20,0x02,0x0e] +// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x40,0x02,0x0e] +// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x60,0x02,0x0e] +// CHECK: tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x63,0x02,0x0e] + + tbl v0.16b, {v1.16b}, v2.16b + tbl v0.16b, {v1.16b, v2.16b}, v2.16b + tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b + tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b + tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b + +// CHECK: tbl v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x00,0x02,0x4e] +// CHECK: tbl v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x20,0x02,0x4e] +// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x40,0x02,0x4e] +// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x60,0x02,0x4e] +// CHECK: tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x63,0x02,0x4e] + + tbx v0.8b, {v1.16b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b + tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b + +// CHECK: tbx v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x10,0x02,0x0e] +// CHECK: tbx v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x30,0x02,0x0e] +// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x50,0x02,0x0e] +// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x70,0x02,0x0e] +// CHECK: tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x73,0x02,0x0e] + + tbx v0.16b, {v1.16b}, v2.16b + tbx v0.16b, {v1.16b, v2.16b}, v2.16b + tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b + tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b + tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b + +// CHECK: tbx v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x10,0x02,0x4e] +// CHECK: tbx v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x30,0x02,0x4e] +// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x50,0x02,0x4e] +// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x70,0x02,0x4e] +// CHECK: tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x73,0x02,0x4e] + |