diff options
| author | Hao Liu <Hao.Liu@arm.com> | 2013-09-04 09:28:24 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2013-09-04 09:28:24 +0000 |
| commit | 19fdc268c316b3b0bdcb2b558449819f4f402d6a (patch) | |
| tree | 7e600b5667c314ab009690568492a55b06b90c1b /test/MC/AArch64 | |
| parent | 886631cc2790cc0143966069e613d933914724b4 (diff) | |
| download | external_llvm-19fdc268c316b3b0bdcb2b558449819f4f402d6a.zip external_llvm-19fdc268c316b3b0bdcb2b558449819f4f402d6a.tar.gz external_llvm-19fdc268c316b3b0bdcb2b558449819f4f402d6a.tar.bz2 | |
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/AArch64')
| -rw-r--r-- | test/MC/AArch64/neon-diagnostics.s | 726 | ||||
| -rw-r--r-- | test/MC/AArch64/neon-simd-shift.s | 434 |
2 files changed, 1157 insertions, 3 deletions
diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index bc54b50..52305f1 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -845,12 +845,12 @@ // Vector Saturating Shift Left (Signed and Unsigned Integer) //---------------------------------------------------------------------- // Mismatched vector types - sqshl v0.2s, v15.2s, v16.2d + sqshl v0.2s, v15.4s, v16.2d uqshl v1.8b, v25.4h, v6.8h // CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: sqshl v0.2s, v15.2s, v16.2d -// CHECK-ERROR: ^ +// CHECK-ERROR: sqshl v0.2s, v15.4s, v16.2d +// CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqshl v1.8b, v25.4h, v6.8h // CHECK-ERROR: ^ @@ -1288,3 +1288,723 @@ // CHECK-ERROR: ushll2 v0.2d, v1.4s, #33 // CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + sshr v0.8b, v1.8h, #3 + sshr v0.4h, v1.4s, #3 + sshr v0.2s, v1.2d, #3 + sshr v0.16b, v1.16b, #9 + sshr v0.8h, v1.8h, #17 + sshr v0.4s, v1.4s, #33 + sshr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sshr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sshr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sshr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: sshr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + ushr v0.8b, v1.8h, #3 + ushr v0.4h, v1.4s, #3 + ushr v0.2s, v1.2d, #3 + ushr v0.16b, v1.16b, #9 + ushr v0.8h, v1.8h, #17 + ushr v0.4s, v1.4s, #33 + ushr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: ushr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: ushr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ushr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ushr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ssra v0.8b, v1.8h, #3 + ssra v0.4h, v1.4s, #3 + ssra v0.2s, v1.2d, #3 + ssra v0.16b, v1.16b, #9 + ssra v0.8h, v1.8h, #17 + ssra v0.4s, v1.4s, #33 + ssra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: ssra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: ssra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ssra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ssra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + usra v0.8b, v1.8h, #3 + usra v0.4h, v1.4s, #3 + usra v0.2s, v1.2d, #3 + usra v0.16b, v1.16b, #9 + usra v0.8h, v1.8h, #17 + usra v0.4s, v1.4s, #33 + usra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: usra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: usra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: usra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: usra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right by immediate +//------------------------------------------------------------------------------ + srshr v0.8b, v1.8h, #3 + srshr v0.4h, v1.4s, #3 + srshr v0.2s, v1.2d, #3 + srshr v0.16b, v1.16b, #9 + srshr v0.8h, v1.8h, #17 + srshr v0.4s, v1.4s, #33 + srshr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: srshr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: srshr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: srshr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: srshr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vecotr rounding shift right by immediate +//------------------------------------------------------------------------------ + urshr v0.8b, v1.8h, #3 + urshr v0.4h, v1.4s, #3 + urshr v0.2s, v1.2d, #3 + urshr v0.16b, v1.16b, #9 + urshr v0.8h, v1.8h, #17 + urshr v0.4s, v1.4s, #33 + urshr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: urshr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: urshr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: urshr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: urshr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + srsra v0.8b, v1.8h, #3 + srsra v0.4h, v1.4s, #3 + srsra v0.2s, v1.2d, #3 + srsra v0.16b, v1.16b, #9 + srsra v0.8h, v1.8h, #17 + srsra v0.4s, v1.4s, #33 + srsra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srsra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srsra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srsra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: srsra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: srsra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: srsra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: srsra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ursra v0.8b, v1.8h, #3 + ursra v0.4h, v1.4s, #3 + ursra v0.2s, v1.2d, #3 + ursra v0.16b, v1.16b, #9 + ursra v0.8h, v1.8h, #17 + ursra v0.4s, v1.4s, #33 + ursra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: ursra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: ursra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ursra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ursra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right and insert by immediate +//------------------------------------------------------------------------------ + sri v0.8b, v1.8h, #3 + sri v0.4h, v1.4s, #3 + sri v0.2s, v1.2d, #3 + sri v0.16b, v1.16b, #9 + sri v0.8h, v1.8h, #17 + sri v0.4s, v1.4s, #33 + sri v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sri v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sri v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sri v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sri v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sri v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sri v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: sri v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift left and insert by immediate +//------------------------------------------------------------------------------ + sli v0.8b, v1.8h, #3 + sli v0.4h, v1.4s, #3 + sli v0.2s, v1.2d, #3 + sli v0.16b, v1.16b, #8 + sli v0.8h, v1.8h, #16 + sli v0.4s, v1.4s, #32 + sli v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sli v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sli v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sli v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sli v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sli v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sli v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sli v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift left unsigned by immediate +//------------------------------------------------------------------------------ + sqshlu v0.8b, v1.8h, #3 + sqshlu v0.4h, v1.4s, #3 + sqshlu v0.2s, v1.2d, #3 + sqshlu v0.16b, v1.16b, #8 + sqshlu v0.8h, v1.8h, #16 + sqshlu v0.4s, v1.4s, #32 + sqshlu v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshlu v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshlu v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshlu v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sqshlu v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sqshlu v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sqshlu v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sqshlu v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + sqshl v0.8b, v1.8h, #3 + sqshl v0.4h, v1.4s, #3 + sqshl v0.2s, v1.2d, #3 + sqshl v0.16b, v1.16b, #8 + sqshl v0.8h, v1.8h, #16 + sqshl v0.4s, v1.4s, #32 + sqshl v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sqshl v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sqshl v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sqshl v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sqshl v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + uqshl v0.8b, v1.8h, #3 + uqshl v0.4h, v1.4s, #3 + uqshl v0.2s, v1.2d, #3 + uqshl v0.16b, v1.16b, #8 + uqshl v0.8h, v1.8h, #16 + uqshl v0.4s, v1.4s, #32 + uqshl v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: uqshl v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: uqshl v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: uqshl v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: uqshl v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right narrow by immediate +//------------------------------------------------------------------------------ + shrn v0.8b, v1.8b, #3 + shrn v0.4h, v1.4h, #3 + shrn v0.2s, v1.2s, #3 + shrn2 v0.16b, v1.8h, #17 + shrn2 v0.8h, v1.4s, #33 + shrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: shrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: shrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: shrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqshrun v0.8b, v1.8b, #3 + sqshrun v0.4h, v1.4h, #3 + sqshrun v0.2s, v1.2s, #3 + sqshrun2 v0.16b, v1.8h, #17 + sqshrun2 v0.8h, v1.4s, #33 + sqshrun2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrun v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrun v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrun v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqshrun2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqshrun2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqshrun2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right narrow by immediate +//------------------------------------------------------------------------------ + rshrn v0.8b, v1.8b, #3 + rshrn v0.4h, v1.4h, #3 + rshrn v0.2s, v1.2s, #3 + rshrn2 v0.16b, v1.8h, #17 + rshrn2 v0.8h, v1.4s, #33 + rshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: rshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: rshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: rshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqrshrun v0.8b, v1.8b, #3 + sqrshrun v0.4h, v1.4h, #3 + sqrshrun v0.2s, v1.2s, #3 + sqrshrun2 v0.16b, v1.8h, #17 + sqrshrun2 v0.8h, v1.4s, #33 + sqrshrun2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrun v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrun v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrun v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqrshrun2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqrshrun2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqrshrun2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + sqshrn v0.8b, v1.8b, #3 + sqshrn v0.4h, v1.4h, #3 + sqshrn v0.2s, v1.2s, #3 + sqshrn2 v0.16b, v1.8h, #17 + sqshrn2 v0.8h, v1.4s, #33 + sqshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + uqshrn v0.8b, v1.8b, #3 + uqshrn v0.4h, v1.4h, #3 + uqshrn v0.2s, v1.2s, #3 + uqshrn2 v0.16b, v1.8h, #17 + uqshrn2 v0.8h, v1.4s, #33 + uqshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: uqshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: uqshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: uqshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + sqrshrn v0.8b, v1.8b, #3 + sqrshrn v0.4h, v1.4h, #3 + sqrshrn v0.2s, v1.2s, #3 + sqrshrn2 v0.16b, v1.8h, #17 + sqrshrn2 v0.8h, v1.4s, #33 + sqrshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqrshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqrshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqrshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + uqrshrn v0.8b, v1.8b, #3 + uqrshrn v0.4h, v1.4h, #3 + uqrshrn v0.2s, v1.2s, #3 + uqrshrn2 v0.16b, v1.8h, #17 + uqrshrn2 v0.8h, v1.4s, #33 + uqrshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: uqrshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: uqrshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: uqrshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Fixed-point convert to floating-point +//------------------------------------------------------------------------------ + scvtf v0.2s, v1.2d, #3 + scvtf v0.4s, v1.4h, #3 + scvtf v0.2d, v1.2s, #3 + ucvtf v0.2s, v1.2s, #33 + ucvtf v0.4s, v1.4s, #33 + ucvtf v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.4s, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.2d, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ucvtf v0.2s, v1.2s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ucvtf v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ucvtf v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert to fixed-point +//------------------------------------------------------------------------------ + fcvtzs v0.2s, v1.2d, #3 + fcvtzs v0.4s, v1.4h, #3 + fcvtzs v0.2d, v1.2s, #3 + fcvtzu v0.2s, v1.2s, #33 + fcvtzu v0.4s, v1.4s, #33 + fcvtzu v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.4s, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.2d, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzu v0.2s, v1.2s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzu v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: fcvtzu v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + diff --git a/test/MC/AArch64/neon-simd-shift.s b/test/MC/AArch64/neon-simd-shift.s new file mode 100644 index 0000000..9e6e1aa --- /dev/null +++ b/test/MC/AArch64/neon-simd-shift.s @@ -0,0 +1,434 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + sshr v0.8b, v1.8b, #3 + sshr v0.4h, v1.4h, #3 + sshr v0.2s, v1.2s, #3 + sshr v0.16b, v1.16b, #3 + sshr v0.8h, v1.8h, #3 + sshr v0.4s, v1.4s, #3 + sshr v0.2d, v1.2d, #3 +// CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f] +// CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f] +// CHECK: sshr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x0f] +// CHECK: sshr v0.16b, v1.16b, #3 // encoding: [0x20,0x04,0x0d,0x4f] +// CHECK: sshr v0.8h, v1.8h, #3 // encoding: [0x20,0x04,0x1d,0x4f] +// CHECK: sshr v0.4s, v1.4s, #3 // encoding: [0x20,0x04,0x3d,0x4f] +// CHECK: sshr v0.2d, v1.2d, #3 // encoding: [0x20,0x04,0x7d,0x4f] + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + ushr v0.8b, v1.8b, #3 + ushr v0.4h, v1.4h, #3 + ushr v0.2s, v1.2s, #3 + ushr v0.16b, v1.16b, #3 + ushr v0.8h, v1.8h, #3 + ushr v0.4s, v1.4s, #3 + ushr v0.2d, v1.2d, #3 + +// CHECK: ushr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x2f] +// CHECK: ushr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x2f] +// CHECK: ushr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x2f] +// CHECK: ushr v0.16b, v1.16b, #3 // encoding: [0x20,0x04,0x0d,0x6f] +// CHECK: ushr v0.8h, v1.8h, #3 // encoding: [0x20,0x04,0x1d,0x6f] +// CHECK: ushr v0.4s, v1.4s, #3 // encoding: [0x20,0x04,0x3d,0x6f] +// CHECK: ushr v0.2d, v1.2d, #3 // encoding: [0x20,0x04,0x7d,0x6f] + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ssra v0.8b, v1.8b, #3 + ssra v0.4h, v1.4h, #3 + ssra v0.2s, v1.2s, #3 + ssra v0.16b, v1.16b, #3 + ssra v0.8h, v1.8h, #3 + ssra v0.4s, v1.4s, #3 + ssra v0.2d, v1.2d, #3 + +// CHECK: ssra v0.8b, v1.8b, #3 // encoding: [0x20,0x14,0x0d,0x0f] +// CHECK: ssra v0.4h, v1.4h, #3 // encoding: [0x20,0x14,0x1d,0x0f] +// CHECK: ssra v0.2s, v1.2s, #3 // encoding: [0x20,0x14,0x3d,0x0f] +// CHECK: ssra v0.16b, v1.16b, #3 // encoding: [0x20,0x14,0x0d,0x4f] +// CHECK: ssra v0.8h, v1.8h, #3 // encoding: [0x20,0x14,0x1d,0x4f] +// CHECK: ssra v0.4s, v1.4s, #3 // encoding: [0x20,0x14,0x3d,0x4f] +// CHECK: ssra v0.2d, v1.2d, #3 // encoding: [0x20,0x14,0x7d,0x4f] + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + usra v0.8b, v1.8b, #3 + usra v0.4h, v1.4h, #3 + usra v0.2s, v1.2s, #3 + usra v0.16b, v1.16b, #3 + usra v0.8h, v1.8h, #3 + usra v0.4s, v1.4s, #3 + usra v0.2d, v1.2d, #3 + +// CHECK: usra v0.8b, v1.8b, #3 // encoding: [0x20,0x14,0x0d,0x2f] +// CHECK: usra v0.4h, v1.4h, #3 // encoding: [0x20,0x14,0x1d,0x2f] +// CHECK: usra v0.2s, v1.2s, #3 // encoding: [0x20,0x14,0x3d,0x2f] +// CHECK: usra v0.16b, v1.16b, #3 // encoding: [0x20,0x14,0x0d,0x6f] +// CHECK: usra v0.8h, v1.8h, #3 // encoding: [0x20,0x14,0x1d,0x6f] +// CHECK: usra v0.4s, v1.4s, #3 // encoding: [0x20,0x14,0x3d,0x6f] +// CHECK: usra v0.2d, v1.2d, #3 // encoding: [0x20,0x14,0x7d,0x6f] + +//------------------------------------------------------------------------------ +// Vector rounding shift right by immediate +//------------------------------------------------------------------------------ + srshr v0.8b, v1.8b, #3 + srshr v0.4h, v1.4h, #3 + srshr v0.2s, v1.2s, #3 + srshr v0.16b, v1.16b, #3 + srshr v0.8h, v1.8h, #3 + srshr v0.4s, v1.4s, #3 + srshr v0.2d, v1.2d, #3 + +// CHECK: srshr v0.8b, v1.8b, #3 // encoding: [0x20,0x24,0x0d,0x0f] +// CHECK: srshr v0.4h, v1.4h, #3 // encoding: [0x20,0x24,0x1d,0x0f] +// CHECK: srshr v0.2s, v1.2s, #3 // encoding: [0x20,0x24,0x3d,0x0f] +// CHECK: srshr v0.16b, v1.16b, #3 // encoding: [0x20,0x24,0x0d,0x4f] +// CHECK: srshr v0.8h, v1.8h, #3 // encoding: [0x20,0x24,0x1d,0x4f] +// CHECK: srshr v0.4s, v1.4s, #3 // encoding: [0x20,0x24,0x3d,0x4f] +// CHECK: srshr v0.2d, v1.2d, #3 // encoding: [0x20,0x24,0x7d,0x4f] + + +//------------------------------------------------------------------------------ +// Vecotr rounding shift right by immediate +//------------------------------------------------------------------------------ + urshr v0.8b, v1.8b, #3 + urshr v0.4h, v1.4h, #3 + urshr v0.2s, v1.2s, #3 + urshr v0.16b, v1.16b, #3 + urshr v0.8h, v1.8h, #3 + urshr v0.4s, v1.4s, #3 + urshr v0.2d, v1.2d, #3 + +// CHECK: urshr v0.8b, v1.8b, #3 // encoding: [0x20,0x24,0x0d,0x2f] +// CHECK: urshr v0.4h, v1.4h, #3 // encoding: [0x20,0x24,0x1d,0x2f] +// CHECK: urshr v0.2s, v1.2s, #3 // encoding: [0x20,0x24,0x3d,0x2f] +// CHECK: urshr v0.16b, v1.16b, #3 // encoding: [0x20,0x24,0x0d,0x6f] +// CHECK: urshr v0.8h, v1.8h, #3 // encoding: [0x20,0x24,0x1d,0x6f] +// CHECK: urshr v0.4s, v1.4s, #3 // encoding: [0x20,0x24,0x3d,0x6f] +// CHECK: urshr v0.2d, v1.2d, #3 // encoding: [0x20,0x24,0x7d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + srsra v0.8b, v1.8b, #3 + srsra v0.4h, v1.4h, #3 + srsra v0.2s, v1.2s, #3 + srsra v0.16b, v1.16b, #3 + srsra v0.8h, v1.8h, #3 + srsra v0.4s, v1.4s, #3 + srsra v0.2d, v1.2d, #3 + +// CHECK: srsra v0.8b, v1.8b, #3 // encoding: [0x20,0x34,0x0d,0x0f] +// CHECK: srsra v0.4h, v1.4h, #3 // encoding: [0x20,0x34,0x1d,0x0f] +// CHECK: srsra v0.2s, v1.2s, #3 // encoding: [0x20,0x34,0x3d,0x0f] +// CHECK: srsra v0.16b, v1.16b, #3 // encoding: [0x20,0x34,0x0d,0x4f] +// CHECK: srsra v0.8h, v1.8h, #3 // encoding: [0x20,0x34,0x1d,0x4f] +// CHECK: srsra v0.4s, v1.4s, #3 // encoding: [0x20,0x34,0x3d,0x4f] +// CHECK: srsra v0.2d, v1.2d, #3 // encoding: [0x20,0x34,0x7d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ursra v0.8b, v1.8b, #3 + ursra v0.4h, v1.4h, #3 + ursra v0.2s, v1.2s, #3 + ursra v0.16b, v1.16b, #3 + ursra v0.8h, v1.8h, #3 + ursra v0.4s, v1.4s, #3 + ursra v0.2d, v1.2d, #3 + +// CHECK: ursra v0.8b, v1.8b, #3 // encoding: [0x20,0x34,0x0d,0x2f] +// CHECK: ursra v0.4h, v1.4h, #3 // encoding: [0x20,0x34,0x1d,0x2f] +// CHECK: ursra v0.2s, v1.2s, #3 // encoding: [0x20,0x34,0x3d,0x2f] +// CHECK: ursra v0.16b, v1.16b, #3 // encoding: [0x20,0x34,0x0d,0x6f] +// CHECK: ursra v0.8h, v1.8h, #3 // encoding: [0x20,0x34,0x1d,0x6f] +// CHECK: ursra v0.4s, v1.4s, #3 // encoding: [0x20,0x34,0x3d,0x6f] +// CHECK: ursra v0.2d, v1.2d, #3 // encoding: [0x20,0x34,0x7d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector shift right and insert by immediate +//------------------------------------------------------------------------------ + sri v0.8b, v1.8b, #3 + sri v0.4h, v1.4h, #3 + sri v0.2s, v1.2s, #3 + sri v0.16b, v1.16b, #3 + sri v0.8h, v1.8h, #3 + sri v0.4s, v1.4s, #3 + sri v0.2d, v1.2d, #3 + +// CHECK: sri v0.8b, v1.8b, #3 // encoding: [0x20,0x44,0x0d,0x2f] +// CHECK: sri v0.4h, v1.4h, #3 // encoding: [0x20,0x44,0x1d,0x2f] +// CHECK: sri v0.2s, v1.2s, #3 // encoding: [0x20,0x44,0x3d,0x2f] +// CHECK: sri v0.16b, v1.16b, #3 // encoding: [0x20,0x44,0x0d,0x6f] +// CHECK: sri v0.8h, v1.8h, #3 // encoding: [0x20,0x44,0x1d,0x6f] +// CHECK: sri v0.4s, v1.4s, #3 // encoding: [0x20,0x44,0x3d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector shift left and insert by immediate +//------------------------------------------------------------------------------ + sli v0.8b, v1.8b, #3 + sli v0.4h, v1.4h, #3 + sli v0.2s, v1.2s, #3 + sli v0.16b, v1.16b, #3 + sli v0.8h, v1.8h, #3 + sli v0.4s, v1.4s, #3 + sli v0.2d, v1.2d, #3 + +// CHECK: sli v0.8b, v1.8b, #3 // encoding: [0x20,0x54,0x0b,0x2f] +// CHECK: sli v0.4h, v1.4h, #3 // encoding: [0x20,0x54,0x13,0x2f] +// CHECK: sli v0.2s, v1.2s, #3 // encoding: [0x20,0x54,0x23,0x2f] +// CHECK: sli v0.16b, v1.16b, #3 // encoding: [0x20,0x54,0x0b,0x6f] +// CHECK: sli v0.8h, v1.8h, #3 // encoding: [0x20,0x54,0x13,0x6f] +// CHECK: sli v0.4s, v1.4s, #3 // encoding: [0x20,0x54,0x23,0x6f] +// CHECK: sli v0.2d, v1.2d, #3 // encoding: [0x20,0x54,0x43,0x6f] + +//------------------------------------------------------------------------------ +// Vector saturating shift left unsigned by immediate +//------------------------------------------------------------------------------ + sqshlu v0.8b, v1.8b, #3 + sqshlu v0.4h, v1.4h, #3 + sqshlu v0.2s, v1.2s, #3 + sqshlu v0.16b, v1.16b, #3 + sqshlu v0.8h, v1.8h, #3 + sqshlu v0.4s, v1.4s, #3 + sqshlu v0.2d, v1.2d, #3 + +// CHECK: sqshlu v0.8b, v1.8b, #3 // encoding: [0x20,0x64,0x0b,0x2f] +// CHECK: sqshlu v0.4h, v1.4h, #3 // encoding: [0x20,0x64,0x13,0x2f] +// CHECK: sqshlu v0.2s, v1.2s, #3 // encoding: [0x20,0x64,0x23,0x2f] +// CHECK: sqshlu v0.16b, v1.16b, #3 // encoding: [0x20,0x64,0x0b,0x6f] +// CHECK: sqshlu v0.8h, v1.8h, #3 // encoding: [0x20,0x64,0x13,0x6f] +// CHECK: sqshlu v0.4s, v1.4s, #3 // encoding: [0x20,0x64,0x23,0x6f] +// CHECK: sqshlu v0.2d, v1.2d, #3 // encoding: [0x20,0x64,0x43,0x6f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + sqshl v0.8b, v1.8b, #3 + sqshl v0.4h, v1.4h, #3 + sqshl v0.2s, v1.2s, #3 + sqshl v0.16b, v1.16b, #3 + sqshl v0.8h, v1.8h, #3 + sqshl v0.4s, v1.4s, #3 + sqshl v0.2d, v1.2d, #3 + +// CHECK: sqshl v0.8b, v1.8b, #3 // encoding: [0x20,0x74,0x0b,0x0f] +// CHECK: sqshl v0.4h, v1.4h, #3 // encoding: [0x20,0x74,0x13,0x0f] +// CHECK: sqshl v0.2s, v1.2s, #3 // encoding: [0x20,0x74,0x23,0x0f] +// CHECK: sqshl v0.16b, v1.16b, #3 // encoding: [0x20,0x74,0x0b,0x4f] +// CHECK: sqshl v0.8h, v1.8h, #3 // encoding: [0x20,0x74,0x13,0x4f] +// CHECK: sqshl v0.4s, v1.4s, #3 // encoding: [0x20,0x74,0x23,0x4f] +// CHECK: sqshl v0.2d, v1.2d, #3 // encoding: [0x20,0x74,0x43,0x4f] + + + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + uqshl v0.8b, v1.8b, #3 + uqshl v0.4h, v1.4h, #3 + uqshl v0.2s, v1.2s, #3 + uqshl v0.16b, v1.16b, #3 + uqshl v0.8h, v1.8h, #3 + uqshl v0.4s, v1.4s, #3 + uqshl v0.2d, v1.2d, #3 + +// CHECK: uqshl v0.8b, v1.8b, #3 // encoding: [0x20,0x74,0x0b,0x2f] +// CHECK: uqshl v0.4h, v1.4h, #3 // encoding: [0x20,0x74,0x13,0x2f] +// CHECK: uqshl v0.2s, v1.2s, #3 // encoding: [0x20,0x74,0x23,0x2f] +// CHECK: uqshl v0.16b, v1.16b, #3 // encoding: [0x20,0x74,0x0b,0x6f] +// CHECK: uqshl v0.8h, v1.8h, #3 // encoding: [0x20,0x74,0x13,0x6f] +// CHECK: uqshl v0.4s, v1.4s, #3 // encoding: [0x20,0x74,0x23,0x6f] +// CHECK: uqshl v0.2d, v1.2d, #3 // encoding: [0x20,0x74,0x43,0x6f] + + +//------------------------------------------------------------------------------ +// Vector shift right narrow by immediate +//------------------------------------------------------------------------------ + shrn v0.8b, v1.8h, #3 + shrn v0.4h, v1.4s, #3 + shrn v0.2s, v1.2d, #3 + shrn2 v0.16b, v1.8h, #3 + shrn2 v0.8h, v1.4s, #3 + shrn2 v0.4s, v1.2d, #3 + +// CHECK: shrn v0.8b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x0f] +// CHECK: shrn v0.4h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x0f] +// CHECK: shrn v0.2s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x0f] +// CHECK: shrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x4f] +// CHECK: shrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x4f] +// CHECK: shrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x4f] + +//------------------------------------------------------------------------------ +// Vector saturating shift right unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqshrun v0.8b, v1.8h, #3 + sqshrun v0.4h, v1.4s, #3 + sqshrun v0.2s, v1.2d, #3 + sqshrun2 v0.16b, v1.8h, #3 + sqshrun2 v0.8h, v1.4s, #3 + sqshrun2 v0.4s, v1.2d, #3 + +// CHECK: sqshrun v0.8b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x2f] +// CHECK: sqshrun v0.4h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x2f] +// CHECK: sqshrun v0.2s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x2f] +// CHECK: sqshrun2 v0.16b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x6f] +// CHECK: sqshrun2 v0.8h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x6f] +// CHECK: sqshrun2 v0.4s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x6f] + +//------------------------------------------------------------------------------ +// Vector rounding shift right narrow by immediate +//------------------------------------------------------------------------------ + rshrn v0.8b, v1.8h, #3 + rshrn v0.4h, v1.4s, #3 + rshrn v0.2s, v1.2d, #3 + rshrn2 v0.16b, v1.8h, #3 + rshrn2 v0.8h, v1.4s, #3 + rshrn2 v0.4s, v1.2d, #3 + +// CHECK: rshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x0f] +// CHECK: rshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x0f] +// CHECK: rshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x0f] +// CHECK: rshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x4f] +// CHECK: rshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x4f] +// CHECK: rshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqrshrun v0.8b, v1.8h, #3 + sqrshrun v0.4h, v1.4s, #3 + sqrshrun v0.2s, v1.2d, #3 + sqrshrun2 v0.16b, v1.8h, #3 + sqrshrun2 v0.8h, v1.4s, #3 + sqrshrun2 v0.4s, v1.2d, #3 + +// CHECK: sqrshrun v0.8b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x2f] +// CHECK: sqrshrun v0.4h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x2f] +// CHECK: sqrshrun v0.2s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x2f] +// CHECK: sqrshrun2 v0.16b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x6f] +// CHECK: sqrshrun2 v0.8h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x6f] +// CHECK: sqrshrun2 v0.4s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + sqshrn v0.8b, v1.8h, #3 + sqshrn v0.4h, v1.4s, #3 + sqshrn v0.2s, v1.2d, #3 + sqshrn2 v0.16b, v1.8h, #3 + sqshrn2 v0.8h, v1.4s, #3 + sqshrn2 v0.4s, v1.2d, #3 + +// CHECK: sqshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x0f] +// CHECK: sqshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x0f] +// CHECK: sqshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x0f] +// CHECK: sqshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x4f] +// CHECK: sqshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x4f] +// CHECK: sqshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + uqshrn v0.8b, v1.8h, #3 + uqshrn v0.4h, v1.4s, #3 + uqshrn v0.2s, v1.2d, #3 + uqshrn2 v0.16b, v1.8h, #3 + uqshrn2 v0.8h, v1.4s, #3 + uqshrn2 v0.4s, v1.2d, #3 + +// CHECK: uqshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x2f] +// CHECK: uqshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x2f] +// CHECK: uqshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x2f] +// CHECK: uqshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x6f] +// CHECK: uqshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x6f] +// CHECK: uqshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x6f] + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + sqrshrn v0.8b, v1.8h, #3 + sqrshrn v0.4h, v1.4s, #3 + sqrshrn v0.2s, v1.2d, #3 + sqrshrn2 v0.16b, v1.8h, #3 + sqrshrn2 v0.8h, v1.4s, #3 + sqrshrn2 v0.4s, v1.2d, #3 + +// CHECK: sqrshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x0f] +// CHECK: sqrshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x0f] +// CHECK: sqrshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x0f] +// CHECK: sqrshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x4f] +// CHECK: sqrshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x4f] +// CHECK: sqrshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + uqrshrn v0.8b, v1.8h, #3 + uqrshrn v0.4h, v1.4s, #3 + uqrshrn v0.2s, v1.2d, #3 + uqrshrn2 v0.16b, v1.8h, #3 + uqrshrn2 v0.8h, v1.4s, #3 + uqrshrn2 v0.4s, v1.2d, #3 + +// CHECK: uqrshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x2f] +// CHECK: uqrshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x2f] +// CHECK: uqrshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x2f] +// CHECK: uqrshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x6f] +// CHECK: uqrshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x6f] +// CHECK: uqrshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x6f] + + +//------------------------------------------------------------------------------ +// Fixed-point convert to floating-point +//------------------------------------------------------------------------------ + scvtf v0.2s, v1.2s, #3 + scvtf v0.4s, v1.4s, #3 + scvtf v0.2d, v1.2d, #3 + ucvtf v0.2s, v1.2s, #3 + ucvtf v0.4s, v1.4s, #3 + ucvtf v0.2d, v1.2d, #3 + +// CHECK: scvtf v0.2s, v1.2s, #3 // encoding: [0x20,0xe4,0x3d,0x0f] +// CHECK: scvtf v0.4s, v1.4s, #3 // encoding: [0x20,0xe4,0x3d,0x4f] +// CHECK: scvtf v0.2d, v1.2d, #3 // encoding: [0x20,0xe4,0x7d,0x4f] +// CHECK: ucvtf v0.2s, v1.2s, #3 // encoding: [0x20,0xe4,0x3d,0x2f] +// CHECK: ucvtf v0.4s, v1.4s, #3 // encoding: [0x20,0xe4,0x3d,0x6f] +// CHECK: ucvtf v0.2d, v1.2d, #3 // encoding: [0x20,0xe4,0x7d,0x6f] + +//------------------------------------------------------------------------------ +// Floating-point convert to fixed-point +//------------------------------------------------------------------------------ + fcvtzs v0.2s, v1.2s, #3 + fcvtzs v0.4s, v1.4s, #3 + fcvtzs v0.2d, v1.2d, #3 + fcvtzu v0.2s, v1.2s, #3 + fcvtzu v0.4s, v1.4s, #3 + fcvtzu v0.2d, v1.2d, #3 + + +// CHECK: fcvtzs v0.2s, v1.2s, #3 // encoding: [0x20,0xfc,0x3d,0x0f] +// CHECK: fcvtzs v0.4s, v1.4s, #3 // encoding: [0x20,0xfc,0x3d,0x4f] +// CHECK: fcvtzs v0.2d, v1.2d, #3 // encoding: [0x20,0xfc,0x7d,0x4f] +// CHECK: fcvtzu v0.2s, v1.2s, #3 // encoding: [0x20,0xfc,0x3d,0x2f] +// CHECK: fcvtzu v0.4s, v1.4s, #3 // encoding: [0x20,0xfc,0x3d,0x6f] +// CHECK: fcvtzu v0.2d, v1.2d, #3 // encoding: [0x20,0xfc,0x7d,0x6f] + |