diff options
author | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-06 11:46:36 -0700 |
---|---|---|
committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-18 10:52:30 -0700 |
commit | 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 (patch) | |
tree | c0104029af14e9f47c2ef58ca60e6137691f3c9b /test/MC/ARM/basic-arm-instructions-v8.1a.s | |
parent | e1bc145815f4334641be19f1c45ecf85d25b6e5a (diff) | |
download | external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.zip external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.gz external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.bz2 |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
Diffstat (limited to 'test/MC/ARM/basic-arm-instructions-v8.1a.s')
-rw-r--r-- | test/MC/ARM/basic-arm-instructions-v8.1a.s | 64 |
1 files changed, 48 insertions, 16 deletions
diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s index f46057b6..005f27b 100644 --- a/test/MC/ARM/basic-arm-instructions-v8.1a.s +++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s @@ -43,28 +43,28 @@ vqrdmlah.s16 d0, d1, d2 //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 d0, d1, d2 //CHECK-V8: ^ vqrdmlah.s32 d0, d1, d2 //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 d0, d1, d2 //CHECK-V8: ^ vqrdmlah.s16 q0, q1, q2 //CHECK-V81aARM: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x54,0x0b,0x12,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 q0, q1, q2 //CHECK-V8: ^ vqrdmlah.s32 q2, q3, q0 //CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 q2, q3, q0 //CHECK-V8: ^ @@ -72,28 +72,28 @@ vqrdmlsh.s16 d7, d6, d5 //CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 d7, d6, d5 //CHECK-V8: ^ vqrdmlsh.s32 d0, d1, d2 //CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x12,0x0c,0x21,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 d0, d1, d2 //CHECK-V8: ^ vqrdmlsh.s16 q0, q1, q2 //CHECK-V81aARM: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 q0, q1, q2 //CHECK-V8: ^ vqrdmlsh.s32 q3, q4, q5 //CHECK-V81aARM: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x5a,0x6c,0x28,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x28,0xff,0x5a,0x6c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 q3, q4, q5 //CHECK-V8: ^ @@ -119,28 +119,28 @@ vqrdmlah.s16 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x42,0x0e,0x91,0xf2] //CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlah.s32 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0x42,0x0e,0xa1,0xf2] //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlah.s16 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x42,0x0e,0x92,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 q0, q1, d2[0] //CHECK-V8: ^ vqrdmlah.s32 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0x42,0x0e,0xa2,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 q0, q1, d2[0] //CHECK-V8: ^ @@ -148,27 +148,59 @@ vqrdmlsh.s16 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x42,0x0f,0x91,0xf2] //CHECK-V81aTHUMB: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlsh.s32 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0x42,0x0f,0xa1,0xf2] //CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlsh.s16 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x42,0x0f,0x92,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 q0, q1, d2[0] //CHECK-V8: ^ vqrdmlsh.s32 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0x42,0x0f,0xa2,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0] //CHECK-V8: ^ + + setpan #0 +//CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6] +//CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1] +//CHECK-V8: error: instruction requires: armv8.1a +//CHECK-V8: setpan #0 +//CHECK-V8: ^ + + setpan #1 +//CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6] +//CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1] +//CHECK-V8: error: instruction requires: armv8.1a +//CHECK-V8: setpan #1 +//CHECK-V8: ^ + setpan + setpan #-1 + setpan #2 +//CHECK-ERROR: error: too few operands for instruction +//CHECK-ERROR: setpan +//CHECK-ERROR: ^ +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR: setpan #-1 +//CHECK-ERROR: ^ +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR: setpan #2 +//CHECK-ERROR: ^ + + it eq + setpaneq #0 +//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified +//CHECK-THUMB-ERROR: setpaneq #0 +//CHECK-THUMB-ERROR: ^ |