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authorJim Grosbach <grosbach@apple.com>2011-08-10 20:29:19 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-10 20:29:19 +0000
commit2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 (patch)
tree900ad82ef8e9db3dba4032a50e5b77d5629ba8b8 /test/MC/ARM
parente2d8cf77c8df45768a3902a97cd357dcf2a5d719 (diff)
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ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
-rw-r--r--test/MC/ARM/arm-memory-instructions.s14
-rw-r--r--test/MC/ARM/diagnostics.s14
2 files changed, 28 insertions, 0 deletions
diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s
index 961f24f..a216a11 100644
--- a/test/MC/ARM/arm-memory-instructions.s
+++ b/test/MC/ARM/arm-memory-instructions.s
@@ -105,3 +105,17 @@ _func:
@ CHECK: ldrbt r2, [r8], #-8 @ encoding: [0x08,0x20,0x78,0xe4]
@ CHECK: ldrbt r8, [r7], r6 @ encoding: [0x06,0x80,0xf7,0xe6]
@ CHECK: ldrbt r1, [r2], -r6, lsl #12 @ encoding: [0x06,0x16,0x72,0xe6]
+
+
+@------------------------------------------------------------------------------
+@ LDRD (immediate)
+@------------------------------------------------------------------------------
+ ldrd r3, r4, [r5]
+ ldrd r7, r8, [r2, #15]
+ ldrd r1, r2, [r9, #32]!
+ ldrd r6, r7, [r1], #8
+
+@ CHECK: ldrd r3, r4, [r5] @ encoding: [0xd0,0x30,0xc5,0xe1]
+@ CHECK: ldrd r7, r8, [r2, #15] @ encoding: [0xdf,0x70,0xc2,0xe1]
+@ CHECK: ldrd r1, r2, [r9, #32]! @ encoding: [0xd0,0x12,0xe9,0xe1]
+@ CHECK: ldrd r6, r7, [r1], #8 @ encoding: [0xd8,0x60,0xc1,0xe0]
diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index cc24416..da1b885 100644
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -283,3 +283,17 @@
@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17
@ CHECK-ERRORS: ^
+
+ @ Out of order Rt/Rt2 operands for ldrd
+ ldrd r4, r3, [r8]
+ ldrd r4, r3, [r8, #8]!
+ ldrd r4, r3, [r8], #8
+@ CHECK-ERRORS: error: destination operands must be sequential
+@ CHECK-ERRORS: ldrd r4, r3, [r8]
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: destination operands must be sequential
+@ CHECK-ERRORS: ldrd r4, r3, [r8, #8]!
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: destination operands must be sequential
+@ CHECK-ERRORS: ldrd r4, r3, [r8], #8
+@ CHECK-ERRORS: ^