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author | Bernard Ogden <bogden@arm.com> | 2013-10-29 09:47:35 +0000 |
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committer | Bernard Ogden <bogden@arm.com> | 2013-10-29 09:47:35 +0000 |
commit | 47c6d17b1cce85ba30471b2270419e35ba3d5653 (patch) | |
tree | f4eca547dd2a067e2e570a49f10ea510b68a2104 /test/MC/ARM | |
parent | 72202297a90563ec3eedd3015395c8d1a8db0a87 (diff) | |
download | external_llvm-47c6d17b1cce85ba30471b2270419e35ba3d5653.zip external_llvm-47c6d17b1cce85ba30471b2270419e35ba3d5653.tar.gz external_llvm-47c6d17b1cce85ba30471b2270419e35ba3d5653.tar.bz2 |
ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.
Differential Revision: http://llvm-reviews.chandlerc.com/D2036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
-rw-r--r-- | test/MC/ARM/crc32-thumb.s | 19 | ||||
-rw-r--r-- | test/MC/ARM/crc32.s | 19 |
2 files changed, 26 insertions, 12 deletions
diff --git a/test/MC/ARM/crc32-thumb.s b/test/MC/ARM/crc32-thumb.s index e0f39c3..3a0e7a9 100644 --- a/test/MC/ARM/crc32-thumb.s +++ b/test/MC/ARM/crc32-thumb.s @@ -1,5 +1,6 @@ @ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 +@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC crc32b r0, r1, r2 crc32h r0, r1, r2 crc32w r0, r1, r2 @@ -7,9 +8,12 @@ @ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0] @ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0] @ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0] -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc crc32cb r0, r1, r2 crc32ch r0, r1, r2 @@ -18,6 +22,9 @@ @ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0] -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc diff --git a/test/MC/ARM/crc32.s b/test/MC/ARM/crc32.s index eeb6fe8..45a1f0c 100644 --- a/test/MC/ARM/crc32.s +++ b/test/MC/ARM/crc32.s @@ -1,5 +1,6 @@ @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 +@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC crc32b r0, r1, r2 crc32h r0, r1, r2 crc32w r0, r1, r2 @@ -7,9 +8,12 @@ @ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1] @ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1] @ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1] -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc crc32cb r0, r1, r2 crc32ch r0, r1, r2 @@ -18,6 +22,9 @@ @ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1] -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 -@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-V7: error: instruction requires: crc armv8 +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc +@ CHECK-NOCRC: error: instruction requires: crc |