diff options
| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-27 10:30:18 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-27 10:30:18 +0000 |
| commit | 6b968eccd79409b0986f394fa597101cf79433d8 (patch) | |
| tree | fa34d002d149da088ab57d90c969ef34cee886c2 /test/MC/ARM | |
| parent | ba616ef0236a11239a0a2c174627dcdc4ab63434 (diff) | |
| download | external_llvm-6b968eccd79409b0986f394fa597101cf79433d8.zip external_llvm-6b968eccd79409b0986f394fa597101cf79433d8.tar.gz external_llvm-6b968eccd79409b0986f394fa597101cf79433d8.tar.bz2 | |
ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!
As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.
If this constraint is not met the result of executing the instruction will be unpredictable.
Fixes rdar://14479780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
| -rw-r--r-- | test/MC/ARM/thumb2-ldrd.s | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/test/MC/ARM/thumb2-ldrd.s b/test/MC/ARM/thumb2-ldrd.s new file mode 100644 index 0000000..4463c21 --- /dev/null +++ b/test/MC/ARM/thumb2-ldrd.s @@ -0,0 +1,9 @@ +// RUN: not llvm-mc -arch thumb -mattr=+thumb2 \ +// RUN: < %s >/dev/null 2> %t +// RUN: grep "error: destination operands can't be identical" %t | count 4 +// rdar://14479780 + +ldrd r0, r0, [pc, #0] +ldrd r0, r0, [r1, #4] +ldrd r0, r0, [r1], #4 +ldrd r0, r0, [r1, #4]! |