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| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-07-03 20:38:01 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-07-03 20:38:01 +0000 |
| commit | 79c163d6ddeb84ea1743eca0644688951bfc5a97 (patch) | |
| tree | 467dc3af27ee3b9bf1e6f11395e7f7fc25e46f6f /test/MC/ARM | |
| parent | 08ebdc73de5e3396bc17b928ad16af523837e660 (diff) | |
| download | external_llvm-79c163d6ddeb84ea1743eca0644688951bfc5a97.zip external_llvm-79c163d6ddeb84ea1743eca0644688951bfc5a97.tar.gz external_llvm-79c163d6ddeb84ea1743eca0644688951bfc5a97.tar.bz2 | |
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.
The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.
This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.
Fixes <rdar://problem/14224440>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index c331d5d..9136aa5 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -79,6 +79,7 @@ _func: add r0, r0, #32 adds r2, r2, #56 adds r2, #56 + add r1, r7, #0xcbcbcbcb adds.w r2, #-16 adds.w r2, r2, #-16 @@ -101,6 +102,7 @@ _func: @ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00] @ CHECK: adds r2, #56 @ encoding: [0x38,0x32] @ CHECK: adds r2, #56 @ encoding: [0x38,0x32] +@ CHECK: add.w r1, r7, #3419130827 @ encoding: [0x07,0xf1,0xcb,0x31] @ CHECK: subs.w r2, r2, #16 @ encoding: [0xb2,0xf1,0x10,0x02] @ CHECK: subs.w r2, r2, #16 @ encoding: [0xb2,0xf1,0x10,0x02] |