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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 21:22:52 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2015-04-10 21:23:04 +0000 |
| commit | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/MC/Disassembler/ARM/armv8.1a.txt | |
| parent | c75239e6119d0f9a74c57099d91cbc9bde56bf33 (diff) | |
| parent | 4c5e43da7792f75567b693105cc53e3f1992ad98 (diff) | |
| download | external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.zip external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.tar.gz external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.tar.bz2 | |
Merge "Update aosp/master llvm for rebase to r233350"
Diffstat (limited to 'test/MC/Disassembler/ARM/armv8.1a.txt')
| -rw-r--r-- | test/MC/Disassembler/ARM/armv8.1a.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/armv8.1a.txt b/test/MC/Disassembler/ARM/armv8.1a.txt new file mode 100644 index 0000000..de0c89e --- /dev/null +++ b/test/MC/Disassembler/ARM/armv8.1a.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a +# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8 + +[0x54,0x0b,0x12,0xf3] +[0x12,0x0b,0x21,0xf3] +[0x54,0x0c,0x12,0xf3] +[0x12,0x0c,0x21,0xf3] +# CHECK-V81a: vqrdmlah.s16 q0, q1, q2 +# CHECK-V81a: vqrdmlah.s32 d0, d1, d2 +# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2 +# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x54,0x0b,0x12,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x12,0x0b,0x21,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x54,0x0c,0x12,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x12,0x0c,0x21,0xf3] + +[0x42,0x0e,0x92,0xf3] +[0x42,0x0e,0xa1,0xf2] +[0x42,0x0f,0x92,0xf3] +[0x42,0x0f,0xa1,0xf2] +# CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0] +# CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0] +# CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0] +# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0e,0x92,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0e,0xa1,0xf2] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0f,0x92,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0f,0xa1,0xf2] |