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| author | Tim Northover <tnorthover@apple.com> | 2013-07-19 10:05:04 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-07-19 10:05:04 +0000 |
| commit | 38c6ff6c111fcc53debb9e2880f89e2dd0676217 (patch) | |
| tree | 4af833fe6c478fcfd619799e9684b171961d072a /test/MC/Disassembler/ARM/invalid-MSRi-arm.txt | |
| parent | c09228dba3be474d9835cad19adc4419224872f3 (diff) | |
| download | external_llvm-38c6ff6c111fcc53debb9e2880f89e2dd0676217.zip external_llvm-38c6ff6c111fcc53debb9e2880f89e2dd0676217.tar.gz external_llvm-38c6ff6c111fcc53debb9e2880f89e2dd0676217.tar.bz2 | |
Improve llvm-mc disassembler mode and refactor ARM tests to use it
This allows "llvm-mc -disassemble" to accept two new features:
+ Using comma as a byte separator
+ Grouping bytes with '[' and ']' pairs.
The behaviour outside a [...] group is unchanged. But within the group once
llvm-mc encounters a true error, it stops rather than trying to resynchronise
the stream at the next byte. This is more useful for disassembly tests, where
we have an almost-instruction in mind and don't care what the misaligned
interpretation would be. Particularly if it means llvm-mc won't actually see
the next intended almost-instruction.
As a side effect, this means llvm-mc can disassemble its own -show-encoding
output if copy-pasted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186661 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler/ARM/invalid-MSRi-arm.txt')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-MSRi-arm.txt | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt deleted file mode 100644 index 901667a..0000000 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) -# The hints instructions have more specific encodings, so if mask == 0, -# we should reject this as an invalid instruction. -0xa7 0xf1 0x20 0x3 |