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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/MC/Disassembler/ARM/invalid-armv8.1a.txt | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/MC/Disassembler/ARM/invalid-armv8.1a.txt')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-armv8.1a.txt | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-armv8.1a.txt b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt new file mode 100644 index 0000000..1a9f275 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt @@ -0,0 +1,83 @@ +# RUN: not llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s + +# Check, if sizes 00 and 11 are undefined for RDMA +[0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0 +# CHECK-NEXT: ^ + +[0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0] +# CHECK-NEXT: ^ + + +[0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0] +# CHECK-NEXT: ^ |