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authorJames Molloy <james.molloy@arm.com>2011-09-07 19:42:28 +0000
committerJames Molloy <james.molloy@arm.com>2011-09-07 19:42:28 +0000
commita5d585685493d85d5cb72b831a68ec747ae55a86 (patch)
tree99483c51a38667c6c06586cc25abd758a8b2fccc /test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
parent2c207a0f677a2d78b768acb559e6b9f6f112a50d (diff)
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Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt')
-rw-r--r--test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
index 55a52cf..3f406d4 100644
--- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
+++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)