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authorAkira Hatanaka <ahatanaka@mips.com>2013-07-26 20:51:20 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-07-26 20:51:20 +0000
commit407883b69b3bc10ebf053f5922d877b2e786d124 (patch)
tree455f21b303921399a0d728c489dd84a9364c7a1a /test/MC/Disassembler/Mips/mips32.txt
parent8b68480453b472fbc49aebc49c37e3ef4cad66cb (diff)
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[mips] Fix FP conditional move instructions to have explicit FP condition code
register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler/Mips/mips32.txt')
-rw-r--r--test/MC/Disassembler/Mips/mips32.txt18
1 files changed, 18 insertions, 0 deletions
diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
index d624889..6d02925 100644
--- a/test/MC/Disassembler/Mips/mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -266,6 +266,24 @@
# CHECK: mov.s $f6, $f7
0x46 0x00 0x39 0x86
+# CHECK: movf $3, $2, $fcc7
+0x00,0x5c,0x18,0x01
+
+# CHECK: movf.d $f4, $f2, $fcc7
+0x46,0x3c,0x11,0x11
+
+# CHECK: movf.s $f4, $f2, $fcc7
+0x46,0x1c,0x11,0x11
+
+# CHECK: movt $3, $2, $fcc7
+0x00,0x5d,0x18,0x01
+
+# CHECK: movt.d $f4, $f2, $fcc7
+0x46,0x3d,0x11,0x11
+
+# CHECK: movt.s $f4, $f2, $fcc7
+0x46,0x1d,0x11,0x11
+
# CHECK: msub $6, $7
0x70 0xc7 0x00 0x04