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| author | Richard Osborne <richard@xmos.com> | 2013-01-20 17:18:47 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-20 17:18:47 +0000 |
| commit | 62b8786d12ceacafd665d4a1fbb6e90af0ec368c (patch) | |
| tree | f9141a727258624ac74e912204bc0119ab9d3f4e /test/MC/Disassembler | |
| parent | 1340833d7c7ed49cf8b19acf53b06a8087ab2bdc (diff) | |
| download | external_llvm-62b8786d12ceacafd665d4a1fbb6e90af0ec368c.zip external_llvm-62b8786d12ceacafd665d4a1fbb6e90af0ec368c.tar.gz external_llvm-62b8786d12ceacafd665d4a1fbb6e90af0ec368c.tar.bz2 | |
Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
| -rw-r--r-- | test/MC/Disassembler/XCore/xcore.txt | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index f6b9c90..b022f50 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -196,3 +196,41 @@ # CHECK: settw res[r7], r2 0x9b 0xff 0xec 0x27 + +# 3r instructions + +# CHECK: add r1, r2, r3 +0x1b 0x10 + +# CHECK: and r11, r10, r9 +0xb9 0x3e + +# CHECK: eq r6, r1, r2 +0x66 0x30 + +# CHECK: ld16s r8, r3[r4] +0xcc 0x82 + +# CHECK: ld8u r9, r1[r10] +0x16 0x8d + +# CHECK: ldw r9, r4[r5] +0x91 0x4b + +# CHECK: lss r7, r3, r0 +0x7c 0xc0 + +# CHECK: lsu r5, r8, r6 +0x12 0xcc + +# CHECK: or r1, r3, r2 +0x1e 0x40 + +# CHECK: shl r8, r2, r4 +0xc8 0x22 + +# CHECK: shr r9, r7, r1 +0x5d 0x29 + +# CHECK: sub r4, r2, r5 +0x89 0x1a |