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| author | Amara Emerson <amara.emerson@arm.com> | 2013-10-31 09:32:11 +0000 |
|---|---|---|
| committer | Amara Emerson <amara.emerson@arm.com> | 2013-10-31 09:32:11 +0000 |
| commit | c2884320feebc543d2ce51151d5418dfc18da9e4 (patch) | |
| tree | 0741cd0182a73f25f8f852c90a8b7751323dc4ef /test/MC/Disassembler | |
| parent | 0f5e68e3dc64e7dde41577649ad44b4453859276 (diff) | |
| download | external_llvm-c2884320feebc543d2ce51151d5418dfc18da9e4.zip external_llvm-c2884320feebc543d2ce51151d5418dfc18da9e4.tar.gz external_llvm-c2884320feebc543d2ce51151d5418dfc18da9e4.tar.bz2 | |
[AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
5 files changed, 5 insertions, 5 deletions
diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt index 966530d..799ecdf 100644 --- a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s # The "Rm" bits are ignored, but the canonical representation has them filled # with 0s. This is what we should produce even if the input bit-pattern had diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 4fa2d50..40926b1 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Add/sub (immediate) diff --git a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt index adb8f75..5363863 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s #------------------------------------------------------------------------------ # Load-store exclusive diff --git a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt index 775660b..637ebdb 100644 --- a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt index 48ea817..f52d37f 100644 --- a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: |