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| author | Jack Carter <jcarter@mips.com> | 2012-08-22 00:49:30 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2012-08-22 00:49:30 +0000 |
| commit | 101771ba4d9c2421f836069fcedf9ddc8a0c9dc7 (patch) | |
| tree | 1f743fb5f09df0548a3df1224fd0ad863cb4877a /test/MC/Mips | |
| parent | cb1f68d7c8bea99530ba55813c2b4ddd14556286 (diff) | |
| download | external_llvm-101771ba4d9c2421f836069fcedf9ddc8a0c9dc7.zip external_llvm-101771ba4d9c2421f836069fcedf9ddc8a0c9dc7.tar.gz external_llvm-101771ba4d9c2421f836069fcedf9ddc8a0c9dc7.tar.bz2 | |
For mips64 switch statements in subroutines could generate
within the codegen EK_GPRel64BlockAddress. This was not
supported for direct object output and resulted in an assertion.
This change adds support for EK_GPRel64BlockAddress for
direct object.
One fallout from this is to turn on rela relocations
for mips64 to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162334 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips')
| -rw-r--r-- | test/MC/Mips/do_switch.ll | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/test/MC/Mips/do_switch.ll b/test/MC/Mips/do_switch.ll new file mode 100644 index 0000000..7eda1b4 --- /dev/null +++ b/test/MC/Mips/do_switch.ll @@ -0,0 +1,39 @@ +; This test case will cause an internal EK_GPRel64BlockAddress to be +; produced. This was not handled for direct object and an assertion +; to occur. This is a variation on test case test/CodeGen/Mips/do_switch.ll + +; RUN: llc < %s -filetype=obj -march=mips -relocation-model=static + +; RUN: llc < %s -filetype=obj -march=mips -relocation-model=pic + +; RUN: llc < %s -filetype=obj -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64 + +define i32 @main() nounwind readnone { +entry: + %x = alloca i32, align 4 ; <i32*> [#uses=2] + store volatile i32 2, i32* %x, align 4 + %0 = load volatile i32* %x, align 4 ; <i32> [#uses=1] + + switch i32 %0, label %bb4 [ + i32 0, label %bb5 + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + ] + +bb1: ; preds = %entry + ret i32 2 + +bb2: ; preds = %entry + ret i32 0 + +bb3: ; preds = %entry + ret i32 3 + +bb4: ; preds = %entry + ret i32 4 + +bb5: ; preds = %entry + ret i32 1 +} + |