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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-26 13:49:15 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-26 13:49:15 +0000 |
commit | 0b8594268feb1c804370541c7853e658caee0ae5 (patch) | |
tree | dc7535ada4e2ac46955bc2ded537f1e68e811903 /test/MC/PowerPC | |
parent | 6e0857e0b6b241e8b698417659a5821f15290a63 (diff) | |
download | external_llvm-0b8594268feb1c804370541c7853e658caee0ae5.zip external_llvm-0b8594268feb1c804370541c7853e658caee0ae5.tar.gz external_llvm-0b8594268feb1c804370541c7853e658caee0ae5.tar.bz2 |
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/PowerPC')
-rw-r--r-- | test/MC/PowerPC/ppc64-fixups.s | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index d7dfc50..18811fa 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -133,6 +133,16 @@ base: # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE li 3, target-base@ha +# CHECK: ori 3, 3, target@l # encoding: [0x60,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 + ori 3, 3, target@l + +# CHECK: oris 3, 3, target@h # encoding: [0x64,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 + oris 3, 3, target@h + # CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] # CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 |