aboutsummaryrefslogtreecommitdiffstats
path: root/test/TableGen/AsmPredicateCondsEmission.td
diff options
context:
space:
mode:
authorPirama Arumuga Nainar <pirama@google.com>2015-05-06 11:46:36 -0700
committerPirama Arumuga Nainar <pirama@google.com>2015-05-18 10:52:30 -0700
commit2c3e0051c31c3f5b2328b447eadf1cf9c4427442 (patch)
treec0104029af14e9f47c2ef58ca60e6137691f3c9b /test/TableGen/AsmPredicateCondsEmission.td
parente1bc145815f4334641be19f1c45ecf85d25b6e5a (diff)
downloadexternal_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.zip
external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.gz
external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.bz2
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
Diffstat (limited to 'test/TableGen/AsmPredicateCondsEmission.td')
-rw-r--r--test/TableGen/AsmPredicateCondsEmission.td31
1 files changed, 31 insertions, 0 deletions
diff --git a/test/TableGen/AsmPredicateCondsEmission.td b/test/TableGen/AsmPredicateCondsEmission.td
new file mode 100644
index 0000000..ba5898f
--- /dev/null
+++ b/test/TableGen/AsmPredicateCondsEmission.td
@@ -0,0 +1,31 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+
+// Check that we don't generate invalid code of the form "( && Cond2)" when
+// emitting AssemblerPredicate conditions. In the example below, the invalid
+// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+ let InstructionSet = archInstrInfo;
+}
+
+def Pred1 : Predicate<"Condition1">;
+def Pred2 : Predicate<"Condition2">,
+ AssemblerPredicate<"AssemblerCondition2">;
+
+def foo : Instruction {
+ let Size = 2;
+ let OutOperandList = (outs);
+ let InOperandList = (ins);
+ field bits<16> Inst;
+ let Inst = 0xAAAA;
+ let AsmString = "foo";
+ field bits<16> SoftFail = 0;
+ // This is the important bit:
+ let Predicates = [Pred1, Pred2];
+}
+
+// CHECK: return ((Bits & arch::AssemblerCondition2));