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| author | Hal Finkel <hfinkel@anl.gov> | 2012-11-28 03:04:10 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-11-28 03:04:10 +0000 |
| commit | 430b9079c614cd3f45015a6516590d33742cc802 (patch) | |
| tree | 81f69c741eaa13b84d73d5d600e8af14b84bcc88 /test/Transforms/BBVectorize | |
| parent | 6acb53152cd2140bc1f7ec7280bf67823e564ba0 (diff) | |
| download | external_llvm-430b9079c614cd3f45015a6516590d33742cc802.zip external_llvm-430b9079c614cd3f45015a6516590d33742cc802.tar.gz external_llvm-430b9079c614cd3f45015a6516590d33742cc802.tar.bz2 | |
BBVectorize: Correctly merge SubclassOptionalData
When two instructions are combined into a vector instruction,
the resulting instruction must have the most-conservative flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168765 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/BBVectorize')
| -rw-r--r-- | test/Transforms/BBVectorize/simple.ll | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/test/Transforms/BBVectorize/simple.ll b/test/Transforms/BBVectorize/simple.ll index d9a12ee..3527ae7 100644 --- a/test/Transforms/BBVectorize/simple.ll +++ b/test/Transforms/BBVectorize/simple.ll @@ -173,3 +173,27 @@ define double @test7(double %A1, double %A2, double %B1, double %B2) { ; CHECK: ret double %R } +; Basic depth-3 chain (subclass data) +define i64 @test8(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { +; CHECK: @test8 +; CHECK: %X1.v.i1.1 = insertelement <2 x i64> undef, i64 %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x i64> %X1.v.i1.1, i64 %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x i64> undef, i64 %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x i64> %X1.v.i0.1, i64 %A2, i32 1 + %X1 = sub nsw i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 +; CHECK: %X1 = sub <2 x i64> %X1.v.i0.2, %X1.v.i1.2 + %Y1 = mul i64 %X1, %A1 + %Y2 = mul i64 %X2, %A2 +; CHECK: %Y1 = mul <2 x i64> %X1, %X1.v.i0.2 + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 +; CHECK: %Z1 = add <2 x i64> %Y1, %X1.v.i1.2 + %R = mul i64 %Z1, %Z2 +; CHECK: %Z1.v.r1 = extractelement <2 x i64> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x i64> %Z1, i32 1 +; CHECK: %R = mul i64 %Z1.v.r1, %Z1.v.r2 + ret i64 %R +; CHECK: ret i64 %R +} + |