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| author | Stephen Hines <srhines@google.com> | 2015-04-01 18:49:24 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2015-04-01 18:49:26 +0000 |
| commit | 3fa16bd6062e23bcdb82ed4dd965674792e6b761 (patch) | |
| tree | 9348fc507292f7e8715d22d64ce5a32131b4f875 /test/Transforms/InstCombine/icmp.ll | |
| parent | beed47390a60f6f0c77532b3d3f76bb47ef49423 (diff) | |
| parent | ebe69fe11e48d322045d5949c83283927a0d790b (diff) | |
| download | external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.zip external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.tar.gz external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.tar.bz2 | |
Merge "Update aosp/master LLVM for rebase to r230699."
Diffstat (limited to 'test/Transforms/InstCombine/icmp.ll')
| -rw-r--r-- | test/Transforms/InstCombine/icmp.ll | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 279d86d..64741c5 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -1522,3 +1522,54 @@ define zeroext i1 @icmp_cmpxchg_strong(i32* %sc, i32 %old_val, i32 %new_val) { %icmp = icmp eq i32 %xtrc, %old_val ret i1 %icmp } + +; CHECK-LABEL: @f1 +; CHECK-NEXT: %[[cmp:.*]] = icmp sge i64 %a, %b +; CHECK-NEXT: ret i1 %[[cmp]] +define i1 @f1(i64 %a, i64 %b) { + %t = sub nsw i64 %a, %b + %v = icmp sge i64 %t, 0 + ret i1 %v +} + +; CHECK-LABEL: @f2 +; CHECK-NEXT: %[[cmp:.*]] = icmp sgt i64 %a, %b +; CHECK-NEXT: ret i1 %[[cmp]] +define i1 @f2(i64 %a, i64 %b) { + %t = sub nsw i64 %a, %b + %v = icmp sgt i64 %t, 0 + ret i1 %v +} + +; CHECK-LABEL: @f3 +; CHECK-NEXT: %[[cmp:.*]] = icmp slt i64 %a, %b +; CHECK-NEXT: ret i1 %[[cmp]] +define i1 @f3(i64 %a, i64 %b) { + %t = sub nsw i64 %a, %b + %v = icmp slt i64 %t, 0 + ret i1 %v +} + +; CHECK-LABEL: @f4 +; CHECK-NEXT: %[[cmp:.*]] = icmp sle i64 %a, %b +; CHECK-NEXT: ret i1 %[[cmp]] +define i1 @f4(i64 %a, i64 %b) { + %t = sub nsw i64 %a, %b + %v = icmp sle i64 %t, 0 + ret i1 %v +} + +; CHECK-LABEL: @f5 +; CHECK: %[[cmp:.*]] = icmp slt i32 %[[sub:.*]], 0 +; CHECK: %[[neg:.*]] = sub nsw i32 0, %[[sub]] +; CHECK: %[[sel:.*]] = select i1 %[[cmp]], i32 %[[neg]], i32 %[[sub]] +; CHECK: ret i32 %[[sel]] +define i32 @f5(i8 %a, i8 %b) { + %conv = zext i8 %a to i32 + %conv3 = zext i8 %b to i32 + %sub = sub nsw i32 %conv, %conv3 + %cmp4 = icmp slt i32 %sub, 0 + %sub7 = sub nsw i32 0, %sub + %sub7.sub = select i1 %cmp4, i32 %sub7, i32 %sub + ret i32 %sub7.sub +} |