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author | Chris Lattner <sabre@nondot.org> | 2011-02-10 05:36:31 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2011-02-10 05:36:31 +0000 |
commit | 7a6aa1a3919af8ece92702c36dc552d81be9151a (patch) | |
tree | bf7aae31c9fef6342c9b6e785c700e6e3f7cbdec /test/Transforms/InstCombine/signext.ll | |
parent | b20c0b5092f11ff349855ec1e732590160aeba23 (diff) | |
download | external_llvm-7a6aa1a3919af8ece92702c36dc552d81be9151a.zip external_llvm-7a6aa1a3919af8ece92702c36dc552d81be9151a.tar.gz external_llvm-7a6aa1a3919af8ece92702c36dc552d81be9151a.tar.bz2 |
Enhance a bunch of transformations in instcombine to start generating
exact/nsw/nuw shifts and have instcombine infer them when it can prove
that the relevant properties are true for a given shift without them.
Also, a variety of refactoring to use the new patternmatch logic thrown
in for good luck. I believe that this takes care of a bunch of related
code quality issues attached to PR8862.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125267 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine/signext.ll')
-rw-r--r-- | test/Transforms/InstCombine/signext.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/Transforms/InstCombine/signext.ll b/test/Transforms/InstCombine/signext.ll index 49384d6..ecee983 100644 --- a/test/Transforms/InstCombine/signext.ll +++ b/test/Transforms/InstCombine/signext.ll @@ -9,7 +9,7 @@ define i32 @test1(i32 %x) { ret i32 %tmp.3 ; CHECK: @test1 ; CHECK: %sext = shl i32 %x, 16 -; CHECK: %tmp.3 = ashr i32 %sext, 16 +; CHECK: %tmp.3 = ashr exact i32 %sext, 16 ; CHECK: ret i32 %tmp.3 } @@ -20,7 +20,7 @@ define i32 @test2(i32 %x) { ret i32 %tmp.3 ; CHECK: @test2 ; CHECK: %sext = shl i32 %x, 16 -; CHECK: %tmp.3 = ashr i32 %sext, 16 +; CHECK: %tmp.3 = ashr exact i32 %sext, 16 ; CHECK: ret i32 %tmp.3 } @@ -51,7 +51,7 @@ define i32 @test5(i32 %x) { ret i32 %tmp.3 ; CHECK: @test5 ; CHECK: %sext = shl i32 %x, 24 -; CHECK: %tmp.3 = ashr i32 %sext, 24 +; CHECK: %tmp.3 = ashr exact i32 %sext, 24 ; CHECK: ret i32 %tmp.3 } @@ -61,7 +61,7 @@ define i32 @test6(i32 %x) { ret i32 %tmp.4 ; CHECK: @test6 ; CHECK: %tmp.2 = shl i32 %x, 16 -; CHECK: %tmp.4 = ashr i32 %tmp.2, 16 +; CHECK: %tmp.4 = ashr exact i32 %tmp.2, 16 ; CHECK: ret i32 %tmp.4 } @@ -82,6 +82,6 @@ entry: %sub = add i32 %xor, -67108864 ; <i32> [#uses=1] ret i32 %sub ; CHECK: @test8 -; CHECK: %sub = ashr i32 %x, 5 -; CHECK: ret i32 %sub +; CHECK: %shr = ashr i32 %x, 5 +; CHECK: ret i32 %shr } |