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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2013-09-18 12:06:59 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2013-09-18 12:06:59 +0000 |
| commit | af96481135473f8da6de06f5ad18c09bd376a50f (patch) | |
| tree | 71fa1450dc6cba6a84d31b9a72d3d716bace1756 /test/Transforms/InstCombine | |
| parent | e2d6f91d63a2e8cf77b07794cda7d9ef72504769 (diff) | |
| download | external_llvm-af96481135473f8da6de06f5ad18c09bd376a50f.zip external_llvm-af96481135473f8da6de06f5ad18c09bd376a50f.tar.gz external_llvm-af96481135473f8da6de06f5ad18c09bd376a50f.tar.bz2 | |
Re-add tests from r179291 which were accidentally removed by r181177.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190934 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine')
| -rw-r--r-- | test/Transforms/InstCombine/vec_shuffle.ll | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll index 738e05b..3ee43dc 100644 --- a/test/Transforms/InstCombine/vec_shuffle.ll +++ b/test/Transforms/InstCombine/vec_shuffle.ll @@ -200,3 +200,31 @@ define void @test14(i16 %conv10) { %sext = sext <2 x i1> %cmp to <2 x i16> ret void } + +; Check that sequences of insert/extract element are +; collapsed into valid shuffle instruction with correct shuffle indexes. + +define <4 x float> @test15a(<4 x float> %LHS, <4 x float> %RHS) { +; CHECK-LABEL: @test15a +; CHECK-NEXT: shufflevector <4 x float> %LHS, <4 x float> %RHS, <4 x i32> <i32 4, i32 0, i32 6, i32 6> +; CHECK-NEXT: ret <4 x float> %tmp4 + %tmp1 = extractelement <4 x float> %LHS, i32 0 + %tmp2 = insertelement <4 x float> %RHS, float %tmp1, i32 1 + %tmp3 = extractelement <4 x float> %RHS, i32 2 + %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 3 + ret <4 x float> %tmp4 +} + +define <4 x float> @test15b(<4 x float> %LHS, <4 x float> %RHS) { +; CHECK-LABEL: @test15b +; CHECK-NEXT: shufflevector <4 x float> %LHS, <4 x float> %RHS, <4 x i32> <i32 4, i32 3, i32 6, i32 6> +; CHECK-NEXT: ret <4 x float> %tmp5 + %tmp0 = extractelement <4 x float> %LHS, i32 3 + %tmp1 = insertelement <4 x float> %RHS, float %tmp0, i32 0 + %tmp2 = extractelement <4 x float> %tmp1, i32 0 + %tmp3 = insertelement <4 x float> %RHS, float %tmp2, i32 1 + %tmp4 = extractelement <4 x float> %RHS, i32 2 + %tmp5 = insertelement <4 x float> %tmp3, float %tmp4, i32 3 + ret <4 x float> %tmp5 +} + |