diff options
| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll')
| -rw-r--r-- | test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll b/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll index 95734bf..4cd703f 100644 --- a/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll +++ b/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll @@ -11,8 +11,8 @@ target triple = "aarch64--linux-gnueabi" ; } ; CHECK-LABEL: @ind_plus2( -; CHECK: load <4 x i32>* -; CHECK: load <4 x i32>* +; CHECK: load <4 x i32>, <4 x i32>* +; CHECK: load <4 x i32>, <4 x i32>* ; CHECK: mul nsw <4 x i32> ; CHECK: mul nsw <4 x i32> ; CHECK: add nsw <4 x i32> @@ -21,7 +21,7 @@ target triple = "aarch64--linux-gnueabi" ; CHECK: icmp eq i64 %index.next, 512 ; FORCE-VEC-LABEL: @ind_plus2( -; FORCE-VEC: %wide.load = load <2 x i32>* +; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>* ; FORCE-VEC: mul nsw <2 x i32> ; FORCE-VEC: add nsw <2 x i32> ; FORCE-VEC: %index.next = add i64 %index, 2 @@ -34,8 +34,8 @@ for.body: ; preds = %entry, %for.body %A.addr = phi i32* [ %A, %entry ], [ %inc.ptr, %for.body ] %i = phi i32 [ 0, %entry ], [ %add1, %for.body ] %sum = phi i32 [ 0, %entry ], [ %add, %for.body ] - %inc.ptr = getelementptr inbounds i32* %A.addr, i64 1 - %0 = load i32* %A.addr, align 4 + %inc.ptr = getelementptr inbounds i32, i32* %A.addr, i64 1 + %0 = load i32, i32* %A.addr, align 4 %mul = mul nsw i32 %0, %i %add = add nsw i32 %mul, %sum %add1 = add nsw i32 %i, 2 @@ -55,8 +55,8 @@ for.end: ; preds = %for.body ; } ; CHECK-LABEL: @ind_minus2( -; CHECK: load <4 x i32>* -; CHECK: load <4 x i32>* +; CHECK: load <4 x i32>, <4 x i32>* +; CHECK: load <4 x i32>, <4 x i32>* ; CHECK: mul nsw <4 x i32> ; CHECK: mul nsw <4 x i32> ; CHECK: add nsw <4 x i32> @@ -65,7 +65,7 @@ for.end: ; preds = %for.body ; CHECK: icmp eq i64 %index.next, 512 ; FORCE-VEC-LABEL: @ind_minus2( -; FORCE-VEC: %wide.load = load <2 x i32>* +; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>* ; FORCE-VEC: mul nsw <2 x i32> ; FORCE-VEC: add nsw <2 x i32> ; FORCE-VEC: %index.next = add i64 %index, 2 @@ -78,8 +78,8 @@ for.body: ; preds = %entry, %for.body %A.addr = phi i32* [ %A, %entry ], [ %inc.ptr, %for.body ] %i = phi i32 [ 1024, %entry ], [ %sub, %for.body ] %sum = phi i32 [ 0, %entry ], [ %add, %for.body ] - %inc.ptr = getelementptr inbounds i32* %A.addr, i64 1 - %0 = load i32* %A.addr, align 4 + %inc.ptr = getelementptr inbounds i32, i32* %A.addr, i64 1 + %0 = load i32, i32* %A.addr, align 4 %mul = mul nsw i32 %0, %i %add = add nsw i32 %mul, %sum %sub = add nsw i32 %i, -2 @@ -102,10 +102,10 @@ for.end: ; preds = %for.body ; } ; CHECK-LABEL: @ptr_ind_plus2( -; CHECK: load i32* -; CHECK: load i32* -; CHECK: load i32* -; CHECK: load i32* +; CHECK: load i32, i32* +; CHECK: load i32, i32* +; CHECK: load i32, i32* +; CHECK: load i32, i32* ; CHECK: mul nsw i32 ; CHECK: mul nsw i32 ; CHECK: add nsw i32 @@ -114,13 +114,13 @@ for.end: ; preds = %for.body ; CHECK: %21 = icmp eq i64 %index.next, 1024 ; FORCE-VEC-LABEL: @ptr_ind_plus2( -; FORCE-VEC: load i32* +; FORCE-VEC: load i32, i32* ; FORCE-VEC: insertelement <2 x i32> -; FORCE-VEC: load i32* +; FORCE-VEC: load i32, i32* ; FORCE-VEC: insertelement <2 x i32> -; FORCE-VEC: load i32* +; FORCE-VEC: load i32, i32* ; FORCE-VEC: insertelement <2 x i32> -; FORCE-VEC: load i32* +; FORCE-VEC: load i32, i32* ; FORCE-VEC: insertelement <2 x i32> ; FORCE-VEC: mul nsw <2 x i32> ; FORCE-VEC: add nsw <2 x i32> @@ -134,10 +134,10 @@ for.body: ; preds = %for.body, %entry %A.addr = phi i32* [ %A, %entry ], [ %inc.ptr1, %for.body ] %sum = phi i32 [ 0, %entry ], [ %add, %for.body ] %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %inc.ptr = getelementptr inbounds i32* %A.addr, i64 1 - %0 = load i32* %A.addr, align 4 - %inc.ptr1 = getelementptr inbounds i32* %A.addr, i64 2 - %1 = load i32* %inc.ptr, align 4 + %inc.ptr = getelementptr inbounds i32, i32* %A.addr, i64 1 + %0 = load i32, i32* %A.addr, align 4 + %inc.ptr1 = getelementptr inbounds i32, i32* %A.addr, i64 2 + %1 = load i32, i32* %inc.ptr, align 4 %mul = mul nsw i32 %1, %0 %add = add nsw i32 %mul, %sum %inc = add nsw i32 %i, 1 |