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authorChandler Carruth <chandlerc@gmail.com>2013-09-18 14:08:30 +0000
committerChandler Carruth <chandlerc@gmail.com>2013-09-18 14:08:30 +0000
commit89ec610f76ead733cbbaf9da3c55b63eaf16ec88 (patch)
tree67157da6c65a027a3504cb7a6240618bcd9fc394 /test/Transforms/LoopVectorize/XCore
parentac04abaf5a1df4c4bf48367cfbb41600289c4d78 (diff)
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Name the XCore target-specific subdirectories canonically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190940 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/LoopVectorize/XCore')
-rw-r--r--test/Transforms/LoopVectorize/XCore/lit.local.cfg3
-rw-r--r--test/Transforms/LoopVectorize/XCore/no-vector-registers.ll23
2 files changed, 26 insertions, 0 deletions
diff --git a/test/Transforms/LoopVectorize/XCore/lit.local.cfg b/test/Transforms/LoopVectorize/XCore/lit.local.cfg
new file mode 100644
index 0000000..4d17d46
--- /dev/null
+++ b/test/Transforms/LoopVectorize/XCore/lit.local.cfg
@@ -0,0 +1,3 @@
+targets = set(config.root.targets_to_build.split())
+if not 'XCore' in targets:
+ config.unsupported = True
diff --git a/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll b/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll
new file mode 100644
index 0000000..a099daa
--- /dev/null
+++ b/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll
@@ -0,0 +1,23 @@
+; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-unroll=2 -S -mtriple=xcore | FileCheck %s
+
+target datalayout = "e-p:32:32:32-a0:0:32-n32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f16:16:32-f32:32:32-f64:32:32"
+target triple = "xcore"
+; The xcore target has no vector registers, so loop should not be vectorized.
+;CHECK-LABEL: @f(
+;CHECK: entry:
+;CHECK-NOT: vector.body
+;CHECK-NEXT: br label %do.body
+define void @f(i8* nocapture %ptr, i32 %len) {
+entry:
+ br label %do.body
+do.body:
+ %ptr.addr.0 = phi i8* [ %ptr, %entry ], [ %incdec.ptr, %do.body ]
+ %len.addr.0 = phi i32 [ %len, %entry ], [ %dec, %do.body ]
+ %incdec.ptr = getelementptr inbounds i8* %ptr.addr.0, i32 1
+ store i8 0, i8* %ptr.addr.0, align 1
+ %dec = add nsw i32 %len.addr.0, -1
+ %tobool = icmp eq i32 %len.addr.0, 0
+ br i1 %tobool, label %do.end, label %do.body
+do.end:
+ ret void
+}