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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/Transforms/SROA/slice-width.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/Transforms/SROA/slice-width.ll')
| -rw-r--r-- | test/Transforms/SROA/slice-width.ll | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/test/Transforms/SROA/slice-width.ll b/test/Transforms/SROA/slice-width.ll index ff66dcc..6b6ab93 100644 --- a/test/Transforms/SROA/slice-width.ll +++ b/test/Transforms/SROA/slice-width.ll @@ -14,14 +14,14 @@ load_i32: ; CHECK-LABEL: load_i32: ; CHECK-NOT: bitcast {{.*}} to i1 ; CHECK-NOT: zext i1 - %r0 = load i32* %arg + %r0 = load i32, i32* %arg br label %load_i1 load_i1: ; CHECK-LABEL: load_i1: ; CHECK: bitcast {{.*}} to i1 %p1 = bitcast i32* %arg to i1* - %t1 = load i1* %p1 + %t1 = load i1, i1* %p1 ret void } @@ -42,16 +42,16 @@ define void @memcpy_fp80_padding() { call void @llvm.memcpy.p0i8.p0i8.i32(i8* %x_i8, i8* bitcast (%union.Foo* @foo_copy_source to i8*), i32 32, i32 16, i1 false) ; Access a slice of the alloca to trigger SROA. - %mid_p = getelementptr %union.Foo* %x, i32 0, i32 1 - %elt = load i64* %mid_p + %mid_p = getelementptr %union.Foo, %union.Foo* %x, i32 0, i32 1 + %elt = load i64, i64* %mid_p store i64 %elt, i64* @i64_sink ret void } ; CHECK-LABEL: define void @memcpy_fp80_padding ; CHECK: alloca x86_fp80 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32 -; CHECK: load i64* getelementptr inbounds (%union.Foo* @foo_copy_source, i64 0, i32 1) -; CHECK: load i64* getelementptr inbounds (%union.Foo* @foo_copy_source, i64 0, i32 2) +; CHECK: load i64, i64* getelementptr inbounds (%union.Foo, %union.Foo* @foo_copy_source, i64 0, i32 1) +; CHECK: load i64, i64* getelementptr inbounds (%union.Foo, %union.Foo* @foo_copy_source, i64 0, i32 2) define void @memset_fp80_padding() { %x = alloca %union.Foo @@ -61,8 +61,8 @@ define void @memset_fp80_padding() { call void @llvm.memset.p0i8.i32(i8* %x_i8, i8 -1, i32 32, i32 16, i1 false) ; Access a slice of the alloca to trigger SROA. - %mid_p = getelementptr %union.Foo* %x, i32 0, i32 1 - %elt = load i64* %mid_p + %mid_p = getelementptr %union.Foo, %union.Foo* %x, i32 0, i32 1 + %elt = load i64, i64* %mid_p store i64 %elt, i64* @i64_sink ret void } @@ -89,8 +89,8 @@ entry: ; The following block does nothing; but appears to confuse SROA %unused1 = bitcast %S.vec3float* %tmp1 to %U.vec3float* - %unused2 = getelementptr inbounds %U.vec3float* %unused1, i32 0, i32 0 - %unused3 = load <4 x float>* %unused2, align 1 + %unused2 = getelementptr inbounds %U.vec3float, %U.vec3float* %unused1, i32 0, i32 0 + %unused3 = load <4 x float>, <4 x float>* %unused2, align 1 ; Create a second temporary and copy %tmp1 into it %tmp2 = alloca %S.vec3float, align 4 |