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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-08-15 23:59:28 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-08-15 23:59:28 +0000 |
| commit | 8176388d65083339efdfa5bee63e620c6bd05aa1 (patch) | |
| tree | 7b4b6dbade9c5d8273ef7ff194722ff0d51f6b44 /test/Transforms/SimplifyCFG | |
| parent | fd06b3cfa184a357f5f37625f50be104c8573fc3 (diff) | |
| download | external_llvm-8176388d65083339efdfa5bee63e620c6bd05aa1.zip external_llvm-8176388d65083339efdfa5bee63e620c6bd05aa1.tar.gz external_llvm-8176388d65083339efdfa5bee63e620c6bd05aa1.tar.bz2 | |
Update SimplifyCFG for atomic operations.
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it. I think the current behavior is correct,
though. Bill, can you double-check that?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137691 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/SimplifyCFG')
| -rw-r--r-- | test/Transforms/SimplifyCFG/trapping-load-unreachable.ll | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll index ebf4f17..10d6981 100644 --- a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll +++ b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll @@ -42,3 +42,46 @@ entry: ; CHECK: store volatile i32 4, i32* null ; CHECK: ret } + +; Check store before unreachable. +define void @test4(i1 %C, i32* %P) { +; CHECK: @test4 +; CHECK: entry: +; CHECK-NEXT: br i1 %C +entry: + br i1 %C, label %T, label %F +T: + store volatile i32 0, i32* %P + unreachable +F: + ret void +} + +; Check cmpxchg before unreachable. +define void @test5(i1 %C, i32* %P) { +; CHECK: @test5 +; CHECK: entry: +; CHECK-NEXT: br i1 %C +entry: + br i1 %C, label %T, label %F +T: + cmpxchg volatile i32* %P, i32 0, i32 1 seq_cst + unreachable +F: + ret void +} + +; Check atomicrmw before unreachable. +define void @test6(i1 %C, i32* %P) { +; CHECK: @test6 +; CHECK: entry: +; CHECK-NEXT: br i1 %C +entry: + br i1 %C, label %T, label %F +T: + atomicrmw volatile xchg i32* %P, i32 0 seq_cst + unreachable +F: + ret void +} + |