[Sparc]: Use cmp instruction instead of subcc to compare integers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 17 insertions, 17 deletions

diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll
index f676fd8..599b451 100644
--- a/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -21,10 +21,10 @@ entry:
 define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
 entry:
 ; V8: test_select_int_icc
-; V8: subcc
+; V8: cmp
 ; V8: {{be|bne}}
 ; V9: test_select_int_icc
-; V9: subcc
+; V9: cmp
 ; V9-NOT: {{be|bne}}
 ; V9: mov{{e|ne}} %icc
   %0 = icmp eq i32 %a, 0
@@ -36,10 +36,10 @@ entry:
 define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
 entry:
 ; V8: test_select_fp_icc
-; V8: subcc
+; V8: cmp
 ; V8: {{be|bne}}
 ; V9: test_select_fp_icc
-; V9: subcc
+; V9: cmp
 ; V9-NOT: {{be|bne}}
 ; V9: fmovs{{e|ne}} %icc
   %0 = icmp eq i32 %a, 0
@@ -50,10 +50,10 @@ entry:
 define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
 entry:
 ; V8: test_select_dfp_icc
-; V8: subcc
+; V8: cmp
 ; V8: {{be|bne}}
 ; V9: test_select_dfp_icc
-; V9: subcc
+; V9: cmp
 ; V9-NOT: {{be|bne}}
 ; V9: fmovd{{e|ne}} %icc
   %0 = icmp eq i32 %a, 0
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 89981a8..b39c355 100644
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -40,7 +40,7 @@ bb:                                               ; preds = %entry, %bb
   %a_addr.0 = add i32 %.pn, %a_addr.18
   %3 = add nsw i32 %1, 1
   %exitcond = icmp eq i32 %3, %b
-;CHECK:      subcc
+;CHECK:      cmp
 ;CHECK:      bne
 ;CHECK-NOT:  nop
   br i1 %exitcond, label %bb5, label %bb
@@ -57,7 +57,7 @@ entry:
 ;CHECK:      test_inlineasm
 ;CHECK:      sethi
 ;CHECK:      !NO_APP
-;CHECK-NEXT: subcc
+;CHECK-NEXT: cmp
 ;CHECK-NEXT: bg
 ;CHECK-NEXT: nop
   tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index 4eb2553..c856941 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -230,7 +230,7 @@ entry:
 declare void @g(i8*)
 
 ; CHECK: expand_setcc
-; CHECK: subcc %i0, 1,
+; CHECK: cmp %i0, 1
 ; CHECK: movl %xcc, 1,
 define i32 @expand_setcc(i64 %a) {
   %cond = icmp sle i64 %a, 0
diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll
index 88b476d..f0f6f9e 100644
--- a/test/CodeGen/SPARC/64cond.ll
+++ b/test/CodeGen/SPARC/64cond.ll
@@ -2,7 +2,7 @@
 ; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
 
 ; CHECK: cmpri
-; CHECK: subcc %i1, 1
+; CHECK: cmp %i1, 1
 ; CHECK: bpe %xcc,
 define void @cmpri(i64* %p, i64 %x) {
 entry:
@@ -18,7 +18,7 @@ if.end:
 }
 
 ; CHECK: cmprr
-; CHECK: subcc %i1, %i2
+; CHECK: cmp %i1, %i2
 ; CHECK: bpgu %xcc,
 define void @cmprr(i64* %p, i64 %x, i64 %y) {
 entry:
@@ -34,7 +34,7 @@ if.end:
 }
 
 ; CHECK: selecti32_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: movg %xcc, %i2, %i3
 ; CHECK: restore %g0, %i3, %o0
 define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
@@ -45,7 +45,7 @@ entry:
 }
 
 ; CHECK: selecti64_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: movg %xcc, %i2, %i3
 ; CHECK: restore %g0, %i3, %o0
 define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
@@ -56,7 +56,7 @@ entry:
 }
 
 ; CHECK: selecti64_icc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: movg %icc, %i2, %i3
 ; CHECK: restore %g0, %i3, %o0
 define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
@@ -78,7 +78,7 @@ entry:
 }
 
 ; CHECK: selectf32_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: fmovsg %xcc, %f5, %f7
 ; CHECK: fmovs %f7, %f1
 define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
@@ -89,7 +89,7 @@ entry:
 }
 
 ; CHECK: selectf64_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: fmovdg %xcc, %f4, %f6
 ; CHECK: fmovd %f6, %f0
 define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
@@ -101,7 +101,7 @@ entry:
 
 ; The MOVXCC instruction can't use %g0 for its tied operand.
 ; CHECK: select_consti64_xcc
-; CHECK: subcc
+; CHECK: cmp
 ; CHECK: movg %xcc, 123, %i0
 define i64 @select_consti64_xcc(i64 %x, i64 %y) {
 entry: