PPC: Add base-pointer support to builtin setjmp/longjmp

First, this changes the base-pointer implementation to remove an unnecessary
complication (and one that is incompatible with how builtin SjLj is
implemented): instead of using r31 as the base pointer when it is not needed as
a frame pointer, now the base pointer will always be r30 when needed.

Second, we introduce another pseudo register, BP, which is used just like the FP
pseudo register to refer to the base register before we know for certain what
register it will be.

Third, we now save BP into the jmp_buf, and restore r30 from that slot in
longjmp.  If the function that called setjmp did not use a base pointer, then
r30 will be overwritten by the setjmp-calling-function's restore code. FP
restoration (which is restored into r31) works the same way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186545 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 58 insertions, 11 deletions

diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll
index 7ea35da..571f3b2 100644
--- a/test/CodeGen/PowerPC/sjlj.ll
+++ b/test/CodeGen/PowerPC/sjlj.ll
@@ -20,6 +20,7 @@ entry:
 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG]])
 ; CHECK: ld 1, 16([[REG]])
 ; CHECK: mtctr [[REG2]]
+; CHECK: ld 30, 32([[REG]])
 ; CHECK: ld 2, 24([[REG]])
 ; CHECK: bctr
 
@@ -99,6 +100,52 @@ return:                                           ; preds = %if.end, %if.then
 ; CHECK-NOAV: blr
 }
 
+define signext i32 @main2() #0 {
+entry:
+  %a = alloca i8, align 64
+  call void @bar(i8* %a)
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = call i8* @llvm.frameaddress(i32 0)
+  store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**)
+  %1 = call i8* @llvm.stacksave()
+  store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
+  %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
+  %tobool = icmp ne i32 %2, 0
+  br i1 %tobool, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  store i32 1, i32* %retval
+  br label %return
+
+if.else:                                          ; preds = %entry
+  call void @foo()
+  br label %if.end
+
+if.end:                                           ; preds = %if.else
+  store i32 0, i32* %retval
+  br label %return
+
+return:                                           ; preds = %if.end, %if.then
+  %3 = load i32* %retval
+  ret i32 %3
+
+; CHECK: @main2
+
+; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
+; CHECK: std 31, env_sigill@toc@l([[REG]])
+; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l
+; CHECK: std [[REG]], [[OFF:[0-9]+]](31)                  # 8-byte Folded Spill
+; CHECK: std 1, 16([[REG]])
+; CHECK: std 2, 24([[REG]])
+; CHECK: std 30, 32([[REG]])
+; CHECK: bcl 20, 31,
+
+; CHECK: blr
+}
+
+declare void @bar(i8*) #3
+
 declare i8* @llvm.frameaddress(i32) #2
 
 declare i8* @llvm.stacksave() #3
diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll
index 7bd28f6..f7b6d19 100644
--- a/test/CodeGen/PowerPC/stack-realign.ll
+++ b/test/CodeGen/PowerPC/stack-realign.ll
@@ -26,20 +26,20 @@ entry:
 
 ; CHECK-DAG: mflr 0
 ; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
-; CHECK-DAG: std 31, -8(1)
-; CHECK-DAG: mr 31, 1
+; CHECK-DAG: std 30, -16(1)
+; CHECK-DAG: mr 30, 1
 ; CHECK-DAG: std 0, 16(1)
 ; CHECK-DAG: subfic 0, [[REG]], -160
 ; CHECK: stdux 1, 1, 0
 
-; CHECK: .cfi_offset r31, -8
+; CHECK: .cfi_offset r30, -16
 ; CHECK: .cfi_offset lr, 16
 
-; CHECK: std 3, 48(31)
+; CHECK: std 3, 48(30)
 
 ; CHECK: ld 1, 0(1)
 ; CHECK-DAG: ld 0, 16(1)
-; CHECK-DAG: ld 31, -8(1)
+; CHECK-DAG: ld 30, -16(1)
 ; CHECK-DAG: mtlr 0
 ; CHECK: blr
 
@@ -91,8 +91,8 @@ entry:
 ; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59
 ; CHECK-DAG: mflr 0
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
-; CHECK-DAG: std 31, -8(1)
-; CHECK-DAG: mr 31, 1
+; CHECK-DAG: std 30, -16(1)
+; CHECK-DAG: mr 30, 1
 ; CHECK-DAG: std 0, 16(1)
 ; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
 ; CHECK: stdux 1, 1, 0
@@ -121,13 +121,13 @@ entry:
 
 ; CHECK-DAG: mflr 0
 ; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
-; CHECK-DAG: std 31, -24(1)
-; CHECK-DAG: mr 31, 1
+; CHECK-DAG: std 30, -32(1)
+; CHECK-DAG: mr 30, 1
 ; CHECK-DAG: std 0, 16(1)
-; CHECK-DAG: subfic 0, [[REG]], -160
+; CHECK-DAG: subfic 0, [[REG]], -192
 ; CHECK: stdux 1, 1, 0
 
-; CHECK: stfd 30, -16(31)
+; CHECK: stfd 30, -16(30)
 
 ; CHECK: blr