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authorAndrew Trick <atrick@apple.com>2012-03-21 22:31:31 +0000
committerAndrew Trick <atrick@apple.com>2012-03-21 22:31:31 +0000
commit07269265b048b4781bc446a3a35e405e9fb71b29 (patch)
treeebcce5f7a060993af2bb1dec3b47a6d2c2c339d8 /test
parent799184d8eb140d02385501223cea0a087148b67b (diff)
downloadexternal_llvm-07269265b048b4781bc446a3a35e405e9fb71b29.zip
external_llvm-07269265b048b4781bc446a3a35e405e9fb71b29.tar.gz
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misched: tag a few XFAILs that I plan to fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153222 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/lsr-reuse.ll1
-rw-r--r--test/CodeGen/X86/misched-new.ll (renamed from test/CodeGen/Generic/misched.ll)9
-rw-r--r--test/CodeGen/X86/remat-scalar-zero.ll1
-rw-r--r--test/CodeGen/X86/zext-sext.ll1
4 files changed, 10 insertions, 2 deletions
diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll
index 527a5a6..1311a73 100644
--- a/test/CodeGen/X86/lsr-reuse.ll
+++ b/test/CodeGen/X86/lsr-reuse.ll
@@ -1,4 +1,5 @@
; XFAIL: *
+; ...should pass. See PR12324: misched bringup
; RUN: llc < %s -march=x86-64 -O3 -asm-verbose=false | FileCheck %s
target datalayout = "e-p:64:64:64"
target triple = "x86_64-unknown-unknown"
diff --git a/test/CodeGen/Generic/misched.ll b/test/CodeGen/X86/misched-new.ll
index 9136b9c..f3c2af8 100644
--- a/test/CodeGen/Generic/misched.ll
+++ b/test/CodeGen/X86/misched-new.ll
@@ -1,5 +1,6 @@
-; RUN: true
-; llc -enable-misched -misched=shuffle -misched-bottomup < %s
+; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup < %s
+; XFAIL: *
+; ...should pass. See PR12324: misched bringup
;
; Interesting MachineScheduler cases.
@@ -7,6 +8,10 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
; From oggenc.
; After coalescing, we have a dead superreg (RAX) definition.
+;
+; CHECK: xorl %esi, %esi
+; CHECK: movl $32, %ecx
+; CHECK: rep;movsl
define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
entry:
br i1 undef, label %for.cond.preheader, label %if.end
diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll
index f6f0ed1..75f438d 100644
--- a/test/CodeGen/X86/remat-scalar-zero.ll
+++ b/test/CodeGen/X86/remat-scalar-zero.ll
@@ -1,4 +1,5 @@
; XFAIL: *
+; ...should pass. See PR12324: misched bringup
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t
; RUN: not grep xor %t
; RUN: not grep movap %t
diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll
index cea9e9c..6432ae3 100644
--- a/test/CodeGen/X86/zext-sext.ll
+++ b/test/CodeGen/X86/zext-sext.ll
@@ -1,4 +1,5 @@
; XFAIL: *
+; ...should pass. See PR12324: misched bringup
; RUN: llc < %s -march=x86-64 | FileCheck %s
; <rdar://problem/8006248>