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| author | Owen Anderson <resistor@mac.com> | 2011-08-29 19:36:44 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-29 19:36:44 +0000 |
| commit | 0da10cf44d0f22111dae728bb535ade2283d976b (patch) | |
| tree | 74856b2e0ad0b66d5f374819a9af807a8ff4ecf1 /test | |
| parent | 98ba358fdb0596d0d705a4e5295c7932f979b701 (diff) | |
| download | external_llvm-0da10cf44d0f22111dae728bb535ade2283d976b.zip external_llvm-0da10cf44d0f22111dae728bb535ade2283d976b.tar.gz external_llvm-0da10cf44d0f22111dae728bb535ade2283d976b.tar.bz2 | |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 8 | ||||
| -rw-r--r-- | test/MC/ARM/simple-fp-encoding.s | 14 |
2 files changed, 15 insertions, 7 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index d466662..861d50f 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1884,6 +1884,14 @@ Lforward: @ CHECK: strex r2, r1, [r7] @ encoding: [0x91,0x2f,0x87,0xe1] @ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1] +@------------------------------------------------------------------------------ +@ STR +@------------------------------------------------------------------------------ + strpl r3, [r10, #-0]! + strpl r3, [r10, #0]! + +@ CHECK: strpl r3, [r10, #-0]! @ encoding: [0x00,0x30,0x2a,0x55] +@ CHECK: strpl r3, [r10]! @ encoding: [0x00,0x30,0xaa,0x55] @------------------------------------------------------------------------------ @ SUB diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index 8917380..88dd81a 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -2,7 +2,7 @@ @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] vadd.f64 d16, d17, d16 - + @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] vadd.f32 s0, s1, s0 @@ -47,7 +47,7 @@ @ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] vabs.f32 s0, s0 - + @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] vcvt.f32.f64 s0, d16 @@ -116,7 +116,7 @@ @ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] @ vmrs apsr_nzcv, fpscr - + @ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] vnegne.f64 d16, d16 @@ -173,13 +173,13 @@ @ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] vldr.64 d1, [r2, #32] vldr.64 d1, [r2, #-32] - + @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] vldr.64 d2, [r3] @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] -@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed] vldr.64 d3, [pc] vldr.64 d3, [pc,#0] vldr.64 d3, [pc,#-0] @@ -191,13 +191,13 @@ @ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] vldr.32 s1, [r2, #32] vldr.32 s1, [r2, #-32] - + @ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] vldr.32 s2, [r3] @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] -@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed] vldr.32 s5, [pc] vldr.32 s5, [pc,#0] vldr.32 s5, [pc,#-0] |