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author | Sirish Pande <spande@codeaurora.org> | 2012-04-23 17:49:20 +0000 |
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committer | Sirish Pande <spande@codeaurora.org> | 2012-04-23 17:49:20 +0000 |
commit | 0dac3919e52e28308deba555bbcb6286674d5495 (patch) | |
tree | e282036a59d3425345998090955e7eae538cb5f5 /test | |
parent | 9f6852dcc292882845876ecc1181710a5c35fb1f (diff) | |
download | external_llvm-0dac3919e52e28308deba555bbcb6286674d5495.zip external_llvm-0dac3919e52e28308deba555bbcb6286674d5495.tar.gz external_llvm-0dac3919e52e28308deba555bbcb6286674d5495.tar.bz2 |
Support for Hexagon VLIW Packetizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155365 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/Hexagon/dualstore.ll | 19 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/fusedandshift.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/newvaluestore.ll | 22 |
3 files changed, 57 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/dualstore.ll b/test/CodeGen/Hexagon/dualstore.ll new file mode 100644 index 0000000..add5e47 --- /dev/null +++ b/test/CodeGen/Hexagon/dualstore.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate dual stores in one packet in V4 + +; CHECK: { +; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}} = r{{[0-9]+}} +; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}} = r{{[0-9]+}} +; CHECK-NEXT: } + + +@Reg = global i32 0, align 4 +define i32 @main() nounwind { +entry: + %number= alloca i32, align 4 + store i32 500000, i32* %number, align 4 + %number1= alloca i32, align 4 + store i32 100000, i32* %number1, align 4 + ret i32 0 +} + diff --git a/test/CodeGen/Hexagon/fusedandshift.ll b/test/CodeGen/Hexagon/fusedandshift.ll new file mode 100644 index 0000000..022b3c6 --- /dev/null +++ b/test/CodeGen/Hexagon/fusedandshift.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate fused logical and with shift instruction. + +; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}}) + +define i32 @main(i16* %a, i16* %b) nounwind { + entry: + %0 = load i16* %a, align 2 + %conv1 = sext i16 %0 to i32 + %shr1 = ashr i32 %conv1, 3 + %and1 = and i32 %shr1, 15 + %conv2 = trunc i32 %and1 to i16 + store i16 %conv2, i16* %b, align 2 + ret i32 0 +} + diff --git a/test/CodeGen/Hexagon/newvaluestore.ll b/test/CodeGen/Hexagon/newvaluestore.ll new file mode 100644 index 0000000..ab69b22 --- /dev/null +++ b/test/CodeGen/Hexagon/newvaluestore.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate new value store packet in V4 + +@i = global i32 0, align 4 +@j = global i32 10, align 4 +@k = global i32 100, align 4 + +define i32 @main() nounwind { +entry: +; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}.new + %number1 = alloca i32, align 4 + %number2 = alloca i32, align 4 + %number3 = alloca i32, align 4 + %0 = load i32 * @i, align 4 + store i32 %0, i32* %number1, align 4 + %1 = load i32 * @j, align 4 + store i32 %1, i32* %number2, align 4 + %2 = load i32 * @k, align 4 + store i32 %2, i32* %number3, align 4 + ret i32 %0 +} + |