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authorStuart Hastings <stuart@apple.com>2011-05-20 19:04:40 +0000
committerStuart Hastings <stuart@apple.com>2011-05-20 19:04:40 +0000
commit0e29ed081b24359978916b997e91e3e1e2293915 (patch)
tree9b66112216898acc26dbf280a06985a3bb5ca23e /test
parent17a1e8775119db75ece41e041eeb6480793696ff (diff)
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Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
rdar://problem/8614450 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/div8.ll22
1 files changed, 22 insertions, 0 deletions
diff --git a/test/CodeGen/X86/div8.ll b/test/CodeGen/X86/div8.ll
new file mode 100644
index 0000000..0825f79
--- /dev/null
+++ b/test/CodeGen/X86/div8.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | FileCheck %s
+; ModuleID = '8div.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.6.6"
+
+define signext i8 @test_div(i8 %dividend, i8 %divisor) nounwind ssp {
+entry:
+ %dividend.addr = alloca i8, align 2
+ %divisor.addr = alloca i8, align 1
+ %quotient = alloca i8, align 1
+ store i8 %dividend, i8* %dividend.addr, align 2
+ store i8 %divisor, i8* %divisor.addr, align 1
+ %tmp = load i8* %dividend.addr, align 2
+ %tmp1 = load i8* %divisor.addr, align 1
+; Insist on i8->i32 zero extension, even though divb demands only i16:
+; CHECK: movzbl {{.*}}%eax
+; CHECK: divb
+ %div = udiv i8 %tmp, %tmp1
+ store i8 %div, i8* %quotient, align 1
+ %tmp4 = load i8* %quotient, align 1
+ ret i8 %tmp4
+}