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authorJush Lu <jush.msn@gmail.com>2012-08-03 02:37:48 +0000
committerJush Lu <jush.msn@gmail.com>2012-08-03 02:37:48 +0000
commit2946549a2817681f9117662139cc0f2241939965 (patch)
treec0fa5ae54a0ed16b0fdf7c5a9eccd71d884305c0 /test
parent8b52c855b3fc2ec496be8b5fd11c1c1f5bb224f0 (diff)
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[arm-fast-isel] Add support for shl, lshr, and ashr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/fast-isel-shifter.ll50
1 files changed, 50 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel-shifter.ll b/test/CodeGen/ARM/fast-isel-shifter.ll
new file mode 100644
index 0000000..111818b
--- /dev/null
+++ b/test/CodeGen/ARM/fast-isel-shifter.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+
+define i32 @shl() nounwind ssp {
+entry:
+; ARM: shl
+; ARM: lsl r0, r0, #2
+ %shl = shl i32 -1, 2
+ ret i32 %shl
+}
+
+define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
+entry:
+; ARM: shl_reg
+; ARM: lsl r0, r0, r1
+ %shl = shl i32 %src1, %src2
+ ret i32 %shl
+}
+
+define i32 @lshr() nounwind ssp {
+entry:
+; ARM: lshr
+; ARM: lsr r0, r0, #2
+ %lshr = lshr i32 -1, 2
+ ret i32 %lshr
+}
+
+define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
+entry:
+; ARM: lshr_reg
+; ARM: lsr r0, r0, r1
+ %lshr = lshr i32 %src1, %src2
+ ret i32 %lshr
+}
+
+define i32 @ashr() nounwind ssp {
+entry:
+; ARM: ashr
+; ARM: asr r0, r0, #2
+ %ashr = ashr i32 -1, 2
+ ret i32 %ashr
+}
+
+define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
+entry:
+; ARM: ashr_reg
+; ARM: asr r0, r0, r1
+ %ashr = ashr i32 %src1, %src2
+ ret i32 %ashr
+}
+