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authorBill Wendling <isanbard@gmail.com>2013-12-08 00:17:29 +0000
committerBill Wendling <isanbard@gmail.com>2013-12-08 00:17:29 +0000
commit2bdc0dd2db145591eb3fdc01fa0b2a3d831f334b (patch)
tree6f14746b9594fe4197c5fb35297b079867ede879 /test
parent92fe16ec5863b65dfe495300e968ed8ddd10cf85 (diff)
downloadexternal_llvm-2bdc0dd2db145591eb3fdc01fa0b2a3d831f334b.zip
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Merging r196588:
------------------------------------------------------------------------ r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines Bug 18149: [AArch32] VSel instructions has no ARMCC field The current peephole optimizing for compare inst assumes an instr that uses CPSR has an MO for ARM Cond code.However, for VSEL instructions (vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do they support the modification of Cond Code. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/sub-cmp-peephole.ll60
1 files changed, 60 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll
index 1b411e3..19727da 100644
--- a/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -1,4 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
+
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
@@ -84,3 +87,60 @@ land.lhs.true: ; preds = %num2long.exit
if.end11: ; preds = %num2long.exit
ret i32 23
}
+
+define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
+entry:
+; CHECK-LABEL: float_sel:
+; CHECK-NOT: cmp
+; V8-LABEL: float_sel:
+; V8-NOT: cmp
+; V8: vseleq.f32
+ %sub = sub i32 %a, %b
+ %cmp = icmp eq i32 %sub, 0
+ %ret = select i1 %cmp, float %x, float %y
+ ret float %ret
+}
+
+define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
+entry:
+; CHECK-LABEL: double_sel:
+; CHECK-NOT: cmp
+; V8-LABEL: double_sel:
+; V8-NOT: cmp
+; V8: vseleq.f64
+ %sub = sub i32 %a, %b
+ %cmp = icmp eq i32 %sub, 0
+ %ret = select i1 %cmp, double %x, double %y
+ ret double %ret
+}
+
+@t = common global i32 0
+define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
+entry:
+; CHECK-LABEL: double_sub:
+; CHECK: subs
+; CHECK-NOT: cmp
+; V8-LABEL: double_sub:
+; V8: vsel
+ %cmp = icmp sgt i32 %a, %b
+ %sub = sub i32 %a, %b
+ store i32 %sub, i32* @t
+ %ret = select i1 %cmp, double %x, double %y
+ ret double %ret
+}
+
+define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
+entry:
+; V7-LABEL: double_sub_swap:
+; V7-NOT: cmp
+; V7: subs
+; V8-LABEL: double_sub_swap:
+; V8-NOT: subs
+; V8: cmp
+; V8: vsel
+ %cmp = icmp sgt i32 %a, %b
+ %sub = sub i32 %b, %a
+ %ret = select i1 %cmp, double %x, double %y
+ store i32 %sub, i32* @t
+ ret double %ret
+}