diff options
author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 12:04:44 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 12:04:44 +0000 |
commit | 38a10ff063971c2f7f7384cceba3253bca32e27a (patch) | |
tree | b33b11ee7611a9aac0ec323faa06dd700e6233fe /test | |
parent | d4bf7a3853dab12c11cbfc8088fd76f548a8d017 (diff) | |
download | external_llvm-38a10ff063971c2f7f7384cceba3253bca32e27a.zip external_llvm-38a10ff063971c2f7f7384cceba3253bca32e27a.tar.gz external_llvm-38a10ff063971c2f7f7384cceba3253bca32e27a.tar.bz2 |
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics)
This required correcting the definition of the bsel and bseli intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/Mips/msa/compare.ll | 326 | ||||
-rw-r--r-- | test/CodeGen/Mips/msa/compare_float.ll | 80 | ||||
-rw-r--r-- | test/CodeGen/Mips/msa/i8.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/Mips/msa/vec.ll | 10 |
4 files changed, 413 insertions, 7 deletions
diff --git a/test/CodeGen/Mips/msa/compare.ll b/test/CodeGen/Mips/msa/compare.ll index 34e619b..fc83f44 100644 --- a/test/CodeGen/Mips/msa/compare.ll +++ b/test/CodeGen/Mips/msa/compare.ll @@ -639,3 +639,329 @@ define void @clti_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind { ret void ; CHECK: .size clti_u_v2i64 } + +define void @bsel_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b, + <16 x i8>* %c) nounwind { + ; CHECK: bsel_s_v16i8: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = load <16 x i8>* %c + ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7) + %4 = icmp sgt <16 x i8> %1, %2 + ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <16 x i8> %5, <16 x i8>* %d + ; CHECK-DAG: st.b [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_s_v16i8 +} + +define void @bsel_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b, + <8 x i16>* %c) nounwind { + ; CHECK: bsel_s_v8i16: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = load <8 x i16>* %c + ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7) + %4 = icmp sgt <8 x i16> %1, %2 + ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <8 x i16> %5, <8 x i16>* %d + ; CHECK-DAG: st.h [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_s_v8i16 +} + +define void @bsel_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b, + <4 x i32>* %c) nounwind { + ; CHECK: bsel_s_v4i32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = load <4 x i32>* %c + ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) + %4 = icmp sgt <4 x i32> %1, %2 + ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <4 x i32> %5, <4 x i32>* %d + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_s_v4i32 +} + +define void @bsel_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b, + <2 x i64>* %c) nounwind { + ; CHECK: bsel_s_v2i64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = load <2 x i64>* %c + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) + %4 = icmp sgt <2 x i64> %1, %2 + ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <2 x i64> %5, <2 x i64>* %d + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_s_v2i64 +} + +define void @bsel_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b, + <16 x i8>* %c) nounwind { + ; CHECK: bsel_u_v16i8: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = load <16 x i8>* %c + ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7) + %4 = icmp ugt <16 x i8> %1, %2 + ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <16 x i8> %5, <16 x i8>* %d + ; CHECK-DAG: st.b [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_u_v16i8 +} + +define void @bsel_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b, + <8 x i16>* %c) nounwind { + ; CHECK: bsel_u_v8i16: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = load <8 x i16>* %c + ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7) + %4 = icmp ugt <8 x i16> %1, %2 + ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <8 x i16> %5, <8 x i16>* %d + ; CHECK-DAG: st.h [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_u_v8i16 +} + +define void @bsel_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b, + <4 x i32>* %c) nounwind { + ; CHECK: bsel_u_v4i32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = load <4 x i32>* %c + ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) + %4 = icmp ugt <4 x i32> %1, %2 + ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <4 x i32> %5, <4 x i32>* %d + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_u_v4i32 +} + +define void @bsel_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b, + <2 x i64>* %c) nounwind { + ; CHECK: bsel_u_v2i64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = load <2 x i64>* %c + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) + %4 = icmp ugt <2 x i64> %1, %2 + ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <2 x i64> %5, <2 x i64>* %d + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_u_v2i64 +} + +define void @bseli_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b, + <16 x i8>* %c) nounwind { + ; CHECK: bseli_s_v16i8: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = icmp sgt <16 x i8> %1, %2 + ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1 + store <16 x i8> %4, <16 x i8>* %d + ; CHECK-DAG: st.b [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_s_v16i8 +} + +define void @bseli_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b, + <8 x i16>* %c) nounwind { + ; CHECK: bseli_s_v8i16: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = icmp sgt <8 x i16> %1, %2 + ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <8 x i16> %4, <8 x i16>* %d + ; CHECK-DAG: st.h [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_s_v8i16 +} + +define void @bseli_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b, + <4 x i32>* %c) nounwind { + ; CHECK: bseli_s_v4i32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = icmp sgt <4 x i32> %1, %2 + ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <4 x i32> %4, <4 x i32>* %d + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_s_v4i32 +} + +define void @bseli_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b, + <2 x i64>* %c) nounwind { + ; CHECK: bseli_s_v2i64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = icmp sgt <2 x i64> %1, %2 + ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1> + ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <2 x i64> %4, <2 x i64>* %d + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_s_v2i64 +} + +define void @bseli_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b, + <16 x i8>* %c) nounwind { + ; CHECK: bseli_u_v16i8: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = icmp ugt <16 x i8> %1, %2 + ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1 + store <16 x i8> %4, <16 x i8>* %d + ; CHECK-DAG: st.b [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_u_v16i8 +} + +define void @bseli_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b, + <8 x i16>* %c) nounwind { + ; CHECK: bseli_u_v8i16: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = icmp ugt <8 x i16> %1, %2 + ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <8 x i16> %4, <8 x i16>* %d + ; CHECK-DAG: st.h [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_u_v8i16 +} + +define void @bseli_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b, + <4 x i32>* %c) nounwind { + ; CHECK: bseli_u_v4i32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = icmp ugt <4 x i32> %1, %2 + ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <4 x i32> %4, <4 x i32>* %d + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_u_v4i32 +} + +define void @bseli_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b, + <2 x i64>* %c) nounwind { + ; CHECK: bseli_u_v2i64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = icmp ugt <2 x i64> %1, %2 + ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1> + ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <2 x i64> %4, <2 x i64>* %d + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_u_v2i64 +} diff --git a/test/CodeGen/Mips/msa/compare_float.ll b/test/CodeGen/Mips/msa/compare_float.ll index b75f839..106653f 100644 --- a/test/CodeGen/Mips/msa/compare_float.ll +++ b/test/CodeGen/Mips/msa/compare_float.ll @@ -516,3 +516,83 @@ define void @true_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounw ; CHECK-DAG: st.d [[R4]], 0($4) ; CHECK: .size true_v2f64 } + +define void @bsel_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, + <4 x float>* %c) nounwind { + ; CHECK: bsel_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x float>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = load <4 x float>* %c + ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) + %4 = fcmp ogt <4 x float> %1, %2 + ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <4 x i1> %4, <4 x float> %1, <4 x float> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <4 x float> %5, <4 x float>* %d + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_v4f32 +} + +define void @bsel_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, + <2 x double>* %c) nounwind { + ; CHECK: bsel_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x double>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = load <2 x double>* %c + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) + %4 = fcmp ogt <2 x double> %1, %2 + ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %5 = select <2 x i1> %4, <2 x double> %1, <2 x double> %3 + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + store <2 x double> %5, <2 x double>* %d + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size bsel_v2f64 +} + +define void @bseli_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, + <4 x float>* %c) nounwind { + ; CHECK: bseli_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x float>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = fcmp ogt <4 x float> %1, %2 + ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <4 x i1> %3, <4 x float> %1, <4 x float> zeroinitializer + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3:\$w[0-9]+]] + store <4 x float> %4, <4 x float>* %d + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_v4f32 +} + +define void @bseli_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, + <2 x double>* %c) nounwind { + ; CHECK: bseli_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x double>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = fcmp ogt <2 x double> %1, %2 + ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] + %4 = select <2 x i1> %3, <2 x double> %1, <2 x double> zeroinitializer + ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3:\$w[0-9]+]] + store <2 x double> %4, <2 x double>* %d + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size bseli_v2f64 +} diff --git a/test/CodeGen/Mips/msa/i8.ll b/test/CodeGen/Mips/msa/i8.ll index e629b04..ad8d0a4 100644 --- a/test/CodeGen/Mips/msa/i8.ll +++ b/test/CodeGen/Mips/msa/i8.ll @@ -65,12 +65,12 @@ declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, i32) nounwind define void @llvm_mips_bseli_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1 - %1 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, i32 25) + %1 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %0, i32 25) store <16 x i8> %1, <16 x i8>* @llvm_mips_bseli_b_RES ret void } -declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, i32) nounwind +declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind ; CHECK: llvm_mips_bseli_b_test: ; CHECK: ld.b diff --git a/test/CodeGen/Mips/msa/vec.ll b/test/CodeGen/Mips/msa/vec.ll index 7ad640b..ee13493 100644 --- a/test/CodeGen/Mips/msa/vec.ll +++ b/test/CodeGen/Mips/msa/vec.ll @@ -355,7 +355,7 @@ entry: %1 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG2 %2 = bitcast <16 x i8> %0 to <16 x i8> %3 = bitcast <16 x i8> %1 to <16 x i8> - %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3) + %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %2, <16 x i8> %3) %5 = bitcast <16 x i8> %4 to <16 x i8> store <16 x i8> %5, <16 x i8>* @llvm_mips_bsel_v_b_RES ret void @@ -378,7 +378,7 @@ entry: %1 = load <8 x i16>* @llvm_mips_bsel_v_h_ARG2 %2 = bitcast <8 x i16> %0 to <16 x i8> %3 = bitcast <8 x i16> %1 to <16 x i8> - %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3) + %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %2, <16 x i8> %3) %5 = bitcast <16 x i8> %4 to <8 x i16> store <8 x i16> %5, <8 x i16>* @llvm_mips_bsel_v_h_RES ret void @@ -401,7 +401,7 @@ entry: %1 = load <4 x i32>* @llvm_mips_bsel_v_w_ARG2 %2 = bitcast <4 x i32> %0 to <16 x i8> %3 = bitcast <4 x i32> %1 to <16 x i8> - %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3) + %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %2, <16 x i8> %3) %5 = bitcast <16 x i8> %4 to <4 x i32> store <4 x i32> %5, <4 x i32>* @llvm_mips_bsel_v_w_RES ret void @@ -424,7 +424,7 @@ entry: %1 = load <2 x i64>* @llvm_mips_bsel_v_d_ARG2 %2 = bitcast <2 x i64> %0 to <16 x i8> %3 = bitcast <2 x i64> %1 to <16 x i8> - %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3) + %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %2, <16 x i8> %3) %5 = bitcast <16 x i8> %4 to <2 x i64> store <2 x i64> %5, <2 x i64>* @llvm_mips_bsel_v_d_RES ret void @@ -848,7 +848,7 @@ entry: declare <16 x i8> @llvm.mips.and.v(<16 x i8>, <16 x i8>) nounwind declare <16 x i8> @llvm.mips.bmnz.v(<16 x i8>, <16 x i8>) nounwind declare <16 x i8> @llvm.mips.bmz.v(<16 x i8>, <16 x i8>) nounwind -declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>, <16 x i8>) nounwind declare <16 x i8> @llvm.mips.nor.v(<16 x i8>, <16 x i8>) nounwind declare <16 x i8> @llvm.mips.or.v(<16 x i8>, <16 x i8>) nounwind declare <16 x i8> @llvm.mips.xor.v(<16 x i8>, <16 x i8>) nounwind |