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author | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-17 18:12:29 +0000 |
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committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-17 18:12:29 +0000 |
commit | 3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6 (patch) | |
tree | 6c7f94df9005b1ef857c4760b82a4f734f8c62ff /test | |
parent | 9bb874cea257753349854106a994999981290259 (diff) | |
download | external_llvm-3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6.zip external_llvm-3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6.tar.gz external_llvm-3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6.tar.bz2 |
[AArch64] Add support for NEON scalar three register different instruction
class. The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/AArch64/neon-scalar-mul.ll | 75 | ||||
-rw-r--r-- | test/MC/AArch64/neon-diagnostics.s | 42 | ||||
-rw-r--r-- | test/MC/AArch64/neon-scalar-mul.s | 30 | ||||
-rw-r--r-- | test/MC/Disassembler/AArch64/neon-instructions.txt | 24 |
4 files changed, 171 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/neon-scalar-mul.ll b/test/CodeGen/AArch64/neon-scalar-mul.ll index 6914a08..3129df2 100644 --- a/test/CodeGen/AArch64/neon-scalar-mul.ll +++ b/test/CodeGen/AArch64/neon-scalar-mul.ll @@ -68,3 +68,78 @@ define double @test_vmulxd_f64(double %a, double %b) { declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>) declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>) + +define i32 @test_vqdmlalh_s16(i16 %a, i16 %b) { +; CHECK: test_vqdmlalh_s16 +; CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} +entry: + %vqdmlal.i = insertelement <1 x i16> undef, i16 %a, i32 0 + %vqdmlal1.i = insertelement <1 x i16> undef, i16 %b, i32 0 + %vqdmlal2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16> %vqdmlal.i, <1 x i16> %vqdmlal1.i) + %0 = extractelement <1 x i32> %vqdmlal2.i, i32 0 + ret i32 %0 +} + +define i64 @test_vqdmlals_s32(i32 %a, i32 %b) { +; CHECK: test_vqdmlals_s32 +; CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +entry: + %vqdmlal.i = insertelement <1 x i32> undef, i32 %a, i32 0 + %vqdmlal1.i = insertelement <1 x i32> undef, i32 %b, i32 0 + %vqdmlal2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32> %vqdmlal.i, <1 x i32> %vqdmlal1.i) + %0 = extractelement <1 x i64> %vqdmlal2.i, i32 0 + ret i64 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16>, <1 x i16>) +declare <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32>, <1 x i32>) + +define i32 @test_vqdmlslh_s16(i16 %a, i16 %b) { +; CHECK: test_vqdmlslh_s16 +; CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} +entry: + %vqdmlsl.i = insertelement <1 x i16> undef, i16 %a, i32 0 + %vqdmlsl1.i = insertelement <1 x i16> undef, i16 %b, i32 0 + %vqdmlsl2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16> %vqdmlsl.i, <1 x i16> %vqdmlsl1.i) + %0 = extractelement <1 x i32> %vqdmlsl2.i, i32 0 + ret i32 %0 +} + +define i64 @test_vqdmlsls_s32(i32 %a, i32 %b) { +; CHECK: test_vqdmlsls_s32 +; CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +entry: + %vqdmlsl.i = insertelement <1 x i32> undef, i32 %a, i32 0 + %vqdmlsl1.i = insertelement <1 x i32> undef, i32 %b, i32 0 + %vqdmlsl2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32> %vqdmlsl.i, <1 x i32> %vqdmlsl1.i) + %0 = extractelement <1 x i64> %vqdmlsl2.i, i32 0 + ret i64 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16>, <1 x i16>) +declare <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32>, <1 x i32>) + +define i32 @test_vqdmullh_s16(i16 %a, i16 %b) { +; CHECK: test_vqdmullh_s16 +; CHECK: sqdmull {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} +entry: + %vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0 + %vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0 + %vqdmull2.i = call <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i) + %0 = extractelement <1 x i32> %vqdmull2.i, i32 0 + ret i32 %0 +} + +define i64 @test_vqdmulls_s32(i32 %a, i32 %b) { +; CHECK: test_vqdmulls_s32 +; CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +entry: + %vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0 + %vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0 + %vqdmull2.i = call <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i) + %0 = extractelement <1 x i64> %vqdmull2.i, i32 0 + ret i64 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>) +declare <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>) diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index 411ea9f..44e4561 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -4460,3 +4460,45 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: neg d29, s24 // CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Add Long +//---------------------------------------------------------------------- + + sqdmlal s17, h27, s12 + sqdmlal d19, s24, d12 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal s17, h27, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal d19, s24, d12 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Subtract Long +//---------------------------------------------------------------------- + + sqdmlsl s14, h12, s25 + sqdmlsl d12, s23, d13 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl s14, h12, s25 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl d12, s23, d13 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply Long +//---------------------------------------------------------------------- + + sqdmull s12, h22, s12 + sqdmull d15, s22, d12 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull s12, h22, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull d15, s22, d12 +// CHECK-ERROR: ^ diff --git a/test/MC/AArch64/neon-scalar-mul.s b/test/MC/AArch64/neon-scalar-mul.s index 8caddb4..e33bdad 100644 --- a/test/MC/AArch64/neon-scalar-mul.s +++ b/test/MC/AArch64/neon-scalar-mul.s @@ -31,3 +31,33 @@ // CHECK: fmulx s20, s22, s15 // encoding: [0xd4,0xde,0x2f,0x5e] // CHECK: fmulx d23, d11, d1 // encoding: [0x77,0xdd,0x61,0x5e] + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Add Long +//---------------------------------------------------------------------- + + sqdmlal s17, h27, h12 + sqdmlal d19, s24, s12 + +// CHECK: sqdmlal s17, h27, h12 // encoding: [0x71,0x93,0x6c,0x5e] +// CHECK: sqdmlal d19, s24, s12 // encoding: [0x13,0x93,0xac,0x5e] + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Subtract Long +//---------------------------------------------------------------------- + + sqdmlsl s14, h12, h25 + sqdmlsl d12, s23, s13 + +// CHECK: sqdmlsl s14, h12, h25 // encoding: [0x8e,0xb1,0x79,0x5e] +// CHECK: sqdmlsl d12, s23, s13 // encoding: [0xec,0xb2,0xad,0x5e] + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply Long +//---------------------------------------------------------------------- + + sqdmull s12, h22, h12 + sqdmull d15, s22, s12 + +// CHECK: sqdmull s12, h22, h12 // encoding: [0xcc,0xd2,0x6c,0x5e] +// CHECK: sqdmull d15, s22, s12 // encoding: [0xcf,0xd2,0xac,0x5e] diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index c70a2f6..364259f 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1659,3 +1659,27 @@ 0xf4,0x39,0x60,0x7e 0x95,0x39,0xa0,0x7e 0xd2,0x3a,0xe0,0x7e + +#---------------------------------------------------------------------- +# Signed Saturating Doubling Multiply-Add Long +#---------------------------------------------------------------------- +# CHECK: sqdmlal s17, h27, h12 +# CHECK: sqdmlal d19, s24, s12 +0x71,0x93,0x6c,0x5e +0x13,0x93,0xac,0x5e + +#---------------------------------------------------------------------- +# Signed Saturating Doubling Multiply-Subtract Long +#---------------------------------------------------------------------- +# CHECK: sqdmlsl s14, h12, h25 +# CHECK: sqdmlsl d12, s23, s13 +0x8e,0xb1,0x79,0x5e +0xec,0xb2,0xad,0x5e + +#---------------------------------------------------------------------- +# Signed Saturating Doubling Multiply Long +#---------------------------------------------------------------------- +# CHECK: sqdmull s12, h22, h12 +# CHECK: sqdmull d15, s22, s12 +0xcc,0xd2,0x6c,0x5e +0xcf,0xd2,0xac,0x5e |