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author | Jyotsna Verma <jverma@codeaurora.org> | 2013-02-05 16:42:24 +0000 |
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committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-02-05 16:42:24 +0000 |
commit | 4210da7253e04f7bf3267cbfb2b80f9116e408fa (patch) | |
tree | 58d7ad147732221f20b0d4b283de0ccf3a6888af /test | |
parent | 1b2c94713600531ddeefb23cd10c49cd533aa09b (diff) | |
download | external_llvm-4210da7253e04f7bf3267cbfb2b80f9116e408fa.zip external_llvm-4210da7253e04f7bf3267cbfb2b80f9116e408fa.tar.gz external_llvm-4210da7253e04f7bf3267cbfb2b80f9116e408fa.tar.bz2 |
Hexagon: Add V4 compare instructions. Enable relationship mapping
for the existing instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/Hexagon/cmp-to-genreg.ll | 34 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/cmp-to-predreg.ll | 43 |
2 files changed, 77 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/cmp-to-genreg.ll b/test/CodeGen/Hexagon/cmp-to-genreg.ll new file mode 100644 index 0000000..97cf51c --- /dev/null +++ b/test/CodeGen/Hexagon/cmp-to-genreg.ll @@ -0,0 +1,34 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate compare to general register. + +define i32 @compare1(i32 %a) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}#120) +entry: + %cmp = icmp eq i32 %a, 120 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @compare2(i32 %a) nounwind readnone { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#120) +entry: + %cmp = icmp ne i32 %a, 120 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @compare3(i32 %a, i32 %b) nounwind readnone { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}}) +entry: + %cmp = icmp eq i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @compare4(i32 %a, i32 %b) nounwind readnone { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}}) +entry: + %cmp = icmp ne i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} diff --git a/test/CodeGen/Hexagon/cmp-to-predreg.ll b/test/CodeGen/Hexagon/cmp-to-predreg.ll new file mode 100644 index 0000000..d430b90 --- /dev/null +++ b/test/CodeGen/Hexagon/cmp-to-predreg.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate compare to predicate register. + +define i32 @compare1(i32 %a, i32 %b) nounwind { +; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}}) +entry: + %cmp = icmp ne i32 %a, %b + %add = add nsw i32 %a, %b + %sub = sub nsw i32 %a, %b + %add.sub = select i1 %cmp, i32 %add, i32 %sub + ret i32 %add.sub +} + +define i32 @compare2(i32 %a) nounwind { +; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#10) +entry: + %cmp = icmp ne i32 %a, 10 + %add = add nsw i32 %a, 10 + %sub = sub nsw i32 %a, 10 + %add.sub = select i1 %cmp, i32 %add, i32 %sub + ret i32 %add.sub +} + +define i32 @compare3(i32 %a, i32 %b) nounwind { +; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}r{{[0-9]+}}) +entry: + %cmp = icmp sgt i32 %a, %b + %sub = sub nsw i32 %a, %b + %add = add nsw i32 %a, %b + %sub.add = select i1 %cmp, i32 %sub, i32 %add + ret i32 %sub.add +} + +define i32 @compare4(i32 %a) nounwind { +; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}#10) +entry: + %cmp = icmp sgt i32 %a, 10 + %sub = sub nsw i32 %a, 10 + %add = add nsw i32 %a, 10 + %sub.add = select i1 %cmp, i32 %sub, i32 %add + ret i32 %sub.add +} + |