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authorReed Kotler <rkotler@mips.com>2013-02-23 03:09:56 +0000
committerReed Kotler <rkotler@mips.com>2013-02-23 03:09:56 +0000
commit50354a3f4a5c9e3689d502a935430f2a57a44af2 (patch)
treef379d66106c6b57591a580e3a6bfc363fdb03d6f /test
parent1e8ed2537b3e4b2175cd9e62626f07606c62cfa0 (diff)
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Expand pseudos/macros for Selt. This is the last of the complex
macros.The rest is some small misc. stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Mips/br-jmp.ll3
-rw-r--r--test/CodeGen/Mips/selpat.ll18
2 files changed, 11 insertions, 10 deletions
diff --git a/test/CodeGen/Mips/br-jmp.ll b/test/CodeGen/Mips/br-jmp.ll
index 9c48e91..9ca8d15 100644
--- a/test/CodeGen/Mips/br-jmp.ll
+++ b/test/CodeGen/Mips/br-jmp.ll
@@ -14,4 +14,5 @@ bosco: ; preds = %bosco, %entry
; CHECK-PIC: b $BB0_1
; CHECK-STATIC: j $BB0_1
; CHECK-PIC16: b $BB0_1
-; CHECK-STATIC16: b $BB0_1 \ No newline at end of file
+; CHECK-STATIC16: b $BB0_1
+
diff --git a/test/CodeGen/Mips/selpat.ll b/test/CodeGen/Mips/selpat.ll
index 721cb9f..8eda8de 100644
--- a/test/CodeGen/Mips/selpat.ll
+++ b/test/CodeGen/Mips/selpat.ll
@@ -20,7 +20,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
-; 16: bteqz .+4
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
store i32 %cond, i32* @z2, align 4
%4 = load i32* @c, align 4
@@ -91,7 +91,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: bteqz .+4
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp sge i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2
@@ -112,7 +112,7 @@ entry:
%1 = load i32* @b, align 4
%cmp = icmp sgt i32 %0, %1
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: btnez .+4
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%2 = load i32* @f, align 4
%3 = load i32* @t, align 4
@@ -141,7 +141,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: bteqz .+4
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp sle i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2
@@ -165,7 +165,7 @@ entry:
%cond = select i1 %cmp, i32 %1, i32 %2
store i32 %cond, i32* @z1, align 4
; 16: slti ${{[0-9]+}}, {{[0-9]+}}
-; 16: btnez .+4
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%3 = load i32* @b, align 4
%cmp1 = icmp slt i32 %3, 2
@@ -192,7 +192,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
-; 16: btnez .+4
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
store i32 %cond, i32* @z2, align 4
%4 = load i32* @c, align 4
@@ -284,7 +284,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: bteqz .+4
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp uge i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2
@@ -309,7 +309,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: btnez .+4
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp ugt i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2
@@ -334,7 +334,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: bteqz .+4
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp ule i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2