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authorEli Friedman <eli.friedman@gmail.com>2012-06-25 23:42:33 +0000
committerEli Friedman <eli.friedman@gmail.com>2012-06-25 23:42:33 +0000
commit52d418df5d67ffdf4c9782c5fa8d3fdbd2478631 (patch)
tree01be5d4e040d5946a893efac8f823dab3a40681e /test
parentfd99cabdc6de1eadda0e9a45d0acc8aa7c2f8f67 (diff)
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Make some ugly hacks for inline asm operands which name a specific register a bit more thorough. PR13196.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/asm-reg-type-mismatch.ll (renamed from test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll)19
1 files changed, 16 insertions, 3 deletions
diff --git a/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll b/test/CodeGen/X86/asm-reg-type-mismatch.ll
index f0d46a0..47accdb 100644
--- a/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
+++ b/test/CodeGen/X86/asm-reg-type-mismatch.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -mcpu=core2 | grep xorps | count 2
-; RUN: llc < %s -mcpu=core2 | not grep movap
+; RUN: llc < %s -mcpu=core2 | FileCheck %s
; PR2715
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
@@ -11,8 +10,22 @@ target triple = "x86_64-unknown-linux-gnu"
%struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 }
%struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix }
-define i32 @XPTC_InvokeByIndex(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
+define i32 @test1(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
entry:
call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind
ret i32 0
+ ; CHECK: test1
+ ; CHECK-NOT: movap
+ ; CHECK: xorps
+ ; CHECK: xorps
+ ; CHECK-NOT: movap
+}
+
+define i64 @test2() nounwind {
+entry:
+ %0 = tail call i64 asm sideeffect "movq $1, $0", "={xmm7},*m,~{dirflag},~{fpsr},~{flags}"(i64* null) nounwind
+ ret i64 %0
+ ; CHECK: test2
+ ; CHECK: movq {{.*}}, %xmm7
+ ; CHECK: movd %xmm7, %rax
}