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author | Evan Cheng <evan.cheng@apple.com> | 2011-03-14 18:15:55 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2011-03-14 18:15:55 +0000 |
commit | 5ae1da96f2ac4a68543295f227398f8e93018eb0 (patch) | |
tree | c200ba1c32aed32bd221ca5cd0c91d05a5772bfa /test | |
parent | 21a6179c9daaaa38be40b53d6993404856e20dc1 (diff) | |
download | external_llvm-5ae1da96f2ac4a68543295f227398f8e93018eb0.zip external_llvm-5ae1da96f2ac4a68543295f227398f8e93018eb0.tar.gz external_llvm-5ae1da96f2ac4a68543295f227398f8e93018eb0.tar.bz2 |
Minor optimization. sign-ext/anyext of undef is still undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127598 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/ARM/shifter_operand.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/ARM/undef-sext.ll | 14 |
2 files changed, 19 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 01e3a92..be891bc 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -51,19 +51,19 @@ entry: declare i8* @malloc(...) -define fastcc void @test4() nounwind { +define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr r1, [r0, r0, lsl #2] -; A8: str r1, [r0, r0, lsl #2] +; A8: ldr r2, [r0, r1, lsl #2] +; A8: str r2, [r0, r1, lsl #2] ; A9: test4: -; A9: add r0, r0, r0, lsl #2 +; A9: add r0, r0, r4, lsl #2 ; A9: ldr r1, [r0] ; A9: str r1, [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* - %2 = sext i16 undef to i32 + %2 = sext i16 %addr to i32 %3 = getelementptr inbounds i32* %1, i32 %2 %4 = load i32* %3, align 4 %5 = add nsw i32 %4, 1 diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll new file mode 100644 index 0000000..2c28da3 --- /dev/null +++ b/test/CodeGen/ARM/undef-sext.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s + +; No need to sign-extend undef. + +define i32 @t(i32* %a) nounwind { +entry: +; CHECK: t: +; CHECK: ldr r0, [r0] +; CHECK: bx lr + %0 = sext i16 undef to i32 + %1 = getelementptr inbounds i32* %a, i32 %0 + %2 = load i32* %1, align 4 + ret i32 %2 +} |