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author | Reed Kotler <rkotler@mips.com> | 2013-02-20 05:45:15 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2013-02-20 05:45:15 +0000 |
commit | 65692c809efa46337bf80f12b1795e785a6e7207 (patch) | |
tree | f9f6d1833ac565de99fd963ba50bb3ba60bd36ef /test | |
parent | d326d05fb9c794e93fc7fc0601028f196600f7e2 (diff) | |
download | external_llvm-65692c809efa46337bf80f12b1795e785a6e7207.zip external_llvm-65692c809efa46337bf80f12b1795e785a6e7207.tar.gz external_llvm-65692c809efa46337bf80f12b1795e785a6e7207.tar.bz2 |
Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/Mips/seteq.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/seteqz.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/Mips/setge.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setgek.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setle.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setlt.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setltk.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setne.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setuge.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setugt.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setule.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setult.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Mips/setultk.ll | 4 |
13 files changed, 15 insertions, 15 deletions
diff --git a/test/CodeGen/Mips/seteq.ll b/test/CodeGen/Mips/seteq.ll index da840c8..5fadf78 100644 --- a/test/CodeGen/Mips/seteq.ll +++ b/test/CodeGen/Mips/seteq.ll @@ -15,7 +15,7 @@ entry: store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/seteqz.ll b/test/CodeGen/Mips/seteqz.ll index d445be6..80dc312 100644 --- a/test/CodeGen/Mips/seteqz.ll +++ b/test/CodeGen/Mips/seteqz.ll @@ -12,13 +12,13 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltiu ${{[0-9]+}}, 1 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 %1 = load i32* @j, align 4 %cmp1 = icmp eq i32 %1, 99 %conv2 = zext i1 %cmp1 to i32 store i32 %conv2, i32* @r2, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setge.ll b/test/CodeGen/Mips/setge.ll index 94b499b..8869eb8 100644 --- a/test/CodeGen/Mips/setge.ll +++ b/test/CodeGen/Mips/setge.ll @@ -17,7 +17,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp sge i32 %0, %2 diff --git a/test/CodeGen/Mips/setgek.ll b/test/CodeGen/Mips/setgek.ll index b6bae09..18a0fcf 100644 --- a/test/CodeGen/Mips/setgek.ll +++ b/test/CodeGen/Mips/setgek.ll @@ -12,7 +12,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slti ${{[0-9]+}}, -32768 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ; 16: xor ${{[0-9]+}}, ${{[0-9]+}} ret void } diff --git a/test/CodeGen/Mips/setle.ll b/test/CodeGen/Mips/setle.ll index f36fb43..2df6774 100644 --- a/test/CodeGen/Mips/setle.ll +++ b/test/CodeGen/Mips/setle.ll @@ -16,7 +16,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp sle i32 %2, %1 diff --git a/test/CodeGen/Mips/setlt.ll b/test/CodeGen/Mips/setlt.ll index 435be8e..3dac74b 100644 --- a/test/CodeGen/Mips/setlt.ll +++ b/test/CodeGen/Mips/setlt.ll @@ -16,6 +16,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setltk.ll b/test/CodeGen/Mips/setltk.ll index c0b610e..ecebc7e 100644 --- a/test/CodeGen/Mips/setltk.ll +++ b/test/CodeGen/Mips/setltk.ll @@ -15,6 +15,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slti $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $t8 +; 16: move $[[REGISTER]], $24 ret void } diff --git a/test/CodeGen/Mips/setne.ll b/test/CodeGen/Mips/setne.ll index 6460c83..9e66901 100644 --- a/test/CodeGen/Mips/setne.ll +++ b/test/CodeGen/Mips/setne.ll @@ -15,6 +15,6 @@ entry: store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, $[[REGISTER]] -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setuge.ll b/test/CodeGen/Mips/setuge.ll index ac72b66..1c9b5bb 100644 --- a/test/CodeGen/Mips/setuge.ll +++ b/test/CodeGen/Mips/setuge.ll @@ -16,7 +16,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp uge i32 %0, %2 diff --git a/test/CodeGen/Mips/setugt.ll b/test/CodeGen/Mips/setugt.ll index 328f0e3..f10b47a 100644 --- a/test/CodeGen/Mips/setugt.ll +++ b/test/CodeGen/Mips/setugt.ll @@ -16,6 +16,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setule.ll b/test/CodeGen/Mips/setule.ll index 792f2ae..a6d6bf0 100644 --- a/test/CodeGen/Mips/setule.ll +++ b/test/CodeGen/Mips/setule.ll @@ -16,7 +16,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp ule i32 %2, %1 diff --git a/test/CodeGen/Mips/setult.ll b/test/CodeGen/Mips/setult.ll index 56d2e8d..00ee437 100644 --- a/test/CodeGen/Mips/setult.ll +++ b/test/CodeGen/Mips/setult.ll @@ -16,6 +16,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setultk.ll b/test/CodeGen/Mips/setultk.ll index 75b270e..eb9edba 100644 --- a/test/CodeGen/Mips/setultk.ll +++ b/test/CodeGen/Mips/setultk.ll @@ -14,7 +14,7 @@ entry: %cmp = icmp ult i32 %0, 10 %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 -; 16: sltiu $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $t8 +; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst +; 16: move ${{[0-9]+}}, $24 ret void } |