diff options
| author | Michael Liao <michael.liao@intel.com> | 2012-08-14 21:24:47 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2012-08-14 21:24:47 +0000 |
| commit | 7091b2451d46ae7e85188d1c5d7a43d775346ee0 (patch) | |
| tree | 7add0bc3c28d704c45893f61e9760e4406152ef9 /test | |
| parent | fc1a161d76f5cc0204bed3bce3e27cf36ac76d22 (diff) | |
| download | external_llvm-7091b2451d46ae7e85188d1c5d7a43d775346ee0.zip external_llvm-7091b2451d46ae7e85188d1c5d7a43d775346ee0.tar.gz external_llvm-7091b2451d46ae7e85188d1c5d7a43d775346ee0.tar.bz2 | |
fix PR11334
- FP_EXTEND only support extending from vectors with matching elements.
This results in the scalarization of extending to v2f64 from v2f32,
which will be legalized to v4f32 not matching with v2f64.
- add X86-specific VFPEXT supproting extending from v4f32 to v2f64.
- add BUILD_VECTOR lowering helper to recover back the original
extending from v4f32 to v2f64.
- test case is enhanced to include different vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/pr11334.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/test/CodeGen/X86/pr11334.ll b/test/CodeGen/X86/pr11334.ll new file mode 100644 index 0000000..5b7b5ea --- /dev/null +++ b/test/CodeGen/X86/pr11334.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=core-avx-i | FileCheck %s --check-prefix=AVX + +define <2 x double> @v2f2d_ext_vec(<2 x float> %v1) nounwind { +entry: +; CHECK: v2f2d_ext_vec +; CHECK: cvtps2pd +; AVX: v2f2d_ext_vec +; AVX: vcvtps2pd + %f1 = fpext <2 x float> %v1 to <2 x double> + ret <2 x double> %f1 +} + +define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind { +entry: +; CHECK: v3f2d_ext_vec +; CHECK: cvtps2pd +; CHECK: movhlps +; CHECK: cvtps2pd +; AVX: v3f2d_ext_vec +; AVX: vcvtps2pd +; AVX: ret + %f1 = fpext <3 x float> %v1 to <3 x double> + ret <3 x double> %f1 +} + +define <4 x double> @v4f2d_ext_vec(<4 x float> %v1) nounwind { +entry: +; CHECK: v4f2d_ext_vec +; CHECK: cvtps2pd +; CHECK: movhlps +; CHECK: cvtps2pd +; AVX: v4f2d_ext_vec +; AVX: vcvtps2pd +; AVX: ret + %f1 = fpext <4 x float> %v1 to <4 x double> + ret <4 x double> %f1 +} + +define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind { +entry: +; CHECK: v8f2d_ext_vec +; CHECK: cvtps2pd +; CHECK: cvtps2pd +; CHECK: movhlps +; CHECK: cvtps2pd +; CHECK: movhlps +; CHECK: cvtps2pd +; AVX: v8f2d_ext_vec +; AVX: vcvtps2pd +; AVX: vextractf128 +; AVX: vcvtps2pd +; AVX: ret + %f1 = fpext <8 x float> %v1 to <8 x double> + ret <8 x double> %f1 +} |