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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-10-06 13:11:09 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-10-06 13:11:09 +0000 |
| commit | 714319a169784577e33fb1ea28ac06be32c9e735 (patch) | |
| tree | 44e27f9869b10312a7f5d319d450fb743b0fddff /test | |
| parent | 26ba5df2ebc123b1d214a5e7334c650e90d3738a (diff) | |
| download | external_llvm-714319a169784577e33fb1ea28ac06be32c9e735.zip external_llvm-714319a169784577e33fb1ea28ac06be32c9e735.tar.gz external_llvm-714319a169784577e33fb1ea28ac06be32c9e735.tar.bz2 | |
AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/avx512-cvt.ll | 31 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx512-intrinsics.ll | 58 |
2 files changed, 89 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll index 543bb5e..bbad507 100644 --- a/test/CodeGen/X86/avx512-cvt.ll +++ b/test/CodeGen/X86/avx512-cvt.ll @@ -184,3 +184,34 @@ define <16 x float> @uitof32(<16 x i32> %a) nounwind { ret <16 x float> %b } +; CHECK-LABEL: @fptosi02 +; CHECK vcvttss2siz +; CHECK: ret +define i32 @fptosi02(float %a) nounwind { + %b = fptosi float %a to i32 + ret i32 %b +} + +; CHECK-LABEL: @fptoui02 +; CHECK vcvttss2usiz +; CHECK: ret +define i32 @fptoui02(float %a) nounwind { + %b = fptoui float %a to i32 + ret i32 %b +} + +; CHECK-LABEL: @uitofp02 +; CHECK vcvtusi2ss +; CHECK: ret +define float @uitofp02(i32 %a) nounwind { + %b = uitofp i32 %a to float + ret float %b +} + +; CHECK-LABEL: @uitofp03 +; CHECK vcvtusi2sd +; CHECK: ret +define double @uitofp03(i32 %a) nounwind { + %b = uitofp i32 %a to double + ret double %b +} diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll index c0ac719..dc2ab85 100644 --- a/test/CodeGen/X86/avx512-intrinsics.ll +++ b/test/CodeGen/X86/avx512-intrinsics.ll @@ -86,3 +86,61 @@ define <2 x double> @test_x86_avx3_sqrt_sd(<2 x double> %a0, <2 x double> %a1) { } declare <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double>, <2 x double>) nounwind readnone +define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) { + ; CHECK: vcvtsd2siz + %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1] + ret i64 %res +} +declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone + +define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) { + ; CHECK: vcvtsi2sdqz + %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1] + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone + +define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) { + ; CHECK: vcvtusi2sdqz + %res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1] + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone + +define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) { + ; CHECK: vcvttsd2siz + %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1] + ret i64 %res +} +declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone + + +define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) { + ; CHECK: vcvtss2siz + %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1] + ret i64 %res +} +declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone + + +define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) { + ; CHECK: vcvtsi2ssqz + %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1] + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone + + +define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) { + ; CHECK: vcvttss2siz + %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1] + ret i64 %res +} +declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone + +define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) { + ; CHECK: vcvtsd2usiz + %res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1] + ret i64 %res +} +declare i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double>) nounwind readnone |