diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-10-23 19:19:04 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-10-23 19:19:04 +0000 |
| commit | 7377cff9e7641c75678fd5c80472942fd7ef869a (patch) | |
| tree | 8ff95078dc08a96effbc21e3cb59dc2630005b96 /test | |
| parent | 531f025361555e7a695eb559ec02645c054ee146 (diff) | |
| download | external_llvm-7377cff9e7641c75678fd5c80472942fd7ef869a.zip external_llvm-7377cff9e7641c75678fd5c80472942fd7ef869a.tar.gz external_llvm-7377cff9e7641c75678fd5c80472942fd7ef869a.tar.bz2 | |
X86: Custom lower zext v16i8 to v16i16.
On sandy bridge (PR17654) we now get
vpxor %xmm1, %xmm1, %xmm1
vpunpckhbw %xmm1, %xmm0, %xmm2
vpunpcklbw %xmm1, %xmm0, %xmm0
vinsertf128 $1, %xmm2, %ymm0, %ymm0
On haswell it's a simple
vpmovzxbw %xmm0, %ymm0
There is a maze of duplicated and dead transforms and patterns in this
area. Remove the dead custom lowering of zext v8i16 to v8i32, that's
already handled by LowerAVXExtend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193262 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/avx-zext.ll | 12 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx2-conversions.ll | 9 |
2 files changed, 21 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx-zext.ll b/test/CodeGen/X86/avx-zext.ll index e2b6c55..7511746 100644 --- a/test/CodeGen/X86/avx-zext.ll +++ b/test/CodeGen/X86/avx-zext.ll @@ -27,3 +27,15 @@ define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) { %t = zext <8 x i8> %z to <8 x i32> ret <8 x i32> %t } + +; PR17654 +define <16 x i16> @zext_16i8_to_16i16(<16 x i8> %z) { +; CHECK-LABEL: zext_16i8_to_16i16: +; CHECK: vpxor +; CHECK: vpunpckhbw +; CHECK: vpunpcklbw +; CHECK: vinsertf128 +; CHECK: ret + %t = zext <16 x i8> %z to <16 x i16> + ret <16 x i16> %t +} diff --git a/test/CodeGen/X86/avx2-conversions.ll b/test/CodeGen/X86/avx2-conversions.ll index 3ce08dc..0143f18 100644 --- a/test/CodeGen/X86/avx2-conversions.ll +++ b/test/CodeGen/X86/avx2-conversions.ll @@ -63,6 +63,15 @@ define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind { ret <8 x i32>%B } +; CHECK-LABEL: zext_16i8_16i16: +; CHECK: vpmovzxbw +; CHECK-NOT: vinsert +; CHECK: ret +define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) { + %t = zext <16 x i8> %z to <16 x i16> + ret <16 x i16> %t +} + ; CHECK: load_sext_test1 ; CHECK: vpmovsxdq (%r{{[^,]*}}), %ymm{{.*}} ; CHECK: ret |