Remove TargetInstrInfo::copyRegToReg entirely.

Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 3 insertions, 4 deletions

diff --git a/test/CodeGen/Blackfin/cmp64.ll b/test/CodeGen/Blackfin/cmp64.ll
index ef5bf45..6c4f9c5 100644
--- a/test/CodeGen/Blackfin/cmp64.ll
+++ b/test/CodeGen/Blackfin/cmp64.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=bfin
 
 ; This test tries to use a JustCC register as a data operand for MOVEcc.  It
-; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to
-; D.  The proper solution would be to restrict the virtual register to D only.
+; copies (JustCC -> DP), failing because JustCC can only be copied to D.
+; The proper solution would be to restrict the virtual register to D only.
 
 define i32 @main() {
 entry:
diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td
index 2871eb8..146ef6f 100644
--- a/test/TableGen/TargetInstrInfo.td
+++ b/test/TableGen/TargetInstrInfo.td
@@ -83,8 +83,7 @@ class Inst<dag opnds, string asmstr, bits<8> opcode,
 //     the pattern.
 //  6. Address expressions should become first-class entities.
 
-// Simple copy instruction.  isMoveInstr could easily be inferred from this,
-// as could TargetRegisterInfo::copyRegToReg.
+// Simple copy instruction.
 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
                   "mov $dst, $src", 0x88, MRMDestReg,
                   [(set R8:$dst, R8:$src)]>;