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| author | Shih-wei Liao <sliao@google.com> | 2010-04-28 01:47:00 -0700 |
|---|---|---|
| committer | Shih-wei Liao <sliao@google.com> | 2010-04-28 01:47:00 -0700 |
| commit | 7abe37e4aee38cc79d91dd069a37d7e91d5bef53 (patch) | |
| tree | c13b26fc3d8909240f981988535c0b82dd9bf37c /test | |
| parent | 6037a7c3c97b651dd70e48ebe5453134713971ed (diff) | |
| download | external_llvm-7abe37e4aee38cc79d91dd069a37d7e91d5bef53.zip external_llvm-7abe37e4aee38cc79d91dd069a37d7e91d5bef53.tar.gz external_llvm-7abe37e4aee38cc79d91dd069a37d7e91d5bef53.tar.bz2 | |
Sync upstream to r102410.
Re-turn on sdk.
Change-Id: I91a890863989a67243b4d2dfd1ae09b843ebaeaf
Diffstat (limited to 'test')
452 files changed, 11814 insertions, 2397 deletions
diff --git a/test/Analysis/BasicAA/cas.ll b/test/Analysis/BasicAA/cas.ll index 4ce7811..8dd3695 100644 --- a/test/Analysis/BasicAA/cas.ll +++ b/test/Analysis/BasicAA/cas.ll @@ -12,4 +12,4 @@ define i32 @main() { ret i32 %d } -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
\ No newline at end of file +declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind diff --git a/test/Analysis/BasicAA/empty.ll b/test/Analysis/BasicAA/empty.ll new file mode 100644 index 0000000..689efec --- /dev/null +++ b/test/Analysis/BasicAA/empty.ll @@ -0,0 +1,10 @@ +; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output \ +; RUN: |& grep {NoAlias: \{\}\\* \[%\]p, \{\}\\* \[%\]q} + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @foo({}* %p, {}* %q) { + store {} {}, {}* %p + store {} {}, {}* %q + ret void +} diff --git a/test/Analysis/BasicAA/modref.ll b/test/Analysis/BasicAA/modref.ll index 4a61636..a2aabf1 100644 --- a/test/Analysis/BasicAA/modref.ll +++ b/test/Analysis/BasicAA/modref.ll @@ -103,7 +103,7 @@ define i32 @test4(i8* %P) { ret i32 %sub ; CHECK: @test4 ; CHECK: load i32* @G -; CHECK: memset.i32 +; CHECK: memset.p0i8.i32 ; CHECK-NOT: load ; CHECK: sub i32 %tmp, %tmp } @@ -118,7 +118,7 @@ define i32 @test5(i8* %P, i32 %Len) { ret i32 %sub ; CHECK: @test5 ; CHECK: load i32* @G -; CHECK: memcpy.i32 +; CHECK: memcpy.p0i8.p0i8.i32 ; CHECK-NOT: load ; CHECK: sub i32 %tmp, %tmp } diff --git a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll index 6e34209..784d6c7 100644 --- a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll +++ b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -print-callgraph -disable-output |& \ -; RUN: grep {Calls function 'callee'} | count 2 +; RUN: grep {calls function 'callee'} | count 2 define internal void @callee(...) { entry: diff --git a/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll b/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll index 12849b7..0c5ef92 100644 --- a/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll +++ b/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll @@ -1,5 +1,4 @@ -; RUN: opt < %s -print-callgraph -disable-output |& \ -; RUN: grep {Calls function} +; RUN: opt < %s -print-callgraph -disable-output |& grep {calls function} @a = global void ()* @f ; <void ()**> [#uses=0] diff --git a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll index 06637b5..335bbaf 100644 --- a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll +++ b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll @@ -1,6 +1,5 @@ ; RUN: opt < %s -analyze -scalar-evolution |& \ ; RUN: grep {Loop %bb: backedge-taken count is (7 + (-1 \\* %argc))} -; XFAIL: * define i32 @main(i32 %argc, i8** %argv) nounwind { entry: diff --git a/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll b/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll index 102acc6..fa9f21a 100644 --- a/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll +++ b/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll @@ -1,6 +1,9 @@ ; RUN: opt < %s -analyze -scalar-evolution |& grep {/u 3} ; XFAIL: * +; This is a tricky testcase for unsigned wrap detection which ScalarEvolution +; doesn't yet know how to do. + define i32 @f(i32 %x) nounwind readnone { entry: %0 = icmp ugt i32 %x, 999 ; <i1> [#uses=1] diff --git a/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll b/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll index 226221b..25a0434 100644 --- a/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll +++ b/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -analyze -scalar-evolution | grep {backedge-taken count is 255} -; XFAIL: * define i32 @foo(i32 %x, i32 %y, i32* %lam, i32* %alp) nounwind { bb1.thread: diff --git a/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll b/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll index 33a7479..12254e3 100644 --- a/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll +++ b/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll @@ -1,5 +1,7 @@ -; RUN: opt < %s -analyze -scalar-evolution | grep {0 smax} -; XFAIL: * +; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s + +; CHECK: @f +; CHECK: Loop %bb16.preheader: backedge-taken count is (-1 + %c.idx.val) define i32 @f(i32 %c.idx.val) { diff --git a/test/Analysis/ScalarEvolution/sle.ll b/test/Analysis/ScalarEvolution/sle.ll new file mode 100644 index 0000000..f38f6b6 --- /dev/null +++ b/test/Analysis/ScalarEvolution/sle.ll @@ -0,0 +1,27 @@ +; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s + +; ScalarEvolution should be able to use nsw information to prove that +; this loop has a finite trip count. + +; CHECK: @le +; CHECK: Loop %for.body: backedge-taken count is %n +; CHECK: Loop %for.body: max backedge-taken count is 9223372036854775807 + +define void @le(i64 %n, double* nocapture %p) nounwind { +entry: + %cmp6 = icmp slt i64 %n, 0 ; <i1> [#uses=1] + br i1 %cmp6, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] ; <i64> [#uses=2] + %arrayidx = getelementptr double* %p, i64 %i ; <double*> [#uses=2] + %t4 = load double* %arrayidx ; <double> [#uses=1] + %mul = fmul double %t4, 2.200000e+00 ; <double> [#uses=1] + store double %mul, double* %arrayidx + %i.next = add nsw i64 %i, 1 ; <i64> [#uses=2] + %cmp = icmp sgt i64 %i.next, %n ; <i1> [#uses=1] + br i1 %cmp, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/Analysis/ScalarEvolution/undefined.ll b/test/Analysis/ScalarEvolution/undefined.ll new file mode 100644 index 0000000..b1f4446 --- /dev/null +++ b/test/Analysis/ScalarEvolution/undefined.ll @@ -0,0 +1,39 @@ +; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s + +; ScalarEvolution shouldn't attempt to interpret expressions which have +; undefined results. + +define void @foo(i64 %x) { + + %a = udiv i64 %x, 0 +; CHECK: --> (%x /u 0) + + %B = shl i64 %x, 64 +; CHECK: --> %B + + %b = ashr i64 %B, 64 +; CHECK: --> %b + + %c = lshr i64 %x, 64 +; CHECK: --> %c + + %d = shl i64 %x, 64 +; CHECK: --> %d + + %E = shl i64 %x, -1 +; CHECK: --> %E + + %e = ashr i64 %E, -1 +; CHECK: --> %e + + %f = lshr i64 %x, -1 +; CHECK: --> %f + + %g = shl i64 %x, -1 +; CHECK: --> %g + + %h = bitcast i64 undef to i64 +; CHECK: --> undef + + ret void +} diff --git a/test/Analysis/ScalarEvolution/unreachable-code.ll b/test/Analysis/ScalarEvolution/unreachable-code.ll new file mode 100644 index 0000000..51d9398 --- /dev/null +++ b/test/Analysis/ScalarEvolution/unreachable-code.ll @@ -0,0 +1,13 @@ +; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s + +; CHECK: %t = add i64 %t, 1 +; CHECK: --> %t + +define void @foo() { +entry: + ret void + +dead: + %t = add i64 %t, 1 + ret void +} diff --git a/test/Analysis/ScalarEvolution/unsimplified-loop.ll b/test/Analysis/ScalarEvolution/unsimplified-loop.ll new file mode 100644 index 0000000..a317507 --- /dev/null +++ b/test/Analysis/ScalarEvolution/unsimplified-loop.ll @@ -0,0 +1,29 @@ +; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s + +; This loop has no preheader, multiple backedges, etc., but ScalarEvolution +; should still be able to analyze it. + +; CHECK: %i = phi i64 [ 5, %entry ], [ 5, %alt ], [ %i.next, %loop.a ], [ %i.next, %loop.b ] +; CHECK-NEXT: --> {5,+,1}<%loop> + +define void @foo(i1 %p, i1 %q, i1 %s, i1 %u) { +entry: + br i1 %p, label %loop, label %alt + +alt: + br i1 %s, label %loop, label %exit + +loop: + %i = phi i64 [ 5, %entry ], [ 5, %alt ], [ %i.next, %loop.a ], [ %i.next, %loop.b ] + %i.next = add i64 %i, 1 + br i1 %q, label %loop.a, label %loop.b + +loop.a: + br label %loop + +loop.b: + br i1 %u, label %loop, label %exit + +exit: + ret void +} diff --git a/test/Assembler/metadata.ll b/test/Assembler/metadata.ll index a52de87..50f27b4 100644 --- a/test/Assembler/metadata.ll +++ b/test/Assembler/metadata.ll @@ -19,4 +19,4 @@ declare void @llvm.dbg.func.start(metadata) nounwind readnone !foo = !{ !0 } !bar = !{ !1 } -; !foo = !{ !0, !"foo" }
\ No newline at end of file +; !foo = !{ !0, !"foo" } diff --git a/test/Bitcode/memcpy.ll b/test/Bitcode/memcpy.ll index 85b95fe..299eb1e 100644 --- a/test/Bitcode/memcpy.ll +++ b/test/Bitcode/memcpy.ll @@ -8,6 +8,7 @@ entry: tail call void @llvm.memcpy.i64( i8* %tmp.1, i8* %tmp.3, i64 100000, i32 1 ) tail call void @llvm.memset.i32( i8* %tmp.3, i8 14, i32 10000, i32 0 ) tail call void @llvm.memmove.i32( i8* %tmp.1, i8* %tmp.3, i32 123124, i32 1 ) + tail call void @llvm.memmove.i64( i8* %tmp.1, i8* %tmp.3, i64 123124, i32 1 ) ret void } @@ -19,3 +20,4 @@ declare void @llvm.memset.i32(i8*, i8, i32, i32) declare void @llvm.memmove.i32(i8*, i8*, i32, i32) +declare void @llvm.memmove.i64(i8*, i8*, i64, i32) diff --git a/test/Bitcode/sse41_pmulld.ll b/test/Bitcode/sse41_pmulld.ll new file mode 100644 index 0000000..6872cc0 --- /dev/null +++ b/test/Bitcode/sse41_pmulld.ll @@ -0,0 +1,2 @@ +; RUN: llvm-dis < %s.bc | not grep {i32 @llvm\\.pmulld} +; RUN: llvm-dis < %s.bc | grep mul diff --git a/test/Bitcode/sse41_pmulld.ll.bc b/test/Bitcode/sse41_pmulld.ll.bc Binary files differnew file mode 100644 index 0000000..bd66f0a --- /dev/null +++ b/test/Bitcode/sse41_pmulld.ll.bc diff --git a/test/Bitcode/ssse3_palignr.ll b/test/Bitcode/ssse3_palignr.ll new file mode 100644 index 0000000..d596dd5 --- /dev/null +++ b/test/Bitcode/ssse3_palignr.ll @@ -0,0 +1 @@ +; RUN: llvm-dis < %s.bc | not grep {@llvm\\.palign} diff --git a/test/Bitcode/ssse3_palignr.ll.bc b/test/Bitcode/ssse3_palignr.ll.bc Binary files differnew file mode 100644 index 0000000..642f4de --- /dev/null +++ b/test/Bitcode/ssse3_palignr.ll.bc diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 5ad48ef..ab060c9 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -7,6 +7,21 @@ set(TARGETS_TO_BUILD ${TARGETS_BUILT}) set(LLVM_LIBS_DIR "${LLVM_BINARY_DIR}/lib/${CMAKE_CFG_INTDIR}") set(SHLIBEXT "${LTDL_SHLIB_EXT}") +if(BUILD_SHARED_LIBS) + set(LLVM_SHARED_LIBS_ENABLED "1") +else() + set(LLVM_SHARED_LIBS_ENABLED "0") +endif(BUILD_SHARED_LIBS) + +if(${CMAKE_SYSTEM_NAME} MATCHES "Darwin") + set(SHLIBPATH_VAR "DYLD_LIBRARY_PATH") +else() # Default for all other unix like systems. + # CMake hardcodes the library locaction using rpath. + # Therefore LD_LIBRARY_PATH is not required to run binaries in the + # build dir. We pass it anyways. + set(SHLIBPATH_VAR "LD_LIBRARY_PATH") +endif() + include(FindPythonInterp) if(PYTHONINTERP_FOUND) configure_file( @@ -27,6 +42,8 @@ if(PYTHONINTERP_FOUND) -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}#" -e "s#\@LLVMGCCDIR\@##" -e "s#\@LLVM_BUILD_MODE\@#${CMAKE_CFG_INTDIR}#" + -e "s#\@ENABLE_SHARED\@#${LLVM_SHARED_LIBS_ENABLED}#" + -e "s#\@SHLIBPATH_VAR\@#${SHLIBPATH_VAR}#" ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in > ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg COMMAND ${PYTHON_EXECUTABLE} diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index b6cf880..c0ad65f 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -86,7 +86,7 @@ bb: ; preds = %entry return: ; preds = %bb ret void } -;CHECK: L_LSDA_1: +;CHECK: L_LSDA_0: declare arm_apcscc void @_ZdlPv(i8*) nounwind diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index a4e7685..f17d059 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -4,8 +4,8 @@ define arm_aapcscc void @g() { entry: -;CHECK: [sp, #+8] -;CHECK: [sp, #+12] +;CHECK: [sp, #8] +;CHECK: [sp, #12] ;CHECK: [sp] tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll index 90a5bd2..87d1a8b 100644 --- a/test/CodeGen/ARM/2009-10-30.ll +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -6,7 +6,7 @@ define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) { entry: ;CHECK: sub sp, sp, #4 ;CHECK: add r{{[0-9]+}}, sp, #8 -;CHECK: str r{{[0-9]+}}, [sp], #+4 +;CHECK: str r{{[0-9]+}}, [sp], #4 ;CHECK: bx lr %ap = alloca i8*, align 4 %ap1 = bitcast i8** %ap to i8* diff --git a/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll new file mode 100644 index 0000000..31525ef --- /dev/null +++ b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s +; RUN: llc < %s -mtriple=armv5-unknown-eabi | FileCheck %s +; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s + +define i32 @bar(i32 %a) nounwind { +entry: + %0 = tail call i32 @foo(i32 %a) nounwind ; <i32> [#uses=1] + %1 = add nsw i32 %0, 3 ; <i32> [#uses=1] +; CHECK: ldmia sp!, {r11, pc} + ret i32 %1 +} + +declare i32 @foo(i32) diff --git a/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..8a24cfa --- /dev/null +++ b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=arm -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll new file mode 100644 index 0000000..71e0b0a --- /dev/null +++ b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=arm -mattr=+neon < %s +; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. + +define arm_apcscc void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +entry: + %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] + %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] + %1 = fsub <4 x float> %0, undef ; <<4 x float>> [#uses=1] + %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=1] + %3 = shufflevector <4 x float> undef, <4 x float> %2, <4 x i32> <i32 2, i32 3, i32 6, i32 7> ; <<4 x float>> [#uses=1] + %4 = fmul <4 x float> %3, <float 0.000000e+00, float 0x3FED906BC0000000, float 0x3FE6A09E60000000, float 0xBFD87DE2A0000000> ; <<4 x float>> [#uses=1] + %5 = fadd <4 x float> undef, %4 ; <<4 x float>> [#uses=1] + %6 = fadd <4 x float> undef, %5 ; <<4 x float>> [#uses=1] + %7 = fadd <4 x float> undef, %6 ; <<4 x float>> [#uses=1] + br i1 undef, label %bb4, label %bb3 + +bb3: ; preds = %entry + %8 = shufflevector <4 x float> undef, <4 x float> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=0] + ret void + +bb4: ; preds = %entry + ret void +} diff --git a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll new file mode 100644 index 0000000..4f71b83 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 +; Radar 7855014 + +define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { +entry: + unreachable +} diff --git a/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/test/CodeGen/ARM/2010-04-14-SplitVector.ll new file mode 100644 index 0000000..42f9852 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=arm -mcpu=arm1136jf-s +; Radar 7854640 + +define arm_apcscc void @test() nounwind { +bb: + br i1 undef, label %bb9, label %bb10 + +bb9: + %tmp63 = bitcast <4 x float> zeroinitializer to i128 + %tmp64 = trunc i128 %tmp63 to i32 + br label %bb10 + +bb10: + %0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ] + ret void +} diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll new file mode 100644 index 0000000..ed7bca8 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s +; PR6847 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv4t-apple-darwin10" + +define hidden arm_apcscc i32 @__addvsi3(i32 %a, i32 %b) nounwind { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) + %0 = add nsw i32 %b, %a, !dbg !9 ; <i32> [#uses=1] + ret i32 %0, !dbg !11 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"b", metadata !2, i32 93, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"__addvsi3", metadata !"__addvsi3", metadata !"__addvsi3", metadata !2, i32 94, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !6, metadata !6} +!6 = metadata !{i32 524310, metadata !2, metadata !"SItype", metadata !7, i32 152, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 524329, metadata !"libgcc2.h", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ] +!8 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 95, i32 0, metadata !10, null} +!10 = metadata !{i32 524299, metadata !1, i32 94, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 100, i32 0, metadata !10, null} diff --git a/test/CodeGen/ARM/arguments7.ll b/test/CodeGen/ARM/arguments7.ll index 038e417..fa97ee8 100644 --- a/test/CodeGen/ARM/arguments7.ll +++ b/test/CodeGen/ARM/arguments7.ll @@ -6,4 +6,4 @@ define double @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, double %b) { ret double %tmp } -declare double @g(double) +declare double @g(i32, i32, i32, i32, double) diff --git a/test/CodeGen/ARM/arguments8.ll b/test/CodeGen/ARM/arguments8.ll index 6999a4d..abe059b 100644 --- a/test/CodeGen/ARM/arguments8.ll +++ b/test/CodeGen/ARM/arguments8.ll @@ -6,4 +6,4 @@ define i64 @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i64 %b) { ret i64 %tmp } -declare i64 @g(i64) +declare i64 @g(i32, i32, i32, i32, i64) diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll index 52ab871..fb0f8ff 100644 --- a/test/CodeGen/ARM/arm-negative-stride.ll +++ b/test/CodeGen/ARM/arm-negative-stride.ll @@ -5,7 +5,7 @@ define void @test(i32* %P, i32 %A, i32 %i) nounwind { entry: -; CHECK: str r1, [{{r.*}}, +{{r.*}}, lsl #2] +; CHECK: str r1, [{{r.*}}, {{r.*}}, lsl #2] icmp eq i32 %i, 0 ; <i1>:0 [#uses=1] br i1 %0, label %return, label %bb diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll new file mode 100644 index 0000000..fcca191 --- /dev/null +++ b/test/CodeGen/ARM/bfx.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s + +define i32 @sbfx1(i32 %a) { +; CHECK: sbfx1 +; CHECK: sbfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = sext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx1(i32 %a) { +; CHECK: ubfx1 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = zext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx2(i32 %a) { +; CHECK: ubfx2 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = and i32 %t1, 2047 + ret i32 %t2 +} + diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index e5b5791..f03282b 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index db18a86..749690e 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index a5c86bf..0c31495 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index 904a587..f8b47b5 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index 7b9e029..7a70543 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index d3c9c82..ef4e3e5 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index d6c22f1..c15005e 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll index 724947e..1d1d06a 100644 --- a/test/CodeGen/ARM/fnmacs.ll +++ b/test/CodeGen/ARM/fnmacs.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEONFP define float @test(float %acc, float %a, float %b) { entry: diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index ad21882..6b7cefa 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll new file mode 100644 index 0000000..c5583b9 --- /dev/null +++ b/test/CodeGen/ARM/fp16.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s | FileCheck %s +; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK-FP16 %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv7-eabi" + +@x = global i16 12902 +@y = global i16 0 +@z = common global i16 0 + +define arm_aapcs_vfpcc void @foo() nounwind { +; CHECK: foo: +; CHECK-FP6: foo: +entry: + %0 = load i16* @x, align 2 + %1 = load i16* @y, align 2 + %2 = tail call float @llvm.convert.from.fp16(i16 %0) +; CHECK: __gnu_h2f_ieee +; CHECK-FP16: vcvtb.f16.f32 + %3 = tail call float @llvm.convert.from.fp16(i16 %1) +; CHECK: __gnu_h2f_ieee +; CHECK-FP16: vcvtb.f16.f32 + %4 = fadd float %2, %3 + %5 = tail call i16 @llvm.convert.to.fp16(float %4) +; CHECK: __gnu_f2h_ieee +; CHECK-FP16: vcvtb.f32.f16 + store i16 %5, i16* @x, align 2 + ret void +} + +declare float @llvm.convert.from.fp16(i16) nounwind readnone + +declare i16 @llvm.convert.to.fp16(float) nounwind readnone diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 2adac78..1ef9f7f 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2 diff --git a/test/CodeGen/ARM/fsubs.ll b/test/CodeGen/ARM/fsubs.ll index ae98be3..bea8d5f 100644 --- a/test/CodeGen/ARM/fsubs.ll +++ b/test/CodeGen/ARM/fsubs.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { entry: diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index 886c0d5..ccb1428 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -11,23 +11,23 @@ define i32 @test1() { } ; DarwinStatic: _test1: -; DarwinStatic: ldr r0, LCPI1_0 +; DarwinStatic: ldr r0, LCPI0_0 ; DarwinStatic: ldr r0, [r0] ; DarwinStatic: bx lr ; DarwinStatic: .align 2 -; DarwinStatic: LCPI1_0: +; DarwinStatic: LCPI0_0: ; DarwinStatic: .long {{_G$}} ; DarwinDynamic: _test1: -; DarwinDynamic: ldr r0, LCPI1_0 +; DarwinDynamic: ldr r0, LCPI0_0 ; DarwinDynamic: ldr r0, [r0] ; DarwinDynamic: ldr r0, [r0] ; DarwinDynamic: bx lr ; DarwinDynamic: .align 2 -; DarwinDynamic: LCPI1_0: +; DarwinDynamic: LCPI0_0: ; DarwinDynamic: .long L_G$non_lazy_ptr ; DarwinDynamic: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers @@ -39,15 +39,15 @@ define i32 @test1() { ; DarwinPIC: _test1: -; DarwinPIC: ldr r0, LCPI1_0 -; DarwinPIC: LPC1_0: -; DarwinPIC: ldr r0, [pc, +r0] +; DarwinPIC: ldr r0, LCPI0_0 +; DarwinPIC: LPC0_0: +; DarwinPIC: ldr r0, [pc, r0] ; DarwinPIC: ldr r0, [r0] ; DarwinPIC: bx lr ; DarwinPIC: .align 2 -; DarwinPIC: LCPI1_0: -; DarwinPIC: .long L_G$non_lazy_ptr-(LPC1_0+8) +; DarwinPIC: LCPI0_0: +; DarwinPIC: .long L_G$non_lazy_ptr-(LPC0_0+8) ; DarwinPIC: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers ; DarwinPIC: .align 2 @@ -58,18 +58,18 @@ define i32 @test1() { ; LinuxPIC: test1: -; LinuxPIC: ldr r0, .LCPI1_0 -; LinuxPIC: ldr r1, .LCPI1_1 +; LinuxPIC: ldr r0, .LCPI0_0 +; LinuxPIC: ldr r1, .LCPI0_1 -; LinuxPIC: .LPC1_0: +; LinuxPIC: .LPC0_0: ; LinuxPIC: add r0, pc, r0 -; LinuxPIC: ldr r0, [r1, +r0] +; LinuxPIC: ldr r0, [r1, r0] ; LinuxPIC: ldr r0, [r0] ; LinuxPIC: bx lr ; LinuxPIC: .align 2 -; LinuxPIC: .LCPI1_0: -; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC1_0+8) +; LinuxPIC: .LCPI0_0: +; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC0_0+8) ; LinuxPIC: .align 2 -; LinuxPIC: .LCPI1_1: +; LinuxPIC: .LCPI0_1: ; LinuxPIC: .long G(GOT) diff --git a/test/CodeGen/ARM/hidden-vis-3.ll b/test/CodeGen/ARM/hidden-vis-3.ll index 3bd710a..fc8b2fe 100644 --- a/test/CodeGen/ARM/hidden-vis-3.ll +++ b/test/CodeGen/ARM/hidden-vis-3.ll @@ -5,9 +5,9 @@ define i32 @t() nounwind readonly { entry: -; CHECK: LCPI1_0: +; CHECK: LCPI0_0: ; CHECK-NEXT: .long _x -; CHECK: LCPI1_1: +; CHECK: LCPI0_1: ; CHECK-NEXT: .long _y %0 = load i32* @x, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 623f2cb..8677ce5 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -11,7 +11,7 @@ entry: define void @t1(i32 %a, i32 %b) { ; CHECK: t1: -; CHECK: ldmfdlt sp!, {r7, pc} +; CHECK: ldmialt sp!, {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index d7fcf7d..342208b 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ ; RUN: grep cmpne | count 1 ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmfdhi | count 1 +; RUN: grep ldmiahi | count 1 define void @foo(i32 %X, i32 %Y) { entry: diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll index c60ad93..eb97085 100644 --- a/test/CodeGen/ARM/ifcvt7.ll +++ b/test/CodeGen/ARM/ifcvt7.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ ; RUN: grep moveq | count 1 ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmfdeq | count 1 +; RUN: grep ldmiaeq | count 1 ; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1. %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll index a7da834..1e39060 100644 --- a/test/CodeGen/ARM/ifcvt8.ll +++ b/test/CodeGen/ARM/ifcvt8.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmfdne | count 1 +; RUN: grep ldmiane | count 1 %struct.SString = type { i8*, i32, i32 } diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index 5135d03..f898060 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -15,14 +15,14 @@ entry: ; indirect branch gets duplicated here ; ARM: bx ; THUMB: mov pc, r1 -; THUMB2: mov pc, r1 +; THUMB2: mov pc, r2 br i1 %1, label %bb3, label %bb2 bb2: ; preds = %entry, %bb3 %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1] ; ARM: bx ; THUMB: mov pc, r1 -; THUMB2: mov pc, r1 +; THUMB2: mov pc, r2 indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] bb3: ; preds = %entry @@ -59,6 +59,6 @@ L1: ; preds = %L2, %bb2 store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 } -; ARM: .long L_BA4__foo_L5-(LPC{{.*}}+8) -; THUMB: .long L_BA4__foo_L5-(LPC{{.*}}+4) -; THUMB2: .long L_BA4__foo_L5 +; ARM: .long Ltmp0-(LPC{{.*}}+8) +; THUMB: .long Ltmp0-(LPC{{.*}}+4) +; THUMB2: .long Ltmp0 diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 1a016a0..9a2dc82 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -24,7 +24,7 @@ define i32 @t2() { define i32 @t3() { ; CHECK: t3: ; CHECK: ldmib -; CHECK: ldmfd sp! +; CHECK: ldmia sp! %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index c366e2d..895562a 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -10,10 +10,10 @@ entry: ;V6: ldrd r2, [r2] ;V5: ldr r3, [r2] -;V5: ldr r2, [r2, #+4] +;V5: ldr r2, [r2, #4] ;EABI: ldr r3, [r2] -;EABI: ldr r2, [r2, #+4] +;EABI: ldr r2, [r2, #4] %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll index 6f1d87d..d29693e 100644 --- a/test/CodeGen/ARM/sbfx.ll +++ b/test/CodeGen/ARM/sbfx.ll @@ -12,7 +12,7 @@ entry: define i32 @f2(i32 %a) { entry: ; CHECK: f2: -; CHECK: ubfx r0, r0, #0, #20 +; CHECK: bfc r0, #20, #12 %tmp = shl i32 %a, 12 %tmp2 = lshr i32 %tmp, 12 ret i32 %tmp2 diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index f8d3df2..553cd64 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!} -; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4} +; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #4} @b = external global i64* diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll index d932f90..57370c4 100644 --- a/test/CodeGen/ARM/tls2.ll +++ b/test/CodeGen/ARM/tls2.ll @@ -7,7 +7,7 @@ define i32 @f() { ; CHECK-NONPIC: f: -; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}] ; CHECK-NONPIC: i(gottpoff) ; CHECK-PIC: f: ; CHECK-PIC: __tls_get_addr @@ -18,7 +18,7 @@ entry: define i32* @g() { ; CHECK-NONPIC: g: -; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}] ; CHECK-NONPIC: i(gottpoff) ; CHECK-PIC: g: ; CHECK-PIC: __tls_get_addr diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index f5383aa..c61ea8c 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -10,28 +10,32 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { define <4 x i16> @vld1i16(i16* %A) nounwind { ;CHECK: vld1i16: ;CHECK: vld1.16 - %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0) ret <4 x i16> %tmp1 } define <2 x i32> @vld1i32(i32* %A) nounwind { ;CHECK: vld1i32: ;CHECK: vld1.32 - %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0) ret <2 x i32> %tmp1 } define <2 x float> @vld1f(float* %A) nounwind { ;CHECK: vld1f: ;CHECK: vld1.32 - %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0) ret <2 x float> %tmp1 } define <1 x i64> @vld1i64(i64* %A) nounwind { ;CHECK: vld1i64: ;CHECK: vld1.64 - %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0) ret <1 x i64> %tmp1 } @@ -45,28 +49,32 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;CHECK: vld1Qi16: ;CHECK: vld1.16 - %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0) ret <8 x i16> %tmp1 } define <4 x i32> @vld1Qi32(i32* %A) nounwind { ;CHECK: vld1Qi32: ;CHECK: vld1.32 - %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0) ret <4 x i32> %tmp1 } define <4 x float> @vld1Qf(float* %A) nounwind { ;CHECK: vld1Qf: ;CHECK: vld1.32 - %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0) ret <4 x float> %tmp1 } define <2 x i64> @vld1Qi64(i64* %A) nounwind { ;CHECK: vld1Qi64: ;CHECK: vld1.64 - %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0) ret <2 x i64> %tmp1 } diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 23f7d2c..f5dc06c 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -24,7 +24,8 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { define <4 x i16> @vld2i16(i16* %A) nounwind { ;CHECK: vld2i16: ;CHECK: vld2.16 - %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,7 +35,8 @@ define <4 x i16> @vld2i16(i16* %A) nounwind { define <2 x i32> @vld2i32(i32* %A) nounwind { ;CHECK: vld2i32: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -44,7 +46,8 @@ define <2 x i32> @vld2i32(i32* %A) nounwind { define <2 x float> @vld2f(float* %A) nounwind { ;CHECK: vld2f: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1 %tmp4 = add <2 x float> %tmp2, %tmp3 @@ -54,7 +57,8 @@ define <2 x float> @vld2f(float* %A) nounwind { define <1 x i64> @vld2i64(i64* %A) nounwind { ;CHECK: vld2i64: ;CHECK: vld1.64 - %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -74,7 +78,8 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { define <8 x i16> @vld2Qi16(i16* %A) nounwind { ;CHECK: vld2Qi16: ;CHECK: vld2.16 - %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -84,7 +89,8 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { define <4 x i32> @vld2Qi32(i32* %A) nounwind { ;CHECK: vld2Qi32: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -94,7 +100,8 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind { define <4 x float> @vld2Qf(float* %A) nounwind { ;CHECK: vld2Qf: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1 %tmp4 = add <4 x float> %tmp2, %tmp3 diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index 207dc6a..33c4d37 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -24,7 +24,8 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { define <4 x i16> @vld3i16(i16* %A) nounwind { ;CHECK: vld3i16: ;CHECK: vld3.16 - %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,7 +35,8 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { define <2 x i32> @vld3i32(i32* %A) nounwind { ;CHECK: vld3i32: ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -44,7 +46,8 @@ define <2 x i32> @vld3i32(i32* %A) nounwind { define <2 x float> @vld3f(float* %A) nounwind { ;CHECK: vld3f: ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 2 %tmp4 = add <2 x float> %tmp2, %tmp3 @@ -54,7 +57,8 @@ define <2 x float> @vld3f(float* %A) nounwind { define <1 x i64> @vld3i64(i64* %A) nounwind { ;CHECK: vld3i64: ;CHECK: vld1.64 - %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -76,7 +80,8 @@ define <8 x i16> @vld3Qi16(i16* %A) nounwind { ;CHECK: vld3Qi16: ;CHECK: vld3.16 ;CHECK: vld3.16 - %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -87,7 +92,8 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ;CHECK: vld3Qi32: ;CHECK: vld3.32 ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -98,7 +104,8 @@ define <4 x float> @vld3Qf(float* %A) nounwind { ;CHECK: vld3Qf: ;CHECK: vld3.32 ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2 %tmp4 = add <4 x float> %tmp2, %tmp3 diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index 0624f29..e800cb5 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -24,7 +24,8 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { define <4 x i16> @vld4i16(i16* %A) nounwind { ;CHECK: vld4i16: ;CHECK: vld4.16 - %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,7 +35,8 @@ define <4 x i16> @vld4i16(i16* %A) nounwind { define <2 x i32> @vld4i32(i32* %A) nounwind { ;CHECK: vld4i32: ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -44,7 +46,8 @@ define <2 x i32> @vld4i32(i32* %A) nounwind { define <2 x float> @vld4f(float* %A) nounwind { ;CHECK: vld4f: ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2 %tmp4 = add <2 x float> %tmp2, %tmp3 @@ -54,7 +57,8 @@ define <2 x float> @vld4f(float* %A) nounwind { define <1 x i64> @vld4i64(i64* %A) nounwind { ;CHECK: vld4i64: ;CHECK: vld1.64 - %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -76,7 +80,8 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ;CHECK: vld4Qi16: ;CHECK: vld4.16 ;CHECK: vld4.16 - %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -87,7 +92,8 @@ define <4 x i32> @vld4Qi32(i32* %A) nounwind { ;CHECK: vld4Qi32: ;CHECK: vld4.32 ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -98,7 +104,8 @@ define <4 x float> @vld4Qf(float* %A) nounwind { ;CHECK: vld4Qf: ;CHECK: vld4.32 ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2 %tmp4 = add <4 x float> %tmp2, %tmp3 diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 53881a3..46a2002 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -23,8 +23,9 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld2lanei16: ;CHECK: vld2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1 %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -34,8 +35,9 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld2lanei32: ;CHECK: vld2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 %tmp5 = add <2 x i32> %tmp3, %tmp4 @@ -45,8 +47,9 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld2lanef: ;CHECK: vld2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1 %tmp5 = add <2 x float> %tmp3, %tmp4 @@ -56,8 +59,9 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld2laneQi16: ;CHECK: vld2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -67,8 +71,9 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld2laneQi32: ;CHECK: vld2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) + %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -78,8 +83,9 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld2laneQf: ;CHECK: vld2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1 %tmp5 = add <4 x float> %tmp3, %tmp4 @@ -120,8 +126,9 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld3lanei16: ;CHECK: vld3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2 @@ -133,8 +140,9 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld3lanei32: ;CHECK: vld3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2 @@ -146,8 +154,9 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld3lanef: ;CHECK: vld3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2 @@ -159,8 +168,9 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld3laneQi16: ;CHECK: vld3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 @@ -172,8 +182,9 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld3laneQi32: ;CHECK: vld3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3) + %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3) %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2 @@ -185,8 +196,9 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld3laneQf: ;CHECK: vld3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2 @@ -231,8 +243,9 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld4lanei16: ;CHECK: vld4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2 @@ -246,8 +259,9 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld4lanei32: ;CHECK: vld4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2 @@ -261,8 +275,9 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld4lanef: ;CHECK: vld4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2 @@ -276,8 +291,9 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld4laneQi16: ;CHECK: vld4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2 @@ -291,8 +307,9 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld4laneQi32: ;CHECK: vld4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2 @@ -306,8 +323,9 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld4laneQf: ;CHECK: vld4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2 diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index 602b124..95414c3 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -11,32 +11,36 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst1i16: ;CHECK: vst1.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst1.v4i16(i16* %A, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1) ret void } define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst1i32: ;CHECK: vst1.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst1.v2i32(i32* %A, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1) ret void } define void @vst1f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst1f: ;CHECK: vst1.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst1.v2f32(float* %A, <2 x float> %tmp1) + call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1) ret void } define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst1.v1i64(i64* %A, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1) ret void } @@ -51,32 +55,36 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst1Qi16: ;CHECK: vst1.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst1.v8i16(i16* %A, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1) ret void } define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst1Qi32: ;CHECK: vst1.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst1.v4i32(i32* %A, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1) ret void } define void @vst1Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst1Qf: ;CHECK: vst1.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst1.v4f32(float* %A, <4 x float> %tmp1) + call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1) ret void } define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { ;CHECK: vst1Qi64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <2 x i64>* %B - call void @llvm.arm.neon.vst1.v2i64(i64* %A, <2 x i64> %tmp1) + call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index 17d6bee..3c98a2c 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -11,32 +11,36 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2i16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst2.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1) ret void } define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2i32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst2.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst2.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1) ret void } define void @vst2f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst2f: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst2.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1) + call void @llvm.arm.neon.vst2.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1) ret void } define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst2i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst2.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1) ret void } @@ -51,24 +55,27 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2Qi16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst2.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1) ret void } define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2Qi32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst2.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1) ret void } define void @vst2Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst2Qf: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst2.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1) + call void @llvm.arm.neon.vst2.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index a831a0c..2599bc0 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -11,32 +11,36 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3i16: ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst3.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) ret void } define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst3i32: ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst3.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) ret void } define void @vst3f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3f: ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst3.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) + call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) ret void } define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst3i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst3.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) ret void } @@ -53,8 +57,9 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3Qi16: ;CHECK: vst3.16 ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst3.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) ret void } @@ -62,8 +67,9 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3Qi32: ;CHECK: vst3.32 ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst3.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst3.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) ret void } @@ -71,8 +77,9 @@ define void @vst3Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3Qf: ;CHECK: vst3.32 ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst3.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) + call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index d92c017..878f0ef 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -11,32 +11,36 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4i16: ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst4.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) ret void } define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4i32: ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst4.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) ret void } define void @vst4f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst4f: ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst4.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) + call void @llvm.arm.neon.vst4.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) ret void } define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst4i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst4.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) ret void } @@ -53,8 +57,9 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4Qi16: ;CHECK: vst4.16 ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst4.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) ret void } @@ -62,8 +67,9 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4Qi32: ;CHECK: vst4.32 ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst4.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst4.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) ret void } @@ -71,8 +77,9 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4Qf: ;CHECK: vst4.32 ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst4.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) + call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 3bfb14f..cf50756 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -11,48 +11,54 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2lanei16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2lanei32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst2lanef: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2laneQi16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ret void } define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2laneQi32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) + call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) ret void } define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst2laneQf: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 3) + call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3) ret void } @@ -76,48 +82,54 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3lanei16: ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst3lanei32: ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3lanef: ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3laneQi16: ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6) + call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6) ret void } define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3laneQi32: ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0) + call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0) ret void } define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3laneQf: ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } @@ -142,48 +154,54 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4lanei16: ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4lanei32: ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst4lanef: ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4laneQi16: ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst4lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7) + call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7) ret void } define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4laneQi32: ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst4lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) + call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) ret void } define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4laneQf: ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst4lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } diff --git a/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..cf3f0b9 --- /dev/null +++ b/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=alpha -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Blackfin/jumptable.ll b/test/CodeGen/Blackfin/jumptable.ll index 5f49e9d..263533c 100644 --- a/test/CodeGen/Blackfin/jumptable.ll +++ b/test/CodeGen/Blackfin/jumptable.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=bfin -verify-machineinstrs | FileCheck %s ; CHECK: .section .rodata -; CHECK: JTI1_0: -; CHECK: .long .BB1_1 +; CHECK: JTI0_0: +; CHECK: .long .BB0_1 define i32 @oper(i32 %op, i32 %A, i32 %B) { entry: diff --git a/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..45d53c8 --- /dev/null +++ b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=cellspu -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/CellSPU/bigstack.ll b/test/CodeGen/CellSPU/bigstack.ll new file mode 100644 index 0000000..5483f46 --- /dev/null +++ b/test/CodeGen/CellSPU/bigstack.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=cellspu -o %t1.s +; RUN: grep lqx %t1.s | count 4 +; RUN: grep il %t1.s | grep -v file | count 7 +; RUN: grep stqx %t1.s | count 2 + +define i32 @bigstack() nounwind { +entry: + %avar = alloca i32 + %big_data = alloca [2048 x i32] + store i32 3840, i32* %avar, align 4 + br label %return + +return: + %retval = load i32* %avar + ret i32 %retval +} + diff --git a/test/CodeGen/CellSPU/bss.ll b/test/CodeGen/CellSPU/bss.ll index 05a0f50..327800d 100644 --- a/test/CodeGen/CellSPU/bss.ll +++ b/test/CodeGen/CellSPU/bss.ll @@ -1,5 +1,11 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep "\.section" %t1.s | grep "\.bss" | count 1 +; RUN: llc < %s -march=cellspu | FileCheck %s @bssVar = global i32 zeroinitializer +; CHECK: .section .bss +; CHECK-NEXT: .globl + +@localVar= internal global i32 zeroinitializer +; CHECK-NOT: .lcomm +; CHECK: .local +; CHECK-NEXT: .comm diff --git a/test/CodeGen/CellSPU/crash.ll b/test/CodeGen/CellSPU/crash.ll new file mode 100644 index 0000000..cc2ab71 --- /dev/null +++ b/test/CodeGen/CellSPU/crash.ll @@ -0,0 +1,8 @@ +; RUN: llc %s -march=cellspu -o - +declare i8 @return_i8() +declare i16 @return_i16() +define void @testfunc() { + %rv1 = call i8 @return_i8() + %rv2 = call i16 @return_i16() + ret void +}
\ No newline at end of file diff --git a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll index a0b1403..9c3c804 100644 --- a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll +++ b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll @@ -1,9 +1,6 @@ ; RUN: llc < %s -O0 ; PR 1323 -; ModuleID = 'test.bc' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "i686-apple-darwin8" %struct.comp = type { i8*, i32, i8*, [3 x i8], i32 } define void @regbranch() { diff --git a/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll b/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll index e220be6..3090857 100644 --- a/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll +++ b/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -o - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i686-pc-linux-gnu" %struct.RETURN = type { i32, i32 } %struct.ada__finalization__controlled = type { %struct.system__finalization_root__root_controlled } %struct.ada__streams__root_stream_type = type { %struct.ada__tags__dispatch_table* } diff --git a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll index bd26481..4cc1e7c 100644 --- a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll +++ b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -enable-eh -target triple = "i686-pc-linux-gnu" - define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() { entry: invoke void asm "rdtsc\0A\09movl %eax, $0\0A\09movl %edx, $1", "=*imr,=*imr,~{dirflag},~{fpsr},~{flags},~{dx},~{ax}"( i32* null, i32* null ) diff --git a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll index fc9164f..d2e97a4 100644 --- a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll +++ b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll @@ -1,8 +1,6 @@ ; RUN: llc < %s -enable-eh ; PR1833 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i686-pc-linux-gnu" %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } %struct.__type_info_pseudo = type { i8*, i8* } @_ZTI2e1 = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=1] diff --git a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll index 4f95dfe..00ca8c7 100644 --- a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll +++ b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s ; PR2603 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i386-pc-linux-gnu" %struct.A = type { i8 } %struct.B = type { i8, [1 x i8] } @Foo = constant %struct.A { i8 ptrtoint (i8* getelementptr ([1 x i8]* inttoptr (i32 17 to [1 x i8]*), i32 0, i32 -16) to i8) } ; <%struct.A*> [#uses=0] diff --git a/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll b/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll index a51c75d..22bd4d7 100644 --- a/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll +++ b/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s ; PR5495 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" -target triple = "i386-pc-linux-gnu" %"struct.std::__ctype_abstract_base<wchar_t>" = type { %"struct.std::locale::facet" } %"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::__ctype_abstract_base<wchar_t>"*, %"struct.std::__ctype_abstract_base<wchar_t>"* } diff --git a/test/CodeGen/Generic/2010-ZeroSizedArg.ll b/test/CodeGen/Generic/2010-ZeroSizedArg.ll new file mode 100644 index 0000000..ba40bd0 --- /dev/null +++ b/test/CodeGen/Generic/2010-ZeroSizedArg.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s +; PR4975 + +%0 = type <{ [0 x i32] }> +%union.T0 = type { } + +@.str = private constant [1 x i8] c" " + +define arm_apcscc void @t(%0) nounwind { +entry: + %arg0 = alloca %union.T0 + %1 = bitcast %union.T0* %arg0 to %0* + store %0 %0, %0* %1, align 1 + ret void +} + +declare arm_apcscc i32 @printf(i8*, ...) diff --git a/test/CodeGen/Generic/GC/redundant_init.ll b/test/CodeGen/Generic/GC/redundant_init.ll deleted file mode 100644 index 10c70e7..0000000 --- a/test/CodeGen/Generic/GC/redundant_init.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -march=x86 | \ -; RUN: ignore grep {movl..0} | count 0 - -%struct.obj = type { i8*, %struct.obj* } - -declare void @g() gc "shadow-stack" - -define void @f(i8* %o) gc "shadow-stack" { -entry: - %root = alloca i8* - call void @llvm.gcroot(i8** %root, i8* null) - store i8* %o, i8** %root - call void @g() - ret void -} - -declare void @llvm.gcroot(i8**, i8*) diff --git a/test/CodeGen/Generic/addr-label.ll b/test/CodeGen/Generic/addr-label.ll new file mode 100644 index 0000000..0dbe502 --- /dev/null +++ b/test/CodeGen/Generic/addr-label.ll @@ -0,0 +1,81 @@ +; RUN: llc %s -o - + +;; Reference to a label that gets deleted. +define i8* @test1() nounwind { +entry: + ret i8* blockaddress(@test1b, %test_label) +} + +define i32 @test1b() nounwind { +entry: + ret i32 -1 +test_label: + br label %ret +ret: + ret i32 -1 +} + + +;; Issues with referring to a label that gets RAUW'd later. +define i32 @test2a() nounwind { +entry: + %target = bitcast i8* blockaddress(@test2b, %test_label) to i8* + + call i32 @test2b(i8* %target) + + ret i32 0 +} + +define i32 @test2b(i8* %target) nounwind { +entry: + indirectbr i8* %target, [label %test_label] + +test_label: +; assume some code here... + br label %ret + +ret: + ret i32 -1 +} + +; Issues with a BB that gets RAUW'd to another one after references are +; generated. +define void @test3(i8** %P, i8** %Q) nounwind { +entry: + store i8* blockaddress(@test3b, %test_label), i8** %P + store i8* blockaddress(@test3b, %ret), i8** %Q + ret void +} + +define i32 @test3b() nounwind { +entry: + br label %test_label +test_label: + br label %ret +ret: + ret i32 -1 +} + + +; PR6673 + +define i64 @test4a() { + %target = bitcast i8* blockaddress(@test4b, %usermain) to i8* + %ret = call i64 @test4b(i8* %target) + + ret i64 %ret +} + +define i64 @test4b(i8* %Code) { +entry: + indirectbr i8* %Code, [label %usermain] +usermain: + br label %label_line_0 + +label_line_0: + br label %label_line_1 + +label_line_1: + %target = ptrtoint i8* blockaddress(@test4b, %label_line_0) to i64 + ret i64 %target +} diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll new file mode 100644 index 0000000..7218565 --- /dev/null +++ b/test/CodeGen/Generic/crash.ll @@ -0,0 +1,8 @@ +; RUN: llc %s -o - + +; PR6332 +%struct.AVCodecTag = type opaque +@ff_codec_bmp_tags = external global [0 x %struct.AVCodecTag] +@tags = global [1 x %struct.AVCodecTag*] [%struct.AVCodecTag* getelementptr +inbounds ([0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)] + diff --git a/test/CodeGen/Generic/dbg_value.ll b/test/CodeGen/Generic/dbg_value.ll new file mode 100644 index 0000000..ce3364d --- /dev/null +++ b/test/CodeGen/Generic/dbg_value.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s +; rdar://7759395 + +%0 = type { i32, i32 } + +define void @t(%0*, i32, i32, i32, i32) nounwind { + tail call void @llvm.dbg.value(metadata !{%0* %0}, i64 0, metadata !0) + unreachable +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!0 = metadata !{i32 0} ; diff --git a/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..854352a --- /dev/null +++ b/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=mblaze -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/MSP430/2009-05-17-Rot.ll b/test/CodeGen/MSP430/2009-05-17-Rot.ll index 2ae0052..d622aa7 100644 --- a/test/CodeGen/MSP430/2009-05-17-Rot.ll +++ b/test/CodeGen/MSP430/2009-05-17-Rot.ll @@ -14,4 +14,4 @@ define i16 @rol1u16(i16 %x.arg) nounwind { return: %6 = load i16* %retval ret i16 %6 -}
\ No newline at end of file +} diff --git a/test/CodeGen/MSP430/2009-05-17-Shift.ll b/test/CodeGen/MSP430/2009-05-17-Shift.ll index 25aff60..e23df78 100644 --- a/test/CodeGen/MSP430/2009-05-17-Shift.ll +++ b/test/CodeGen/MSP430/2009-05-17-Shift.ll @@ -12,4 +12,4 @@ return: %3 = load i16* %retval ret i16 %3 -}
\ No newline at end of file +} diff --git a/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..8de044c --- /dev/null +++ b/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=msp430 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll index 636b318..b8d6826 100644 --- a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll +++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll @@ -4,7 +4,7 @@ target triple = "mips-unknown-linux" define float @h() nounwind readnone { entry: -; CHECK: lw $2, %got($CPI1_0)($gp) -; CHECK: lwc1 $f0, %lo($CPI1_0)($2) +; CHECK: lw $2, %got($CPI0_0)($gp) +; CHECK: lwc1 $f0, %lo($CPI0_0)($2) ret float 0x400B333340000000 } diff --git a/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..4161c1d --- /dev/null +++ b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=mips -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll index b508026..5b5e11f 100644 --- a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll +++ b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s +; XFAIL: vg_leak target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32" target triple = "pic16-" diff --git a/test/CodeGen/PIC16/C16-15.ll b/test/CodeGen/PIC16/C16-15.ll index 5ca2d4a..020b0dd 100644 --- a/test/CodeGen/PIC16/C16-15.ll +++ b/test/CodeGen/PIC16/C16-15.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | grep "extern" | grep "@.lib.unordered.f32" | count 3 +; XFAIL: vg_leak @pc = global i8* inttoptr (i64 160 to i8*), align 1 ; <i8**> [#uses=2] @aa = common global i16 0, align 1 ; <i16*> [#uses=0] diff --git a/test/CodeGen/PIC16/global-in-user-section.ll b/test/CodeGen/PIC16/global-in-user-section.ll index 74c9d9d..6cdb648 100644 --- a/test/CodeGen/PIC16/global-in-user-section.ll +++ b/test/CodeGen/PIC16/global-in-user-section.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s +; XFAIL: vg_leak @G1 = common global i16 0, section "usersection", align 1 ; CHECK: usersection UDATA diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll index 432c291..3ee2e25 100644 --- a/test/CodeGen/PIC16/globals.ll +++ b/test/CodeGen/PIC16/globals.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s +; XFAIL: vg_leak @G1 = global i32 4712, section "Address=412" ; CHECK: @G1.412..user_section.# IDATA 412 diff --git a/test/CodeGen/PIC16/sext.ll b/test/CodeGen/PIC16/sext.ll index b49925f..e51a542 100644 --- a/test/CodeGen/PIC16/sext.ll +++ b/test/CodeGen/PIC16/sext.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 +; XFAIL: vg_leak @main.auto.c = internal global i8 0 ; <i8*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll index a05245d..db2ab87 100644 --- a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 | grep .byte +; RUN: llc < %s -march=ppc32 | grep nop target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll index 20683b9..8322a843 100644 --- a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll +++ b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll @@ -35,3 +35,10 @@ declare ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128) nounwind readonly declare ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128) nounwind readonly declare ppc_fp128 @llvm.pow.ppcf128(ppc_fp128, ppc_fp128) nounwind readonly + +declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) + +define ppc_fp128 @cs(ppc_fp128 %from, ppc_fp128 %to) { + %tmp = call ppc_fp128 @copysignl(ppc_fp128 %from, ppc_fp128 %to) + ret ppc_fp128 %tmp +} diff --git a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll index 32ddb34..1ba11d3 100644 --- a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll +++ b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll @@ -8,4 +8,13 @@ ; CHECK: .globl __cmd ; CHECK-NEXT: .align 3 ; CHECK-NEXT: __cmd: -; CHECK-NEXT: .space 1 +; CHECK-NEXT: .byte 0 + +; PR6340 + +%Ty = type { i32, {}, i32 } +@k = global %Ty { i32 1, {} zeroinitializer, i32 3 } + +; CHECK: _k: +; CHECK-NEXT: .long 1 +; CHECK-NEXT: .long 3 diff --git a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll new file mode 100644 index 0000000..d094509 --- /dev/null +++ b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=ppc32 -mcpu=g5 -mtriple=powerpc-apple-darwin10.0 | FileCheck %s +; ModuleID = 'nn.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin11.0" +; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of +; the function being called; the mtctr is not required to use it). + +@p = external global void (...)* ; <void (...)**> [#uses=1] + +define void @foo() nounwind ssp { +entry: +; CHECK: mtctr r12 + %0 = load void (...)** @p, align 4 ; <void (...)*> [#uses=1] + call void (...)* %0() nounwind + br label %return + +return: ; preds = %entry + ret void +} diff --git a/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll b/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll new file mode 100644 index 0000000..8fd0550 --- /dev/null +++ b/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin10.0 +; rdar://7819990 + +%0 = type { i32 } +%1 = type { i64 } +%struct.Buffer = type { [1024 x i8], i64, i64, i64 } +%struct.InStream = type { %struct.Buffer, %0, %1, i32*, %struct.InStreamMethods* } +%struct.InStreamMethods = type { void (%struct.InStream*, i8*, i32)*, void (%struct.InStream*, i64)*, i64 (%struct.InStream*)*, void (%struct.InStream*)* } + +define i64 @t(%struct.InStream* %is) nounwind optsize ssp { +entry: + br i1 undef, label %is_read_byte.exit, label %bb.i + +bb.i: ; preds = %entry + br label %is_read_byte.exit + +is_read_byte.exit: ; preds = %bb.i, %entry + br i1 undef, label %is_read_byte.exit22, label %bb.i21 + +bb.i21: ; preds = %is_read_byte.exit + unreachable + +is_read_byte.exit22: ; preds = %is_read_byte.exit + br i1 undef, label %is_read_byte.exit19, label %bb.i18 + +bb.i18: ; preds = %is_read_byte.exit22 + br label %is_read_byte.exit19 + +is_read_byte.exit19: ; preds = %bb.i18, %is_read_byte.exit22 + br i1 undef, label %is_read_byte.exit16, label %bb.i15 + +bb.i15: ; preds = %is_read_byte.exit19 + unreachable + +is_read_byte.exit16: ; preds = %is_read_byte.exit19 + %0 = shl i64 undef, 32 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit13, label %bb.i12 + +bb.i12: ; preds = %is_read_byte.exit16 + unreachable + +is_read_byte.exit13: ; preds = %is_read_byte.exit16 + %1 = shl i64 undef, 24 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit10, label %bb.i9 + +bb.i9: ; preds = %is_read_byte.exit13 + unreachable + +is_read_byte.exit10: ; preds = %is_read_byte.exit13 + %2 = shl i64 undef, 16 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit7, label %bb.i6 + +bb.i6: ; preds = %is_read_byte.exit10 + br label %is_read_byte.exit7 + +is_read_byte.exit7: ; preds = %bb.i6, %is_read_byte.exit10 + %3 = shl i64 undef, 8 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit4, label %bb.i3 + +bb.i3: ; preds = %is_read_byte.exit7 + unreachable + +is_read_byte.exit4: ; preds = %is_read_byte.exit7 + %4 = or i64 0, %0 ; <i64> [#uses=1] + %5 = or i64 %4, %1 ; <i64> [#uses=1] + %6 = or i64 %5, %2 ; <i64> [#uses=1] + %7 = or i64 %6, %3 ; <i64> [#uses=1] + %8 = or i64 %7, 0 ; <i64> [#uses=1] + ret i64 %8 +} diff --git a/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..f48f32f --- /dev/null +++ b/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=ppc32 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll index 558fd1b..f99089b 100644 --- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll +++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll @@ -9,66 +9,66 @@ ; RUN: llc < %s -march=ppc32 | \ ; RUN: grep nand | count 1 -define i32 @EQV1(i32 %X, i32 %Y) { +define i32 @EQV1(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, %Y ; <i32> [#uses=1] %B = xor i32 %A, -1 ; <i32> [#uses=1] ret i32 %B } -define i32 @EQV2(i32 %X, i32 %Y) { +define i32 @EQV2(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = xor i32 %A, %Y ; <i32> [#uses=1] ret i32 %B } -define i32 @EQV3(i32 %X, i32 %Y) { +define i32 @EQV3(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = xor i32 %Y, %A ; <i32> [#uses=1] ret i32 %B } -define i32 @ANDC1(i32 %X, i32 %Y) { +define i32 @ANDC1(i32 %X, i32 %Y) nounwind { %A = xor i32 %Y, -1 ; <i32> [#uses=1] %B = and i32 %X, %A ; <i32> [#uses=1] ret i32 %B } -define i32 @ANDC2(i32 %X, i32 %Y) { +define i32 @ANDC2(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = and i32 %A, %Y ; <i32> [#uses=1] ret i32 %B } -define i32 @ORC1(i32 %X, i32 %Y) { +define i32 @ORC1(i32 %X, i32 %Y) nounwind { %A = xor i32 %Y, -1 ; <i32> [#uses=1] %B = or i32 %X, %A ; <i32> [#uses=1] ret i32 %B } -define i32 @ORC2(i32 %X, i32 %Y) { +define i32 @ORC2(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = or i32 %A, %Y ; <i32> [#uses=1] ret i32 %B } -define i32 @NOR1(i32 %X) { +define i32 @NOR1(i32 %X) nounwind { %Y = xor i32 %X, -1 ; <i32> [#uses=1] ret i32 %Y } -define i32 @NOR2(i32 %X, i32 %Y) { +define i32 @NOR2(i32 %X, i32 %Y) nounwind { %Z = or i32 %X, %Y ; <i32> [#uses=1] %R = xor i32 %Z, -1 ; <i32> [#uses=1] ret i32 %R } -define i32 @NAND1(i32 %X, i32 %Y) { +define i32 @NAND1(i32 %X, i32 %Y) nounwind { %Z = and i32 %X, %Y ; <i32> [#uses=1] %W = xor i32 %Z, -1 ; <i32> [#uses=1] ret i32 %W } -define void @VNOR(<4 x float>* %P, <4 x float>* %Q) { +define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind { %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1] %tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1] @@ -80,7 +80,7 @@ define void @VNOR(<4 x float>* %P, <4 x float>* %Q) { ret void } -define void @VANDC(<4 x float>* %P, <4 x float>* %Q) { +define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind { %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1] %tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index 2094e10..ab8d9dc 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -43,13 +43,13 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; PIC: addis r5, r4, ha16(L_BA4__foo_L5-"L1$pb") -; PIC: li r6, lo16(L_BA4__foo_L5-"L1$pb") -; PIC: add r5, r5, r6 -; PIC: stw r5 -; STATIC: li r4, lo16(L_BA4__foo_L5) -; STATIC: addis r4, r4, ha16(L_BA4__foo_L5) -; STATIC: stw r4 +; PIC: addis r4, r4, ha16(Ltmp0-"L0$pb") +; PIC: li r6, lo16(Ltmp0-"L0$pb") +; PIC: add r4, r4, r6 +; PIC: stw r4 +; STATIC: li r5, lo16(Ltmp0) +; STATIC: addis r5, r5, ha16(Ltmp0) +; STATIC: stw r5 store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 } diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll index e49dcb8..2ebfd3c 100644 --- a/test/CodeGen/PowerPC/ppc-prologue.ll +++ b/test/CodeGen/PowerPC/ppc-prologue.ll @@ -5,9 +5,9 @@ define i32 @_Z4funci(i32 %a) ssp { ; CHECK-NEXT: stw r31, -4(r1) ; CHECK-NEXT: stw r0, 8(r1) ; CHECK-NEXT: stwu r1, -80(r1) -; CHECK-NEXT: Llabel1: +; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: mr r31, r1 -; CHECK-NEXT: Llabel2: +; CHECK-NEXT: Ltmp1: entry: %a_addr = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll index 7bce01c..3dc8061 100644 --- a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll +++ b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll @@ -25,4 +25,4 @@ entry: return: ret void ; CHECK: blr -}
\ No newline at end of file +} diff --git a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll index 8a1288a..6f10346 100644 --- a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll +++ b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s +; RN: llc < %s +; RUN: false +; XFAIL: * ; PR4534 ; ModuleID = 'tango.net.ftp.FtpClient.bc' diff --git a/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..f66ee21 --- /dev/null +++ b/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=sparc -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/SystemZ/00-RetVoid.ll b/test/CodeGen/SystemZ/00-RetVoid.ll index de23795..6f3cbac 100644 --- a/test/CodeGen/SystemZ/00-RetVoid.ll +++ b/test/CodeGen/SystemZ/00-RetVoid.ll @@ -3,4 +3,4 @@ define void @foo() { entry: ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/01-RetArg.ll b/test/CodeGen/SystemZ/01-RetArg.ll index 9ab2097..8e1ff49 100644 --- a/test/CodeGen/SystemZ/01-RetArg.ll +++ b/test/CodeGen/SystemZ/01-RetArg.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: ret i64 %b -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetAdd.ll b/test/CodeGen/SystemZ/02-RetAdd.ll index 9ff9b6a..d5dfa22 100644 --- a/test/CodeGen/SystemZ/02-RetAdd.ll +++ b/test/CodeGen/SystemZ/02-RetAdd.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = add i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetAddImm.ll b/test/CodeGen/SystemZ/02-RetAddImm.ll index 6d73e4d..40f6cce 100644 --- a/test/CodeGen/SystemZ/02-RetAddImm.ll +++ b/test/CodeGen/SystemZ/02-RetAddImm.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = add i64 %a, 1 ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetAnd.ll b/test/CodeGen/SystemZ/02-RetAnd.ll index 1492f9d..b568a57 100644 --- a/test/CodeGen/SystemZ/02-RetAnd.ll +++ b/test/CodeGen/SystemZ/02-RetAnd.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = and i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetNeg.ll b/test/CodeGen/SystemZ/02-RetNeg.ll index 7f3380d..3f6ba2f 100644 --- a/test/CodeGen/SystemZ/02-RetNeg.ll +++ b/test/CodeGen/SystemZ/02-RetNeg.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a) { entry: %c = sub i64 0, %a ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetOr.ll b/test/CodeGen/SystemZ/02-RetOr.ll index 1e8134d..a1ddb63 100644 --- a/test/CodeGen/SystemZ/02-RetOr.ll +++ b/test/CodeGen/SystemZ/02-RetOr.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = or i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetSub.ll b/test/CodeGen/SystemZ/02-RetSub.ll index 1c4514f..98e1861 100644 --- a/test/CodeGen/SystemZ/02-RetSub.ll +++ b/test/CodeGen/SystemZ/02-RetSub.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = sub i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetSubImm.ll b/test/CodeGen/SystemZ/02-RetSubImm.ll index 4f91cb0..8479fbf 100644 --- a/test/CodeGen/SystemZ/02-RetSubImm.ll +++ b/test/CodeGen/SystemZ/02-RetSubImm.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = sub i64 %a, 1 ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetXor.ll b/test/CodeGen/SystemZ/02-RetXor.ll index a9439bf..4d1adf2 100644 --- a/test/CodeGen/SystemZ/02-RetXor.ll +++ b/test/CodeGen/SystemZ/02-RetXor.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = xor i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetXorImm.ll b/test/CodeGen/SystemZ/02-RetXorImm.ll index ea4b829..473bbf7 100644 --- a/test/CodeGen/SystemZ/02-RetXorImm.ll +++ b/test/CodeGen/SystemZ/02-RetXorImm.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = xor i64 %a, 1 ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll b/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll index 564d343..5457b12 100644 --- a/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll +++ b/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll @@ -13,4 +13,4 @@ define i32 @bar(float %a) { entry: %b = bitcast float %a to i32 ret i32 %b -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..610aa40 --- /dev/null +++ b/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=systemz -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll index c31b65b..72c9e62 100644 --- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll +++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll @@ -11,7 +11,7 @@ define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { ; CHECK: t: -; CHECK: adds r3, #8 +; CHECK: adds r0, #8 entry: %val = alloca i64, align 4 ; <i64*> [#uses=3] %0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1] diff --git a/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..6b6c14f --- /dev/null +++ b/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=thumb -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Thumb/machine-licm.ll b/test/CodeGen/Thumb/machine-licm.ll index dae1412..a69a64f 100644 --- a/test/CodeGen/Thumb/machine-licm.ll +++ b/test/CodeGen/Thumb/machine-licm.ll @@ -15,12 +15,12 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: ldr.n r2, LCPI1_0 +; CHECK: ldr.n r2, LCPI0_0 ; CHECK: add r2, pc ; CHECK: ldr r{{[0-9]+}}, [r2] -; CHECK: LBB1_2 -; CHECK: LCPI1_0: -; CHECK-NOT: LCPI1_1: +; CHECK: LBB0_2 +; CHECK: LCPI0_0: +; CHECK-NOT: LCPI0_1: ; CHECK: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll index 319d29b..9c1fdb3 100644 --- a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim type { %struct.GAP } ; type %0 type { i16, i8, i8 } ; type %1 diff --git a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll index a62b612..317db64 100644 --- a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll +++ b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim -O3 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -O3 type { i16, i8, i8 } ; type %0 type { [2 x i32], [2 x i32] } ; type %1 diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll index 7647474..2bbc231 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | not grep fcpys ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll index acf562c..8294484 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll index 3ada026..b18c972 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll index 090ed2d..96bcbad 100644 --- a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll +++ b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -arm-use-neon-fp +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } %struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 } diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll index b4b6ed9..bfb7f6e 100644 --- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll +++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll @@ -12,10 +12,10 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it ne -; CHECK-NEXT: ldmfdne.w +; CHECK-NEXT: ldmiane.w ; CHECK-NEXT: itt eq ; CHECK-NEXT: subeq.w -; CHECK-NEXT: ldmfdeq.w +; CHECK-NEXT: ldmiaeq.w entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] diff --git a/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll new file mode 100644 index 0000000..54f4122 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll @@ -0,0 +1,266 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin + +@.str41196 = external constant [2 x i8], align 4 ; <[2 x i8]*> [#uses=1] + +declare arm_apcscc void @syStopraw(i32) nounwind + +declare arm_apcscc i32 @SyFopen(i8*, i8*) nounwind + +declare arm_apcscc i8* @SyFgets(i8*, i32) nounwind + +define arm_apcscc void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind { +entry: + %line = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1] + %secname = alloca [1024 x i8], align 4 ; <[1024 x i8]*> [#uses=0] + %last = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1] + %last2 = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1] + br i1 undef, label %bb, label %bb2 + +bb: ; preds = %entry + br i1 undef, label %bb2, label %bb3 + +bb2: ; preds = %bb, %entry + br label %bb3 + +bb3: ; preds = %bb2, %bb + %storemerge = phi i32 [ 0, %bb2 ], [ 1, %bb ] ; <i32> [#uses=1] + br i1 undef, label %bb19, label %bb20 + +bb19: ; preds = %bb3 + br label %bb20 + +bb20: ; preds = %bb19, %bb3 + br i1 undef, label %bb25, label %bb26 + +bb25: ; preds = %bb20 + br label %bb26 + +bb26: ; preds = %bb25, %bb20 + %offset.2 = phi i32 [ -2, %bb25 ], [ 0, %bb20 ] ; <i32> [#uses=1] + br i1 undef, label %bb.nph508, label %bb49 + +bb.nph508: ; preds = %bb26 + unreachable + +bb49: ; preds = %bb26 + br i1 undef, label %bb51, label %bb50 + +bb50: ; preds = %bb49 + br i1 undef, label %bb51, label %bb104 + +bb51: ; preds = %bb50, %bb49 + unreachable + +bb104: ; preds = %bb50 + br i1 undef, label %bb106, label %bb105 + +bb105: ; preds = %bb104 + br i1 undef, label %bb106, label %bb161 + +bb106: ; preds = %bb105, %bb104 + unreachable + +bb161: ; preds = %bb105 + br i1 false, label %bb163, label %bb162 + +bb162: ; preds = %bb161 + br i1 undef, label %bb163, label %bb224 + +bb163: ; preds = %bb162, %bb161 + unreachable + +bb224: ; preds = %bb162 + %0 = call arm_apcscc i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2] + br i1 false, label %bb297, label %bb300 + +bb297: ; preds = %bb224 + unreachable + +bb300: ; preds = %bb224 + %1 = icmp eq i32 %offset.2, -1 ; <i1> [#uses=1] + br label %bb440 + +bb307: ; preds = %isdigit1498.exit67 + br label %bb308 + +bb308: ; preds = %bb440, %bb307 + br i1 undef, label %bb309, label %isdigit1498.exit67 + +isdigit1498.exit67: ; preds = %bb308 + br i1 undef, label %bb309, label %bb307 + +bb309: ; preds = %isdigit1498.exit67, %bb308 + br i1 undef, label %bb310, label %bb313 + +bb310: ; preds = %bb309 + br label %bb313 + +bb313: ; preds = %bb310, %bb309 + br i1 false, label %bb318, label %bb317 + +bb317: ; preds = %bb313 + %2 = icmp sgt i8 undef, -1 ; <i1> [#uses=1] + br i1 %2, label %bb.i.i73, label %bb1.i.i74 + +bb.i.i73: ; preds = %bb317 + br i1 false, label %bb318, label %bb329.outer + +bb1.i.i74: ; preds = %bb317 + unreachable + +bb318: ; preds = %bb.i.i73, %bb313 + ret void + +bb329.outer: ; preds = %bb.i.i73 + br i1 undef, label %bb333, label %bb329.us.us + +bb329.us.us: ; preds = %bb329.us.us, %bb329.outer + br i1 undef, label %bb333, label %bb329.us.us + +bb333: ; preds = %bb329.us.us, %bb329.outer + %match.0.lcssa = phi i32 [ undef, %bb329.us.us ], [ 2, %bb329.outer ] ; <i32> [#uses=2] + br i1 undef, label %bb335, label %bb388 + +bb335: ; preds = %bb333 + %3 = and i1 undef, %1 ; <i1> [#uses=1] + br i1 %3, label %bb339, label %bb348 + +bb339: ; preds = %bb335 + br i1 false, label %bb340, label %bb345 + +bb340: ; preds = %bb339 + br i1 undef, label %return, label %bb341 + +bb341: ; preds = %bb340 + ret void + +bb345: ; preds = %bb345, %bb339 + %4 = phi i8 [ %5, %bb345 ], [ undef, %bb339 ] ; <i8> [#uses=0] + %indvar670 = phi i32 [ %tmp673, %bb345 ], [ 0, %bb339 ] ; <i32> [#uses=1] + %tmp673 = add i32 %indvar670, 1 ; <i32> [#uses=2] + %scevgep674 = getelementptr [256 x i8]* %last, i32 0, i32 %tmp673 ; <i8*> [#uses=1] + %5 = load i8* %scevgep674, align 1 ; <i8> [#uses=1] + br i1 undef, label %bb347, label %bb345 + +bb347: ; preds = %bb345 + br label %bb348 + +bb348: ; preds = %bb347, %bb335 + br i1 false, label %bb352, label %bb356 + +bb352: ; preds = %bb348 + unreachable + +bb356: ; preds = %bb348 + br i1 undef, label %bb360, label %bb369 + +bb360: ; preds = %bb356 + br i1 false, label %bb361, label %bb366 + +bb361: ; preds = %bb360 + br i1 undef, label %return, label %bb362 + +bb362: ; preds = %bb361 + ret void + +bb366: ; preds = %bb366, %bb360 + %indvar662 = phi i32 [ %tmp665, %bb366 ], [ 0, %bb360 ] ; <i32> [#uses=1] + %tmp665 = add i32 %indvar662, 1 ; <i32> [#uses=2] + %scevgep666 = getelementptr [256 x i8]* %last2, i32 0, i32 %tmp665 ; <i8*> [#uses=1] + %6 = load i8* %scevgep666, align 1 ; <i8> [#uses=0] + br i1 false, label %bb368, label %bb366 + +bb368: ; preds = %bb366 + br label %bb369 + +bb369: ; preds = %bb368, %bb356 + br i1 undef, label %bb373, label %bb388 + +bb373: ; preds = %bb383, %bb369 + %7 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=1] + %8 = icmp eq i8* %7, null ; <i1> [#uses=1] + br i1 %8, label %bb375, label %bb383 + +bb375: ; preds = %bb373 + %9 = icmp eq i32 %storemerge, 0 ; <i1> [#uses=1] + br i1 %9, label %return, label %bb376 + +bb376: ; preds = %bb375 + ret void + +bb383: ; preds = %bb373 + %10 = load i8* undef, align 1 ; <i8> [#uses=1] + %cond1 = icmp eq i8 %10, 46 ; <i1> [#uses=1] + br i1 %cond1, label %bb373, label %bb388 + +bb388: ; preds = %bb383, %bb369, %bb333 + %match.1140 = phi i32 [ %match.0.lcssa, %bb369 ], [ 0, %bb333 ], [ %match.0.lcssa, %bb383 ] ; <i32> [#uses=1] + br label %bb391 + +bb390: ; preds = %isdigit1498.exit83, %bb392 + %indvar.next725 = add i32 %indvar724, 1 ; <i32> [#uses=1] + br label %bb391 + +bb391: ; preds = %bb390, %bb388 + %indvar724 = phi i32 [ %indvar.next725, %bb390 ], [ 0, %bb388 ] ; <i32> [#uses=2] + %11 = load i8* undef, align 1 ; <i8> [#uses=0] + br i1 false, label %bb395, label %bb392 + +bb392: ; preds = %bb391 + br i1 undef, label %bb390, label %isdigit1498.exit83 + +isdigit1498.exit83: ; preds = %bb392 + br i1 undef, label %bb390, label %bb395 + +bb394: ; preds = %isdigit1498.exit87 + br label %bb395 + +bb395: ; preds = %bb394, %isdigit1498.exit83, %bb391 + %storemerge14.sum = add i32 %indvar724, undef ; <i32> [#uses=1] + %p.26 = getelementptr [256 x i8]* %line, i32 0, i32 %storemerge14.sum ; <i8*> [#uses=1] + br i1 undef, label %bb400, label %isdigit1498.exit87 + +isdigit1498.exit87: ; preds = %bb395 + br i1 false, label %bb400, label %bb394 + +bb400: ; preds = %isdigit1498.exit87, %bb395 + br i1 undef, label %bb402, label %bb403 + +bb402: ; preds = %bb400 + %12 = getelementptr inbounds i8* %p.26, i32 undef ; <i8*> [#uses=1] + br label %bb403 + +bb403: ; preds = %bb402, %bb400 + %p.29 = phi i8* [ %12, %bb402 ], [ undef, %bb400 ] ; <i8*> [#uses=0] + br i1 undef, label %bb405, label %bb404 + +bb404: ; preds = %bb403 + br i1 undef, label %bb405, label %bb407 + +bb405: ; preds = %bb404, %bb403 + br i1 undef, label %return, label %bb406 + +bb406: ; preds = %bb405 + call arm_apcscc void @syStopraw(i32 %fin) nounwind + ret void + +bb407: ; preds = %bb404 + %cond = icmp eq i32 %match.1140, 2 ; <i1> [#uses=1] + br i1 %cond, label %bb408, label %bb428 + +bb408: ; preds = %bb407 + unreachable + +bb428: ; preds = %bb407 + br label %bb440 + +bb440: ; preds = %bb428, %bb300 + %13 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=0] + br i1 false, label %bb442, label %bb308 + +bb442: ; preds = %bb440 + unreachable + +return: ; preds = %bb405, %bb375, %bb361, %bb340 + ret void +} diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll new file mode 100644 index 0000000..71ff68a --- /dev/null +++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -0,0 +1,63 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; Radar 7459078 +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" + +%0 = type { i32, i32 } +%s1 = type { %s3, i32, %s4, i8*, void (i8*, i8*)*, i8*, i32*, i32*, i32*, i32, i64, [1 x i32] } +%s2 = type { i32 (...)**, %s4 } +%s3 = type { %s2, i32, i32, i32*, [4 x i8], float, %s4, i8*, i8* } +%s4 = type { %s5 } +%s5 = type { i32 } + +; Make sure the cmp is not scheduled before the InlineAsm that clobbers cc. +; CHECK: InlineAsm End +; CHECK: cmp +; CHECK: beq +define arm_apcscc void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { +entry: + %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 + volatile store i32 1, i32* %tmp1, align 4 + %tmp12 = getelementptr inbounds %s1* %this, i32 0, i32 1 + store i32 %levels, i32* %tmp12, align 4 + %tmp13 = getelementptr inbounds %s1* %this, i32 0, i32 3 + store i8* %data, i8** %tmp13, align 4 + %tmp14 = getelementptr inbounds %s1* %this, i32 0, i32 4 + store void (i8*, i8*)* %release, void (i8*, i8*)** %tmp14, align 4 + %tmp15 = getelementptr inbounds %s1* %this, i32 0, i32 5 + store i8* %info, i8** %tmp15, align 4 + %tmp16 = getelementptr inbounds %s1* %this, i32 0, i32 6 + store i32* null, i32** %tmp16, align 4 + %tmp17 = getelementptr inbounds %s1* %this, i32 0, i32 7 + store i32* null, i32** %tmp17, align 4 + %tmp19 = getelementptr inbounds %s1* %this, i32 0, i32 10 + store i64 0, i64* %tmp19, align 4 + %tmp20 = getelementptr inbounds %s1* %this, i32 0, i32 0 + tail call arm_apcscc void @f1(%s3* %tmp20, i32* %s) nounwind + %tmp21 = shl i32 %format, 6 + %tmp22 = tail call arm_apcscc zeroext i8 @f2(i32 %format) nounwind + %toBoolnot = icmp eq i8 %tmp22, 0 + %tmp23 = zext i1 %toBoolnot to i32 + %flags.0 = or i32 %tmp23, %tmp21 + %tmp24 = shl i32 %flags.0, 16 + %asmtmp.i.i.i = tail call %0 asm sideeffect "\0A0:\09ldrex $1, [$2]\0A\09orr $1, $1, $3\0A\09strex $0, $1, [$2]\0A\09cmp $0, #0\0A\09bne 0b", "=&r,=&r,r,r,~{memory},~{cc}"(i32* %tmp1, i32 %tmp24) nounwind + %tmp25 = getelementptr inbounds %s1* %this, i32 0, i32 2, i32 0, i32 0 + volatile store i32 1, i32* %tmp25, align 4 + %tmp26 = icmp eq i32 %levels, 0 + br i1 %tmp26, label %return, label %bb4 + +bb4: + %l.09 = phi i32 [ %tmp28, %bb4 ], [ 0, %entry ] + %scevgep = getelementptr %s1* %this, i32 0, i32 11, i32 %l.09 + %scevgep10 = getelementptr i32* %rowbytes, i32 %l.09 + %tmp27 = load i32* %scevgep10, align 4 + store i32 %tmp27, i32* %scevgep, align 4 + %tmp28 = add i32 %l.09, 1 + %exitcond = icmp eq i32 %tmp28, %levels + br i1 %exitcond, label %return, label %bb4 + +return: + ret void +} + +declare arm_apcscc void @f1(%s3*, i32*) +declare arm_apcscc zeroext i8 @f2(i32) diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll new file mode 100644 index 0000000..fea2dca --- /dev/null +++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -O3 | FileCheck %s +; rdar://7493908 + +; Make sure the result of the first dynamic_alloc isn't copied back to sp more +; than once. We'll deal with poor codegen later. + +define arm_apcscc void @t() nounwind ssp { +entry: +; CHECK: t: +; CHECK: mov r0, sp +; CHECK: bfc r0, #0, #3 +; CHECK: subs r0, #16 +; CHECK: mov sp, r0 +; Yes, this is stupid codegen, but it's correct. +; CHECK: mov r0, sp +; CHECK: bfc r0, #0, #3 +; CHECK: subs r0, #16 +; CHECK: mov sp, r0 + %size = mul i32 8, 2 + %vla_a = alloca i8, i32 %size, align 8 + %vla_b = alloca i8, i32 %size, align 8 + unreachable +} diff --git a/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll b/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll new file mode 100644 index 0000000..950b67e --- /dev/null +++ b/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll @@ -0,0 +1,73 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin +; Radar 7896289 + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +define arm_apcscc void @test(i32 %mode) nounwind optsize noinline { +entry: + br i1 undef, label %return, label %bb3 + +bb3: ; preds = %entry + br i1 undef, label %bb15, label %bb18 + +bb15: ; preds = %bb3 + unreachable + +bb18: ; preds = %bb3 + switch i32 %mode, label %return [ + i32 0, label %bb26 + i32 1, label %bb56 + i32 2, label %bb107 + i32 6, label %bb150.preheader + i32 9, label %bb310.preheader + i32 13, label %bb414.preheader + i32 15, label %bb468.preheader + i32 16, label %bb522.preheader + ] + +bb150.preheader: ; preds = %bb18 + br i1 undef, label %bb154, label %bb160 + +bb310.preheader: ; preds = %bb18 + unreachable + +bb414.preheader: ; preds = %bb18 + unreachable + +bb468.preheader: ; preds = %bb18 + unreachable + +bb522.preheader: ; preds = %bb18 + unreachable + +bb26: ; preds = %bb18 + unreachable + +bb56: ; preds = %bb18 + unreachable + +bb107: ; preds = %bb18 + br label %bb110 + +bb110: ; preds = %bb122, %bb107 + %asmtmp.i.i179 = tail call i16 asm "rev16 $0, $1\0A", "=l,l"(i16 undef) nounwind ; <i16> [#uses=1] + %asmtmp.i.i178 = tail call i16 asm "rev16 $0, $1\0A", "=l,l"(i16 %asmtmp.i.i179) nounwind ; <i16> [#uses=1] + store i16 %asmtmp.i.i178, i16* undef, align 2 + br i1 undef, label %bb122, label %bb121 + +bb121: ; preds = %bb110 + br label %bb122 + +bb122: ; preds = %bb121, %bb110 + br label %bb110 + +bb154: ; preds = %bb150.preheader + unreachable + +bb160: ; preds = %bb150.preheader + unreachable + +return: ; preds = %bb18, %entry + ret void +} diff --git a/test/CodeGen/Thumb2/bfx.ll b/test/CodeGen/Thumb2/bfx.ll new file mode 100644 index 0000000..489349d --- /dev/null +++ b/test/CodeGen/Thumb2/bfx.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + +define i32 @sbfx1(i32 %a) { +; CHECK: sbfx1 +; CHECK: sbfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = sext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx1(i32 %a) { +; CHECK: ubfx1 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = zext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx2(i32 %a) { +; CHECK: ubfx2 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = and i32 %t1, 2047 + ret i32 %t2 +} + diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index 2b20931..6c45349 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 3 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 1 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll index fe0e506..9729534 100644 --- a/test/CodeGen/Thumb2/large-stack.ll +++ b/test/CodeGen/Thumb2/large-stack.ll @@ -27,7 +27,7 @@ define i32 @test3() { ; DARWIN: sub.w sp, sp, #805306368 ; DARWIN: sub sp, #20 ; LINUX: test3: -; LINUX: stmfd sp!, {r4, r7, r11, lr} +; LINUX: stmdb sp!, {r4, r7, r11, lr} ; LINUX: sub.w sp, sp, #805306368 ; LINUX: sub sp, #16 %retval = alloca i32, align 4 diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index f007b5c..55cdac9 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -22,7 +22,7 @@ define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w r9, [r7, #+28] +; CHECK: ldr.w r9, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br i1 false, label %bb, label %bb20 @@ -50,9 +50,9 @@ bb119: ; preds = %bb20, %bb20 bb420: ; preds = %bb20, %bb20 ; CHECK: bb420 ; CHECK: str r{{[0-7]}}, [sp] -; CHECK: str r{{[0-7]}}, [sp, #+4] -; CHECK: str r{{[0-7]}}, [sp, #+8] -; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #+24] +; CHECK: str r{{[0-7]}}, [sp, #4] +; CHECK: str r{{[0-7]}}, [sp, #8] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4 diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll index 9286670..46e053c 100644 --- a/test/CodeGen/Thumb2/load-global.ll +++ b/test/CodeGen/Thumb2/load-global.ll @@ -14,7 +14,7 @@ define i32 @test1() { ; PIC: _test1 ; PIC: add r0, pc -; PIC: .long L_G$non_lazy_ptr-(LPC1_0+4) +; PIC: .long L_G$non_lazy_ptr-(LPC0_0+4) ; LINUX: test1 ; LINUX: .long G(GOT) diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll index ac2cd34..2038606 100644 --- a/test/CodeGen/Thumb2/lsr-deficiency.ll +++ b/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -19,7 +19,7 @@ entry: br label %bb bb: ; preds = %bb, %entry -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK: cmp r2, #0 ; CHECK: sub.w r9, r2, #1 ; CHECK: mov r2, r9 diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 9ab19e9..c298aa2 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -17,24 +17,22 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: ldr.n r2, LCPI1_0 -; CHECK: ldr r3, [r2] -; CHECK: ldr r3, [r3] +; CHECK: ldr.n r2, LCPI0_0 ; CHECK: ldr r2, [r2] -; CHECK: LBB1_2 -; CHECK: LCPI1_0: +; CHECK: ldr r3, [r2] +; CHECK: LBB0_2 +; CHECK: LCPI0_0: ; CHECK-NOT: LCPI1_1: ; CHECK: .section ; PIC: BB#1 -; PIC: ldr.n r2, LCPI1_0 +; PIC: ldr.n r2, LCPI0_0 ; PIC: add r2, pc -; PIC: ldr r3, [r2] -; PIC: ldr r3, [r3] ; PIC: ldr r2, [r2] -; PIC: LBB1_2 -; PIC: LCPI1_0: -; PIC-NOT: LCPI1_1: +; PIC: ldr r3, [r2] +; PIC: LBB0_2 +; PIC: LCPI0_0: +; PIC-NOT: LCPI0_1: ; PIC: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll index 496158c..e465c00 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -23,7 +23,7 @@ bb52: ; preds = %newFuncRoot ; CHECK: movne ; CHECK: moveq ; CHECK: pop -; CHECK-NEXT: LBB1_1: +; CHECK-NEXT: LBB0_1: %0 = load i64* @posed, align 4 ; <i64> [#uses=3] %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1] %2 = ashr i64 %1, 1 ; <i64> [#uses=3] diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll index 94888fd..88434f1 100644 --- a/test/CodeGen/Thumb2/thumb2-ldr.ll +++ b/test/CodeGen/Thumb2/thumb2-ldr.ll @@ -11,7 +11,7 @@ entry: define i32 @f2(i32* %v) { entry: ; CHECK: f2: -; CHECK: ldr.w r0, [r0, #+4092] +; CHECK: ldr.w r0, [r0, #4092] %tmp2 = getelementptr i32* %v, i32 1023 %tmp = load i32* %tmp2 ret i32 %tmp diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll index f1fb79c..fee97bf 100644 --- a/test/CodeGen/Thumb2/thumb2-ldrh.ll +++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll @@ -11,7 +11,7 @@ entry: define i16 @f2(i16* %v) { entry: ; CHECK: f2: -; CHECK: ldrh.w r0, [r0, #+2046] +; CHECK: ldrh.w r0, [r0, #2046] %tmp2 = getelementptr i16* %v, i16 1023 %tmp = load i16* %tmp2 ret i16 %tmp diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll index 3eeec8c..11bb936 100644 --- a/test/CodeGen/Thumb2/thumb2-str.ll +++ b/test/CodeGen/Thumb2/thumb2-str.ll @@ -9,7 +9,7 @@ define i32 @f1(i32 %a, i32* %v) { define i32 @f2(i32 %a, i32* %v) { ; CHECK: f2: -; CHECK: str.w r0, [r1, #+4092] +; CHECK: str.w r0, [r1, #4092] %tmp2 = getelementptr i32* %v, i32 1023 store i32 %a, i32* %tmp2 ret i32 %a diff --git a/test/CodeGen/Thumb2/thumb2-str_pre.ll b/test/CodeGen/Thumb2/thumb2-str_pre.ll index 9af960b..1e6616a 100644 --- a/test/CodeGen/Thumb2/thumb2-str_pre.ll +++ b/test/CodeGen/Thumb2/thumb2-str_pre.ll @@ -2,7 +2,7 @@ define void @test1(i32* %X, i32* %A, i32** %dest) { ; CHECK: test1 -; CHECK: str r1, [r0, #+16]! +; CHECK: str r1, [r0, #16]! %B = load i32* %A ; <i32> [#uses=1] %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] store i32 %B, i32* %Y @@ -12,7 +12,7 @@ define void @test1(i32* %X, i32* %A, i32** %dest) { define i16* @test2(i16* %X, i32* %A) { ; CHECK: test2 -; CHECK: strh r1, [r0, #+8]! +; CHECK: strh r1, [r0, #8]! %B = load i32* %A ; <i32> [#uses=1] %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] %tmp = trunc i32 %B to i16 ; <i16> [#uses=1] diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll index 1ebb938..7978e7f 100644 --- a/test/CodeGen/Thumb2/thumb2-strb.ll +++ b/test/CodeGen/Thumb2/thumb2-strb.ll @@ -9,7 +9,7 @@ define i8 @f1(i8 %a, i8* %v) { define i8 @f2(i8 %a, i8* %v) { ; CHECK: f2: -; CHECK: strb.w r0, [r1, #+4092] +; CHECK: strb.w r0, [r1, #4092] %tmp2 = getelementptr i8* %v, i32 4092 store i8 %a, i8* %tmp2 ret i8 %a diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll index b0eb8c1..97110a72 100644 --- a/test/CodeGen/Thumb2/thumb2-strh.ll +++ b/test/CodeGen/Thumb2/thumb2-strh.ll @@ -9,7 +9,7 @@ define i16 @f1(i16 %a, i16* %v) { define i16 @f2(i16 %a, i16* %v) { ; CHECK: f2: -; CHECK: strh.w r0, [r1, #+4092] +; CHECK: strh.w r0, [r1, #4092] %tmp2 = getelementptr i16* %v, i32 2046 store i16 %a, i16* %tmp2 ret i16 %a diff --git a/test/CodeGen/X86/2004-03-30-Select-Max.ll b/test/CodeGen/X86/2004-03-30-Select-Max.ll index b6631b6..c44d10a 100644 --- a/test/CodeGen/X86/2004-03-30-Select-Max.ll +++ b/test/CodeGen/X86/2004-03-30-Select-Max.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 | not grep {j\[lgbe\]} +; RUN: llc < %s -march=x86 -mcpu=yonah | not grep {j\[lgbe\]} -define i32 @max(i32 %A, i32 %B) { +define i32 @max(i32 %A, i32 %B) nounwind { %gt = icmp sgt i32 %A, %B ; <i1> [#uses=1] %R = select i1 %gt, i32 %A, i32 %B ; <i32> [#uses=1] ret i32 %R diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index 317ed0a..ef19d72 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -11,12 +11,12 @@ define float @foo(float %x) nounwind { %tmp14 = fadd float %tmp12, %tmp7 ret float %tmp14 -; CHECK: mulss LCPI1_3(%rip) -; CHECK-NEXT: mulss LCPI1_0(%rip) -; CHECK-NEXT: mulss LCPI1_1(%rip) -; CHECK-NEXT: mulss LCPI1_2(%rip) -; CHECK-NEXT: addss -; CHECK-NEXT: addss -; CHECK-NEXT: addss -; CHECK-NEXT: ret +; CHECK: mulss LCPI0_0(%rip) +; CHECK: mulss LCPI0_1(%rip) +; CHECK: addss +; CHECK: mulss LCPI0_2(%rip) +; CHECK: addss +; CHECK: mulss LCPI0_3(%rip) +; CHECK: addss +; CHECK: ret } diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll index 5e7c0a7..a228898 100644 --- a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll +++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86-64 > %t -; RUN: grep leaq %t ; RUN: not grep {,%rsp)} %t ; PR1103 diff --git a/test/CodeGen/Generic/2007-02-16-BranchFold.ll b/test/CodeGen/X86/2007-02-16-BranchFold.ll index 6bf5631..6bf5631 100644 --- a/test/CodeGen/Generic/2007-02-16-BranchFold.ll +++ b/test/CodeGen/X86/2007-02-16-BranchFold.ll diff --git a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll index 113d0eb..c39b82a 100644 --- a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll +++ b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll @@ -1,12 +1,16 @@ -; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep paddq | count 2 -; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep movq | count 2 +; RUN: llc < %s -o - -march=x86 -mattr=+mmx | FileCheck %s -define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) { +define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) nounwind { entry: %tmp2942 = icmp eq i32 %count, 0 ; <i1> [#uses=1] br i1 %tmp2942, label %bb31, label %bb26 bb26: ; preds = %bb26, %entry + +; CHECK: movq ({{.*}},8), %mm +; CHECK: paddq ({{.*}},8), %mm +; CHECK: paddq %mm{{[0-7]}}, %mm + %i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3] %sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1] %tmp13 = getelementptr <1 x i64>* %b, i32 %i.037.0 ; <<1 x i64>*> [#uses=1] diff --git a/test/CodeGen/Generic/2007-05-05-Personality.ll b/test/CodeGen/X86/2007-05-05-Personality.ll index c92783e..c92783e 100644 --- a/test/CodeGen/Generic/2007-05-05-Personality.ll +++ b/test/CodeGen/X86/2007-05-05-Personality.ll diff --git a/test/CodeGen/X86/2007-10-16-IllegalAsm.ll b/test/CodeGen/X86/2007-10-16-IllegalAsm.ll deleted file mode 100644 index 6d0cb47..0000000 --- a/test/CodeGen/X86/2007-10-16-IllegalAsm.ll +++ /dev/null @@ -1,272 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep movb | not grep x -; PR1734 - - %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.eh_status = type opaque - %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** } - %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* } - %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 } - %struct.initial_value_struct = type opaque - %struct.lang_decl = type opaque - %struct.lang_type = type opaque - %struct.language_function = type opaque - %struct.location_t = type { i8*, i32 } - %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 } - %struct.rtunion = type { i8* } - %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] } - %struct.rtx_def = type { i16, i8, i8, %struct.u } - %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* } - %struct.stack_local_entry = type opaque - %struct.temp_slot = type opaque - %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 } - %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* } - %struct.tree_decl_u1 = type { i64 } - %struct.tree_decl_u2 = type { %struct.function* } - %struct.tree_node = type { %struct.tree_decl } - %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* } - %struct.u = type { [1 x %struct.rtunion] } - %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } - %struct.varasm_status = type opaque - %struct.varray_data = type { [1 x i64] } - %struct.varray_head_tag = type { i64, i64, i32, i8*, %struct.varray_data } - %union.tree_ann_d = type opaque -@.str = external constant [28 x i8] ; <[28 x i8]*> [#uses=1] -@tree_code_type = external constant [0 x i32] ; <[0 x i32]*> [#uses=5] -@global_trees = external global [47 x %struct.tree_node*] ; <[47 x %struct.tree_node*]*> [#uses=1] -@mode_size = external global [48 x i8] ; <[48 x i8]*> [#uses=1] -@__FUNCTION__.22683 = external constant [12 x i8] ; <[12 x i8]*> [#uses=1] - -define void @layout_type(%struct.tree_node* %type) { -entry: - %tmp15 = icmp eq %struct.tree_node* %type, null ; <i1> [#uses=1] - br i1 %tmp15, label %cond_true, label %cond_false - -cond_true: ; preds = %entry - tail call void @fancy_abort( i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1713, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_false: ; preds = %entry - %tmp19 = load %struct.tree_node** getelementptr ([47 x %struct.tree_node*]* @global_trees, i32 0, i64 0), align 8 ; <%struct.tree_node*> [#uses=1] - %tmp21 = icmp eq %struct.tree_node* %tmp19, %type ; <i1> [#uses=1] - br i1 %tmp21, label %UnifiedReturnBlock, label %cond_next25 - -cond_next25: ; preds = %cond_false - %tmp30 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1] - %tmp3031 = bitcast i8* %tmp30 to i32* ; <i32*> [#uses=6] - %tmp32 = load i32* %tmp3031, align 8 ; <i32> [#uses=3] - %tmp3435 = trunc i32 %tmp32 to i8 ; <i8> [#uses=3] - %tmp34353637 = zext i8 %tmp3435 to i64 ; <i64> [#uses=1] - %tmp38 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp34353637 ; <i32*> [#uses=1] - %tmp39 = load i32* %tmp38, align 4 ; <i32> [#uses=1] - %tmp40 = icmp eq i32 %tmp39, 2 ; <i1> [#uses=4] - br i1 %tmp40, label %cond_next46, label %cond_true43 - -cond_true43: ; preds = %cond_next25 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1719, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next46: ; preds = %cond_next25 - %tmp4950 = bitcast %struct.tree_node* %type to %struct.tree_type* ; <%struct.tree_type*> [#uses=2] - %tmp51 = getelementptr %struct.tree_type* %tmp4950, i32 0, i32 2 ; <%struct.tree_node**> [#uses=2] - %tmp52 = load %struct.tree_node** %tmp51, align 8 ; <%struct.tree_node*> [#uses=1] - %tmp53 = icmp eq %struct.tree_node* %tmp52, null ; <i1> [#uses=1] - br i1 %tmp53, label %cond_next57, label %UnifiedReturnBlock - -cond_next57: ; preds = %cond_next46 - %tmp65 = and i32 %tmp32, 255 ; <i32> [#uses=1] - switch i32 %tmp65, label %UnifiedReturnBlock [ - i32 6, label %bb140 - i32 7, label %bb69 - i32 8, label %bb140 - i32 13, label %bb478 - i32 23, label %bb - ] - -bb: ; preds = %cond_next57 - tail call void @fancy_abort( i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1727, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -bb69: ; preds = %cond_next57 - br i1 %tmp40, label %cond_next91, label %cond_true88 - -cond_true88: ; preds = %bb69 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1730, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next91: ; preds = %bb69 - %tmp96 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 8 ; <i8*> [#uses=1] - %tmp9697 = bitcast i8* %tmp96 to i32* ; <i32*> [#uses=2] - %tmp98 = load i32* %tmp9697, align 8 ; <i32> [#uses=2] - %tmp100101552 = and i32 %tmp98, 511 ; <i32> [#uses=1] - %tmp102 = icmp eq i32 %tmp100101552, 0 ; <i1> [#uses=1] - br i1 %tmp102, label %cond_true105, label %bb140 - -cond_true105: ; preds = %cond_next91 - br i1 %tmp40, label %cond_next127, label %cond_true124 - -cond_true124: ; preds = %cond_true105 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1731, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next127: ; preds = %cond_true105 - %tmp136 = or i32 %tmp98, 1 ; <i32> [#uses=1] - %tmp137 = and i32 %tmp136, -511 ; <i32> [#uses=1] - store i32 %tmp137, i32* %tmp9697, align 8 - br label %bb140 - -bb140: ; preds = %cond_next127, %cond_next91, %cond_next57, %cond_next57 - switch i8 %tmp3435, label %cond_true202 [ - i8 6, label %cond_next208 - i8 9, label %cond_next208 - i8 7, label %cond_next208 - i8 8, label %cond_next208 - i8 10, label %cond_next208 - ] - -cond_true202: ; preds = %bb140 - tail call void (%struct.tree_node*, i8*, i32, i8*, ...)* @tree_check_failed( %struct.tree_node* %type, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1738, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0), i32 9, i32 6, i32 7, i32 8, i32 10, i32 0 ) - unreachable - -cond_next208: ; preds = %bb140, %bb140, %bb140, %bb140, %bb140 - %tmp213 = getelementptr %struct.tree_type* %tmp4950, i32 0, i32 14 ; <%struct.tree_node**> [#uses=1] - %tmp214 = load %struct.tree_node** %tmp213, align 8 ; <%struct.tree_node*> [#uses=2] - %tmp217 = getelementptr %struct.tree_node* %tmp214, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1] - %tmp217218 = bitcast i8* %tmp217 to i32* ; <i32*> [#uses=1] - %tmp219 = load i32* %tmp217218, align 8 ; <i32> [#uses=1] - %tmp221222 = trunc i32 %tmp219 to i8 ; <i8> [#uses=1] - %tmp223 = icmp eq i8 %tmp221222, 24 ; <i1> [#uses=1] - br i1 %tmp223, label %cond_true226, label %cond_next340 - -cond_true226: ; preds = %cond_next208 - switch i8 %tmp3435, label %cond_true288 [ - i8 6, label %cond_next294 - i8 9, label %cond_next294 - i8 7, label %cond_next294 - i8 8, label %cond_next294 - i8 10, label %cond_next294 - ] - -cond_true288: ; preds = %cond_true226 - tail call void (%struct.tree_node*, i8*, i32, i8*, ...)* @tree_check_failed( %struct.tree_node* %type, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1739, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0), i32 9, i32 6, i32 7, i32 8, i32 10, i32 0 ) - unreachable - -cond_next294: ; preds = %cond_true226, %cond_true226, %cond_true226, %cond_true226, %cond_true226 - %tmp301 = tail call i32 @tree_int_cst_sgn( %struct.tree_node* %tmp214 ) ; <i32> [#uses=1] - %tmp302 = icmp sgt i32 %tmp301, -1 ; <i1> [#uses=1] - br i1 %tmp302, label %cond_true305, label %cond_next340 - -cond_true305: ; preds = %cond_next294 - %tmp313 = load i32* %tmp3031, align 8 ; <i32> [#uses=2] - %tmp315316 = trunc i32 %tmp313 to i8 ; <i8> [#uses=1] - %tmp315316317318 = zext i8 %tmp315316 to i64 ; <i64> [#uses=1] - %tmp319 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp315316317318 ; <i32*> [#uses=1] - %tmp320 = load i32* %tmp319, align 4 ; <i32> [#uses=1] - %tmp321 = icmp eq i32 %tmp320, 2 ; <i1> [#uses=1] - br i1 %tmp321, label %cond_next327, label %cond_true324 - -cond_true324: ; preds = %cond_true305 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1740, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next327: ; preds = %cond_true305 - %tmp338 = or i32 %tmp313, 8192 ; <i32> [#uses=1] - store i32 %tmp338, i32* %tmp3031, align 8 - br label %cond_next340 - -cond_next340: ; preds = %cond_next327, %cond_next294, %cond_next208 - %tmp348 = load i32* %tmp3031, align 8 ; <i32> [#uses=1] - %tmp350351 = trunc i32 %tmp348 to i8 ; <i8> [#uses=1] - %tmp350351352353 = zext i8 %tmp350351 to i64 ; <i64> [#uses=1] - %tmp354 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp350351352353 ; <i32*> [#uses=1] - %tmp355 = load i32* %tmp354, align 4 ; <i32> [#uses=1] - %tmp356 = icmp eq i32 %tmp355, 2 ; <i1> [#uses=1] - br i1 %tmp356, label %cond_next385, label %cond_true359 - -cond_true359: ; preds = %cond_next340 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1742, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next385: ; preds = %cond_next340 - %tmp390 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 8 ; <i8*> [#uses=1] - %tmp390391 = bitcast i8* %tmp390 to i32* ; <i32*> [#uses=3] - %tmp392 = load i32* %tmp390391, align 8 ; <i32> [#uses=1] - %tmp394 = and i32 %tmp392, 511 ; <i32> [#uses=1] - %tmp397 = tail call i32 @smallest_mode_for_size( i32 %tmp394, i32 2 ) ; <i32> [#uses=1] - %tmp404 = load i32* %tmp390391, align 8 ; <i32> [#uses=1] - %tmp397398405 = shl i32 %tmp397, 9 ; <i32> [#uses=1] - %tmp407 = and i32 %tmp397398405, 65024 ; <i32> [#uses=1] - %tmp408 = and i32 %tmp404, -65025 ; <i32> [#uses=1] - %tmp409 = or i32 %tmp408, %tmp407 ; <i32> [#uses=2] - store i32 %tmp409, i32* %tmp390391, align 8 - %tmp417 = load i32* %tmp3031, align 8 ; <i32> [#uses=1] - %tmp419420 = trunc i32 %tmp417 to i8 ; <i8> [#uses=1] - %tmp419420421422 = zext i8 %tmp419420 to i64 ; <i64> [#uses=1] - %tmp423 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp419420421422 ; <i32*> [#uses=1] - %tmp424 = load i32* %tmp423, align 4 ; <i32> [#uses=1] - %tmp425 = icmp eq i32 %tmp424, 2 ; <i1> [#uses=1] - br i1 %tmp425, label %cond_next454, label %cond_true428 - -cond_true428: ; preds = %cond_next385 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1744, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next454: ; preds = %cond_next385 - lshr i32 %tmp409, 9 ; <i32>:0 [#uses=1] - trunc i32 %0 to i8 ; <i8>:1 [#uses=1] - %tmp463464 = and i8 %1, 127 ; <i8> [#uses=1] - %tmp463464465466 = zext i8 %tmp463464 to i64 ; <i64> [#uses=1] - %tmp467 = getelementptr [48 x i8]* @mode_size, i32 0, i64 %tmp463464465466 ; <i8*> [#uses=1] - %tmp468 = load i8* %tmp467, align 1 ; <i8> [#uses=1] - %tmp468469553 = zext i8 %tmp468 to i16 ; <i16> [#uses=1] - %tmp470471 = shl i16 %tmp468469553, 3 ; <i16> [#uses=1] - %tmp470471472 = zext i16 %tmp470471 to i64 ; <i64> [#uses=1] - %tmp473 = tail call %struct.tree_node* @size_int_kind( i64 %tmp470471472, i32 2 ) ; <%struct.tree_node*> [#uses=1] - store %struct.tree_node* %tmp473, %struct.tree_node** %tmp51, align 8 - ret void - -bb478: ; preds = %cond_next57 - br i1 %tmp40, label %cond_next500, label %cond_true497 - -cond_true497: ; preds = %bb478 - tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1755, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next500: ; preds = %bb478 - %tmp506 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 0, i32 1 ; <%struct.tree_node**> [#uses=1] - %tmp507 = load %struct.tree_node** %tmp506, align 8 ; <%struct.tree_node*> [#uses=2] - %tmp511 = getelementptr %struct.tree_node* %tmp507, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1] - %tmp511512 = bitcast i8* %tmp511 to i32* ; <i32*> [#uses=1] - %tmp513 = load i32* %tmp511512, align 8 ; <i32> [#uses=2] - %tmp515516 = trunc i32 %tmp513 to i8 ; <i8> [#uses=1] - %tmp515516517518 = zext i8 %tmp515516 to i64 ; <i64> [#uses=1] - %tmp519 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp515516517518 ; <i32*> [#uses=1] - %tmp520 = load i32* %tmp519, align 4 ; <i32> [#uses=1] - %tmp521 = icmp eq i32 %tmp520, 2 ; <i1> [#uses=1] - br i1 %tmp521, label %cond_next527, label %cond_true524 - -cond_true524: ; preds = %cond_next500 - tail call void @tree_class_check_failed( %struct.tree_node* %tmp507, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1755, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) ) - unreachable - -cond_next527: ; preds = %cond_next500 - %tmp545 = and i32 %tmp513, 8192 ; <i32> [#uses=1] - %tmp547 = and i32 %tmp32, -8193 ; <i32> [#uses=1] - %tmp548 = or i32 %tmp547, %tmp545 ; <i32> [#uses=1] - store i32 %tmp548, i32* %tmp3031, align 8 - ret void - -UnifiedReturnBlock: ; preds = %cond_next57, %cond_next46, %cond_false - ret void -} - -declare void @fancy_abort(i8*, i32, i8*) - -declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*) - -declare i32 @smallest_mode_for_size(i32, i32) - -declare %struct.tree_node* @size_int_kind(i64, i32) - -declare void @tree_check_failed(%struct.tree_node*, i8*, i32, i8*, ...) - -declare i32 @tree_int_cst_sgn(%struct.tree_node*) diff --git a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll index 387645f..b936686 100644 --- a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep {.byte 0} +; RUN: llc < %s -march=x86 | grep nop target triple = "i686-apple-darwin8" diff --git a/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/test/CodeGen/X86/2008-08-05-SpillerBug.ll index 4c64934..d9d95b5 100644 --- a/test/CodeGen/X86/2008-08-05-SpillerBug.ll +++ b/test/CodeGen/X86/2008-08-05-SpillerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 55 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -disable-fp-elim -stats |& grep asm-printer | grep 55 ; PR2568 @g_3 = external global i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/X86/2008-10-16-SpillerBug.ll b/test/CodeGen/X86/2008-10-16-SpillerBug.ll index b8ca364..f811230 100644 --- a/test/CodeGen/X86/2008-10-16-SpillerBug.ll +++ b/test/CodeGen/X86/2008-10-16-SpillerBug.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi} +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 40 +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s %struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } %struct.XXDAlphaTest = type { float, i16, i8, i8 } @@ -61,11 +62,15 @@ define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind { entry: +; CHECK: t: +; CHECK: xorl %ecx, %ecx %0 = trunc i64 %key_token to i32 ; <i32> [#uses=1] %1 = getelementptr %struct.YYToken* %pstrm, i32 %0 ; <%struct.YYToken*> [#uses=5] br label %bb1132 bb51: ; preds = %bb1132 +; CHECK: .align 4 +; CHECK: andl $7 %2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0 ; <i16*> [#uses=1] %3 = load i16* %2, align 1 ; <i16> [#uses=3] %4 = lshr i16 %3, 6 ; <i16> [#uses=1] diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll index a6cabc4..5eba9b9 100644 --- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll +++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll @@ -3,7 +3,7 @@ ; Make sure the copy after inline asm is not coalesced away. ; CHECK: ## InlineAsm End -; CHECK-NEXT: BB1_2: +; CHECK-NEXT: BB0_2: ; CHECK-NEXT: movl %esi, %eax diff --git a/test/CodeGen/X86/2009-02-05-CoalescerBug.ll b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll index 0ffa8fd..a46a20b 100644 --- a/test/CodeGen/X86/2009-02-05-CoalescerBug.ll +++ b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movaps | count 4 +; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t +; RUN: grep movss %t | count 2 +; RUN: grep movaps %t | count 2 +; RUN: grep movdqa %t | count 2 define i1 @t([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind { newFuncRoot: diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index a4d642b..d9655fd 100644 --- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s ; rdar://6627786 +; rdar://7792037 target triple = "x86_64-apple-darwin10.0" %struct.Key = type { i64 } @@ -11,6 +13,13 @@ entry: br label %bb4 bb4: ; preds = %bb.i, %bb26, %bb4, %entry +; CHECK: %bb4 +; CHECK: xorb +; CHECK: callq +; CHECK: movq +; CHECK: xorl +; CHECK: xorb + %0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0] %ins = or i64 %p, 2097152 ; <i64> [#uses=1] %1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll index ad7f9f7..8d42627 100644 --- a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll +++ b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll @@ -28,5 +28,5 @@ lpad: ; preds = %cont, %entry } ; CHECK: call{{.*}}f -; CHECK-NEXT: Llabel1: +; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: movl %eax, %esi diff --git a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll index 11c4101..da493d4 100644 --- a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll +++ b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll @@ -21,4 +21,4 @@ lpad: ; preds = %cont, %entry } ; CHECK: lpad -; CHECK-NEXT: Llabel +; CHECK-NEXT: Ltmp diff --git a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll index 2fd42f4..1d14620 100644 --- a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll +++ b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll @@ -1,38 +1,15 @@ ; RUN: llc < %s -march=x86-64 - %struct.tempsym_t = type { i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32 } - -define fastcc signext i8 @S_next_symbol(%struct.tempsym_t* %symptr) nounwind ssp { +define fastcc void @S_next_symbol(i448* %P) nounwind ssp { entry: - br label %bb116 - -bb: ; preds = %bb116 - switch i8 undef, label %bb14 [ - i8 9, label %bb116 - i8 32, label %bb116 - i8 10, label %bb116 - i8 13, label %bb116 - i8 12, label %bb116 - ] + br label %bb14 bb14: ; preds = %bb - br i1 undef, label %bb75, label %bb115 - -bb75: ; preds = %bb14 - %srcval16 = load i448* null, align 8 ; <i448> [#uses=1] + %srcval16 = load i448* %P, align 8 ; <i448> [#uses=1] %tmp = zext i32 undef to i448 ; <i448> [#uses=1] %tmp15 = shl i448 %tmp, 288 ; <i448> [#uses=1] %mask = and i448 %srcval16, -2135987035423586845985235064014169866455883682256196619149693890381755748887481053010428711403521 ; <i448> [#uses=1] %ins = or i448 %tmp15, %mask ; <i448> [#uses=1] - store i448 %ins, i448* null, align 8 - ret i8 1 - -bb115: ; preds = %bb14 - ret i8 1 - -bb116: ; preds = %bb, %bb, %bb, %bb, %bb, %entry - br i1 undef, label %bb, label %bb117 - -bb117: ; preds = %bb116 - ret i8 0 + store i448 %ins, i448* %P, align 8 + ret void } diff --git a/test/CodeGen/X86/2009-08-06-inlineasm.ll b/test/CodeGen/X86/2009-08-06-inlineasm.ll index cc2f3d8..de32c21 100644 --- a/test/CodeGen/X86/2009-08-06-inlineasm.ll +++ b/test/CodeGen/X86/2009-08-06-inlineasm.ll @@ -1,8 +1,10 @@ -; RUN: llc < %s +; RUN: llc -mtriple=i386-pc-linux-gnu < %s ; PR4668 -; ModuleID = '<stdin>' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i386-pc-linux-gnu" +; XFAIL: * +; FIXME: If the coalescer happens to coalesce %level.1 with the copy to EAX +; (for ret) then this will fail to compile. The fundamental problem is +; once the coalescer fixes a virtual register to physical register we can't +; evict it. define i32 @x(i32 %qscale) nounwind { entry: diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll index 8f274df..2ac688f 100644 --- a/test/CodeGen/X86/2009-11-16-MachineLICM.ll +++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll @@ -15,7 +15,7 @@ bb.nph: ; preds = %entry br label %bb bb: ; preds = %bb, %bb.nph -; CHECK: LBB1_2: +; CHECK: LBB0_2: %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=2] %tmp9 = shl i64 %indvar, 2 ; <i64> [#uses=4] %tmp1016 = or i64 %tmp9, 1 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll index 3ce9edb..d33f93e 100644 --- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll +++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s ; rdar://7396984 @str = private constant [28 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 1 @@ -13,7 +13,7 @@ entry: br label %bb1 bb1: -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK: movaps %xmm0, (%rsp) %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ] call void @llvm.memcpy.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1) diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll index 172e1c7..c693636 100644 --- a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll +++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll @@ -10,7 +10,7 @@ entry: ; CHECK: movl $1 ; CHECK: movl (%ebp), %eax ; CHECK: movl 4(%ebp), %edx -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK-NOT: movl $1 ; CHECK-NOT: movl $0 ; CHECK: addl diff --git a/test/CodeGen/X86/2010-03-17-ISelBug.ll b/test/CodeGen/X86/2010-03-17-ISelBug.ll new file mode 100644 index 0000000..609b4e2 --- /dev/null +++ b/test/CodeGen/X86/2010-03-17-ISelBug.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin5 +; rdar://7761790 + +%"struct..0$_485" = type { i16, i16, i32 } +%union.PPToken = type { %"struct..0$_485" } +%struct.PPOperation = type { %union.PPToken, %union.PPToken, [6 x %union.PPToken], i32, i32, i32, [1 x i32], [0 x i8] } + +define i32* @t() align 2 nounwind { +entry: + %operation = alloca %struct.PPOperation, align 8 ; <%struct.PPOperation*> [#uses=2] + %0 = load i32*** null, align 4 ; [#uses=1] + %1 = ptrtoint i32** %0 to i32 ; <i32> [#uses=1] + %2 = sub nsw i32 %1, undef ; <i32> [#uses=2] + br i1 false, label %bb20, label %bb.nph380 + +bb20: ; preds = %entry + ret i32* null + +bb.nph380: ; preds = %entry + %scevgep403 = getelementptr %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 2 ; <i32*> [#uses=1] + %3 = ashr i32 %2, 1 ; <i32> [#uses=1] + %tmp405 = and i32 %3, -2 ; <i32> [#uses=1] + %scevgep408 = getelementptr %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 1 ; <i16*> [#uses=1] + %tmp410 = and i32 %2, -4 ; <i32> [#uses=1] + br label %bb169 + +bb169: ; preds = %bb169, %bb.nph380 + %index.6379 = phi i32 [ 0, %bb.nph380 ], [ %4, %bb169 ] ; <i32> [#uses=3] + %tmp404 = mul i32 %index.6379, -2 ; <i32> [#uses=1] + %tmp406 = add i32 %tmp405, %tmp404 ; <i32> [#uses=1] + %scevgep407 = getelementptr i32* %scevgep403, i32 %tmp406 ; <i32*> [#uses=1] + %tmp409 = mul i32 %index.6379, -4 ; <i32> [#uses=1] + %tmp411 = add i32 %tmp410, %tmp409 ; <i32> [#uses=1] + %scevgep412 = getelementptr i16* %scevgep408, i32 %tmp411 ; <i16*> [#uses=1] + store i16 undef, i16* %scevgep412, align 2 + store i32 undef, i32* %scevgep407, align 4 + %4 = add nsw i32 %index.6379, 1 ; <i32> [#uses=1] + br label %bb169 +} diff --git a/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll new file mode 100644 index 0000000..ef1798d --- /dev/null +++ b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll @@ -0,0 +1,64 @@ +; RUN: llc < %s -O3 -relocation-model=pic -disable-fp-elim -mcpu=nocona +; +; This test case is reduced from Bullet. It crashes SSEDomainFix. +; +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0" + +declare i32 @_ZN11HullLibrary16CreateConvexHullERK8HullDescR10HullResult(i8*, i8* nocapture, i8* nocapture) ssp align 2 + +define void @_ZN17btSoftBodyHelpers4DrawEP10btSoftBodyP12btIDebugDrawi(i8* %psb, i8* %idraw, i32 %drawflags) ssp align 2 { +entry: + br i1 undef, label %bb92, label %bb58 + +bb58: ; preds = %entry + %0 = invoke i32 @_ZN11HullLibrary16CreateConvexHullERK8HullDescR10HullResult(i8* undef, i8* undef, i8* undef) + to label %invcont64 unwind label %lpad159 ; <i32> [#uses=0] + +invcont64: ; preds = %bb58 + br i1 undef, label %invcont65, label %bb.i.i + +bb.i.i: ; preds = %invcont64 + %1 = load <4 x float>* undef, align 16 ; <<4 x float>> [#uses=5] + br i1 undef, label %bb.nph.i.i, label %invcont65 + +bb.nph.i.i: ; preds = %bb.i.i + %tmp22.i.i = bitcast <4 x float> %1 to i128 ; <i128> [#uses=1] + %tmp23.i.i = trunc i128 %tmp22.i.i to i32 ; <i32> [#uses=1] + %2 = bitcast i32 %tmp23.i.i to float ; <float> [#uses=1] + %tmp6.i = extractelement <4 x float> %1, i32 1 ; <float> [#uses=1] + %tmp2.i = extractelement <4 x float> %1, i32 2 ; <float> [#uses=1] + br label %bb1.i.i + +bb1.i.i: ; preds = %bb1.i.i, %bb.nph.i.i + %.tmp6.0.i.i = phi float [ %tmp2.i, %bb.nph.i.i ], [ %5, %bb1.i.i ] ; <float> [#uses=1] + %.tmp5.0.i.i = phi float [ %tmp6.i, %bb.nph.i.i ], [ %4, %bb1.i.i ] ; <float> [#uses=1] + %.tmp.0.i.i = phi float [ %2, %bb.nph.i.i ], [ %3, %bb1.i.i ] ; <float> [#uses=1] + %3 = fadd float %.tmp.0.i.i, undef ; <float> [#uses=2] + %4 = fadd float %.tmp5.0.i.i, undef ; <float> [#uses=2] + %5 = fadd float %.tmp6.0.i.i, undef ; <float> [#uses=2] + br i1 undef, label %bb2.return.loopexit_crit_edge.i.i, label %bb1.i.i + +bb2.return.loopexit_crit_edge.i.i: ; preds = %bb1.i.i + %tmp8.i = insertelement <4 x float> %1, float %3, i32 0 ; <<4 x float>> [#uses=1] + %tmp4.i = insertelement <4 x float> %tmp8.i, float %4, i32 1 ; <<4 x float>> [#uses=1] + %tmp.i = insertelement <4 x float> %tmp4.i, float %5, i32 2 ; <<4 x float>> [#uses=1] + br label %invcont65 + +invcont65: ; preds = %bb2.return.loopexit_crit_edge.i.i, %bb.i.i, %invcont64 + %.0.i = phi <4 x float> [ %tmp.i, %bb2.return.loopexit_crit_edge.i.i ], [ undef, %invcont64 ], [ %1, %bb.i.i ] ; <<4 x float>> [#uses=1] + %tmp15.i = extractelement <4 x float> %.0.i, i32 2 ; <float> [#uses=1] + %6 = fmul float %tmp15.i, undef ; <float> [#uses=1] + br label %bb.i265 + +bb.i265: ; preds = %bb.i265, %invcont65 + %7 = fsub float 0.000000e+00, %6 ; <float> [#uses=1] + store float %7, float* undef, align 4 + br label %bb.i265 + +bb92: ; preds = %entry + unreachable + +lpad159: ; preds = %bb58 + unreachable +} diff --git a/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..76cc1a4 --- /dev/null +++ b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,34 @@ +; RUN: llc -O0 -march=x86 -asm-verbose < %s | FileCheck %s +; RUN: llc -O0 -march=x86-64 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll new file mode 100644 index 0000000..1c7c28c --- /dev/null +++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; rdar://7842028 + +; Do not delete partially dead copy instructions. +; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> +; REP_MOVSD %ECX<imp-def,dead>, %EDI<imp-def,dead>, %ESI<imp-def,dead>, %ECX<imp-use,kill>, %EDI<imp-use,kill>, %ESI<imp-use,kill> + + +%struct.F = type { %struct.FC*, i32, i32, i8, i32, i32, i32 } +%struct.FC = type { [10 x i8], [32 x i32], %struct.FC*, i32 } + +define void @t(%struct.F* %this) nounwind { +entry: +; CHECK: t: +; CHECK: addq $12, %rsi + %BitValueArray = alloca [32 x i32], align 4 + %tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0 + %tmp3 = load %struct.FC** %tmp2, align 8 + %tmp4 = getelementptr inbounds %struct.FC* %tmp3, i64 0, i32 1, i64 0 + %tmp5 = bitcast [32 x i32]* %BitValueArray to i8* + %tmp6 = bitcast i32* %tmp4 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp5, i8* %tmp6, i64 128, i32 4, i1 false) + unreachable +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll new file mode 100644 index 0000000..fadbd21 --- /dev/null +++ b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 +; rdar://7857830 + +%0 = type opaque +%1 = type opaque + +define void @t(%0* %self, i8* nocapture %_cmd, %1* %scroller, i32 %hitPart, float %multiplier) nounwind optsize ssp { +entry: + switch i32 %hitPart, label %if.else [ + i32 7, label %if.then + i32 8, label %if.then + ] + +if.then: ; preds = %entry, %entry + %tmp69 = load float* null, align 4 ; <float> [#uses=1] + %cmp19 = icmp eq %1* null, %scroller ; <i1> [#uses=2] + %cond = select i1 %cmp19, float %tmp69, float 0.000000e+00 ; <float> [#uses=1] + %call36 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*)*)(i8* undef, i8* undef) nounwind optsize ; <i64> [#uses=2] + br i1 %cmp19, label %cond.true32, label %cond.false39 + +cond.true32: ; preds = %if.then + %sroa.store.elt68 = lshr i64 %call36, 32 ; <i64> [#uses=1] + %0 = trunc i64 %sroa.store.elt68 to i32 ; <i32> [#uses=1] + br label %cond.end47 + +cond.false39: ; preds = %if.then + %1 = trunc i64 %call36 to i32 ; <i32> [#uses=1] + br label %cond.end47 + +cond.end47: ; preds = %cond.false39, %cond.true32 + %cond48.in = phi i32 [ %0, %cond.true32 ], [ %1, %cond.false39 ] ; <i32> [#uses=1] + %cond48 = bitcast i32 %cond48.in to float ; <float> [#uses=1] + %div = fdiv float %cond, undef ; <float> [#uses=1] + %div58 = fdiv float %div, %cond48 ; <float> [#uses=1] + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, float)*)(i8* undef, i8* undef, float %div58) nounwind optsize + ret void + +if.else: ; preds = %entry + ret void +} + +declare i8* @objc_msgSend(i8*, i8*, ...) diff --git a/test/CodeGen/X86/2010-04-21-CoalescerBug.ll b/test/CodeGen/X86/2010-04-21-CoalescerBug.ll new file mode 100644 index 0000000..d598764 --- /dev/null +++ b/test/CodeGen/X86/2010-04-21-CoalescerBug.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin +; rdar://7886733 + +%struct.CMTime = type <{ i64, i32, i32, i64 }> +%struct.CMTimeMapping = type { %struct.CMTimeRange, %struct.CMTimeRange } +%struct.CMTimeRange = type { %struct.CMTime, %struct.CMTime } + +define void @t(%struct.CMTimeMapping* noalias nocapture sret %agg.result) nounwind optsize ssp { +entry: + %agg.result1 = bitcast %struct.CMTimeMapping* %agg.result to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %agg.result1, i8* null, i64 96, i32 4, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll new file mode 100644 index 0000000..4cd3be3 --- /dev/null +++ b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s + +define void @ti8(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <8 x i8> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <8 x i8> +; CHECK: movdq2q + %tmp3 = add <8 x i8> %tmp1, %tmp2 + store <8 x i8> %tmp3, <8 x i8>* null + ret void +} + +define void @ti16(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <4 x i16> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <4 x i16> +; CHECK: movdq2q + %tmp3 = add <4 x i16> %tmp1, %tmp2 + store <4 x i16> %tmp3, <4 x i16>* null + ret void +} + +define void @ti32(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <2 x i32> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <2 x i32> +; CHECK: movdq2q + %tmp3 = add <2 x i32> %tmp1, %tmp2 + store <2 x i32> %tmp3, <2 x i32>* null + ret void +} + +define void @ti64(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <1 x i64> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <1 x i64> +; CHECK: movdq2q + %tmp3 = add <1 x i64> %tmp1, %tmp2 + store <1 x i64> %tmp3, <1 x i64>* null + ret void +} diff --git a/test/CodeGen/Generic/GC/alloc_loop.ll b/test/CodeGen/X86/GC/alloc_loop.ll index fb78ba2..fb78ba2 100644 --- a/test/CodeGen/Generic/GC/alloc_loop.ll +++ b/test/CodeGen/X86/GC/alloc_loop.ll diff --git a/test/CodeGen/Generic/GC/argpromotion.ll b/test/CodeGen/X86/GC/argpromotion.ll index c63ce22..c63ce22 100644 --- a/test/CodeGen/Generic/GC/argpromotion.ll +++ b/test/CodeGen/X86/GC/argpromotion.ll diff --git a/test/CodeGen/Generic/GC/badreadproto.ll b/test/CodeGen/X86/GC/badreadproto.ll index 4fe90b9..4fe90b9 100644 --- a/test/CodeGen/Generic/GC/badreadproto.ll +++ b/test/CodeGen/X86/GC/badreadproto.ll diff --git a/test/CodeGen/Generic/GC/badrootproto.ll b/test/CodeGen/X86/GC/badrootproto.ll index ff86d03..ff86d03 100644 --- a/test/CodeGen/Generic/GC/badrootproto.ll +++ b/test/CodeGen/X86/GC/badrootproto.ll diff --git a/test/CodeGen/Generic/GC/badwriteproto.ll b/test/CodeGen/X86/GC/badwriteproto.ll index be81f84..be81f84 100644 --- a/test/CodeGen/Generic/GC/badwriteproto.ll +++ b/test/CodeGen/X86/GC/badwriteproto.ll diff --git a/test/CodeGen/Generic/GC/deadargelim.ll b/test/CodeGen/X86/GC/deadargelim.ll index 1760190..1760190 100644 --- a/test/CodeGen/Generic/GC/deadargelim.ll +++ b/test/CodeGen/X86/GC/deadargelim.ll diff --git a/test/CodeGen/Generic/GC/dg.exp b/test/CodeGen/X86/GC/dg.exp index f200589..f200589 100644 --- a/test/CodeGen/Generic/GC/dg.exp +++ b/test/CodeGen/X86/GC/dg.exp diff --git a/test/CodeGen/Generic/GC/fat.ll b/test/CodeGen/X86/GC/fat.ll index d05ca3d..d05ca3d 100644 --- a/test/CodeGen/Generic/GC/fat.ll +++ b/test/CodeGen/X86/GC/fat.ll diff --git a/test/CodeGen/Generic/GC/inline.ll b/test/CodeGen/X86/GC/inline.ll index 9da33ae..9da33ae 100644 --- a/test/CodeGen/Generic/GC/inline.ll +++ b/test/CodeGen/X86/GC/inline.ll diff --git a/test/CodeGen/Generic/GC/inline2.ll b/test/CodeGen/X86/GC/inline2.ll index 1594705..1594705 100644 --- a/test/CodeGen/Generic/GC/inline2.ll +++ b/test/CodeGen/X86/GC/inline2.ll diff --git a/test/CodeGen/Generic/GC/lower_gcroot.ll b/test/CodeGen/X86/GC/lower_gcroot.ll index c2d418a..c2d418a 100644 --- a/test/CodeGen/Generic/GC/lower_gcroot.ll +++ b/test/CodeGen/X86/GC/lower_gcroot.ll diff --git a/test/CodeGen/Generic/GC/outside.ll b/test/CodeGen/X86/GC/outside.ll index 2968c69..2968c69 100644 --- a/test/CodeGen/Generic/GC/outside.ll +++ b/test/CodeGen/X86/GC/outside.ll diff --git a/test/CodeGen/Generic/GC/simple_ocaml.ll b/test/CodeGen/X86/GC/simple_ocaml.ll index f765dc0..f765dc0 100644 --- a/test/CodeGen/Generic/GC/simple_ocaml.ll +++ b/test/CodeGen/X86/GC/simple_ocaml.ll diff --git a/test/CodeGen/X86/MachineSink-CritEdge.ll b/test/CodeGen/X86/MachineSink-CritEdge.ll new file mode 100644 index 0000000..74a1049 --- /dev/null +++ b/test/CodeGen/X86/MachineSink-CritEdge.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @f(i32 %x) nounwind ssp { +entry: + %shl.i = shl i32 %x, 12 + %neg.i = xor i32 %shl.i, -1 + %add.i = add nsw i32 %neg.i, %x + %shr.i = ashr i32 %add.i, 22 + %xor.i = xor i32 %shr.i, %add.i + %shl5.i = shl i32 %xor.i, 13 + %neg6.i = xor i32 %shl5.i, -1 + %add8.i = add nsw i32 %xor.i, %neg6.i + %shr10.i = ashr i32 %add8.i, 8 + %xor12.i = xor i32 %shr10.i, %add8.i + %add16.i = mul i32 %xor12.i, 9 + %shr18.i = ashr i32 %add16.i, 15 + %xor20.i = xor i32 %shr18.i, %add16.i + %shl22.i = shl i32 %xor20.i, 27 + %neg23.i = xor i32 %shl22.i, -1 + %add25.i = add nsw i32 %xor20.i, %neg23.i + %shr27.i = ashr i32 %add25.i, 31 + %rem = srem i32 %x, 7 + %cmp = icmp eq i32 %rem, 3 + br i1 %cmp, label %land.lhs.true, label %do.body.preheader + +land.lhs.true: + %call3 = tail call i32 @g(i32 %x) nounwind + %cmp4 = icmp eq i32 %call3, 10 + br i1 %cmp4, label %do.body.preheader, label %if.then + +; %shl.i should be sinked all the way down to do.body.preheader, but not into the loop. +; CHECK: do.body.preheader +; CHECK-NOT: do.body +; CHECK: shll $12 + +do.body.preheader: + %xor29.i = xor i32 %shr27.i, %add25.i + br label %do.body + +if.then: + %add = add nsw i32 %x, 11 + ret i32 %add + +do.body: + %x.addr.1 = phi i32 [ %add9, %do.body ], [ %x, %do.body.preheader ] + %xor = xor i32 %xor29.i, %x.addr.1 + %add9 = add nsw i32 %xor, %x.addr.1 + %and = and i32 %add9, 13 + %tobool = icmp eq i32 %and, 0 + br i1 %tobool, label %if.end, label %do.body + +if.end: + ret i32 %add9 +} + +declare i32 @g(i32) diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll index 9208738..23042b6 100644 --- a/test/CodeGen/X86/abi-isel.ll +++ b/test/CodeGen/X86/abi-isel.ll @@ -72,12 +72,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo00: -; DARWIN-32-PIC: call L1$pb -; DARWIN-32-PIC-NEXT: L1$pb: +; DARWIN-32-PIC: call L0$pb +; DARWIN-32-PIC-NEXT: L0$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L1$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L0$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L1$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L0$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -144,12 +144,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo00: -; DARWIN-32-PIC: call L2$pb -; DARWIN-32-PIC-NEXT: L2$pb: +; DARWIN-32-PIC: call L1$pb +; DARWIN-32-PIC-NEXT: L1$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L2$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L1$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L2$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L1$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -208,11 +208,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo01: -; DARWIN-32-PIC: call L3$pb -; DARWIN-32-PIC-NEXT: L3$pb: +; DARWIN-32-PIC: call L2$pb +; DARWIN-32-PIC-NEXT: L2$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L3$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L2$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L2$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -268,11 +268,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo01: -; DARWIN-32-PIC: call L4$pb -; DARWIN-32-PIC-NEXT: L4$pb: +; DARWIN-32-PIC: call L3$pb +; DARWIN-32-PIC-NEXT: L3$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L4$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L3$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -342,12 +342,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo02: -; DARWIN-32-PIC: call L5$pb -; DARWIN-32-PIC-NEXT: L5$pb: +; DARWIN-32-PIC: call L4$pb +; DARWIN-32-PIC-NEXT: L4$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L5$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L4$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -424,12 +424,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo02: -; DARWIN-32-PIC: call L6$pb -; DARWIN-32-PIC-NEXT: L6$pb: +; DARWIN-32-PIC: call L5$pb +; DARWIN-32-PIC-NEXT: L5$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L6$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L5$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L6$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -497,11 +497,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo03: -; DARWIN-32-PIC: call L7$pb -; DARWIN-32-PIC-NEXT: L7$pb: +; DARWIN-32-PIC: call L6$pb +; DARWIN-32-PIC-NEXT: L6$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L7$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L7$pb(%eax) +; DARWIN-32-PIC-NEXT: movl _dsrc-L6$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L6$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo03: @@ -551,11 +551,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo04: -; DARWIN-32-PIC: call L8$pb -; DARWIN-32-PIC-NEXT: L8$pb: +; DARWIN-32-PIC: call L7$pb +; DARWIN-32-PIC-NEXT: L7$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L8$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L8$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ddst-L7$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L7$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo04: @@ -619,11 +619,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo05: -; DARWIN-32-PIC: call L9$pb -; DARWIN-32-PIC-NEXT: L9$pb: +; DARWIN-32-PIC: call L8$pb +; DARWIN-32-PIC-NEXT: L8$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L9$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L9$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dsrc-L8$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L8$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -682,11 +682,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo06: -; DARWIN-32-PIC: call L10$pb -; DARWIN-32-PIC-NEXT: L10$pb: +; DARWIN-32-PIC: call L9$pb +; DARWIN-32-PIC-NEXT: L9$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L10$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L10$pb(%eax) +; DARWIN-32-PIC-NEXT: movl _lsrc-L9$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L9$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo06: @@ -735,11 +735,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo07: -; DARWIN-32-PIC: call L11$pb -; DARWIN-32-PIC-NEXT: L11$pb: +; DARWIN-32-PIC: call L10$pb +; DARWIN-32-PIC-NEXT: L10$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L11$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L11$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ldst-L10$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L10$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo07: @@ -801,11 +801,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo08: -; DARWIN-32-PIC: call L12$pb -; DARWIN-32-PIC-NEXT: L12$pb: +; DARWIN-32-PIC: call L11$pb +; DARWIN-32-PIC-NEXT: L11$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L12$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L12$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lsrc-L11$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L11$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -868,12 +868,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux00: -; DARWIN-32-PIC: call L13$pb -; DARWIN-32-PIC-NEXT: L13$pb: +; DARWIN-32-PIC: call L12$pb +; DARWIN-32-PIC-NEXT: L12$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L13$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L12$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L13$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L12$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -939,12 +939,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx00: -; DARWIN-32-PIC: call L14$pb -; DARWIN-32-PIC-NEXT: L14$pb: +; DARWIN-32-PIC: call L13$pb +; DARWIN-32-PIC-NEXT: L13$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L14$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L13$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L14$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L13$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1005,12 +1005,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux01: -; DARWIN-32-PIC: call L15$pb -; DARWIN-32-PIC-NEXT: L15$pb: +; DARWIN-32-PIC: call L14$pb +; DARWIN-32-PIC-NEXT: L14$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L15$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L14$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L14$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1071,12 +1071,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx01: -; DARWIN-32-PIC: call L16$pb -; DARWIN-32-PIC-NEXT: L16$pb: +; DARWIN-32-PIC: call L15$pb +; DARWIN-32-PIC-NEXT: L15$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L16$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L15$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1150,12 +1150,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux02: -; DARWIN-32-PIC: call L17$pb -; DARWIN-32-PIC-NEXT: L17$pb: +; DARWIN-32-PIC: call L16$pb +; DARWIN-32-PIC-NEXT: L16$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L17$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L16$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1233,12 +1233,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx02: -; DARWIN-32-PIC: call L18$pb -; DARWIN-32-PIC-NEXT: L18$pb: +; DARWIN-32-PIC: call L17$pb +; DARWIN-32-PIC-NEXT: L17$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L18$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L17$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L18$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1306,11 +1306,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux03: -; DARWIN-32-PIC: call L19$pb -; DARWIN-32-PIC-NEXT: L19$pb: +; DARWIN-32-PIC: call L18$pb +; DARWIN-32-PIC-NEXT: L18$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L19$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L19$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L18$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L18$pb)+64(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux03: @@ -1361,11 +1361,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux04: -; DARWIN-32-PIC: call L20$pb -; DARWIN-32-PIC-NEXT: L20$pb: +; DARWIN-32-PIC: call L19$pb +; DARWIN-32-PIC-NEXT: L19$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L20$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L20$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L19$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L19$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux04: @@ -1430,11 +1430,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux05: -; DARWIN-32-PIC: call L21$pb -; DARWIN-32-PIC-NEXT: L21$pb: +; DARWIN-32-PIC: call L20$pb +; DARWIN-32-PIC-NEXT: L20$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L21$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L21$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L20$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L20$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1493,11 +1493,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux06: -; DARWIN-32-PIC: call L22$pb -; DARWIN-32-PIC-NEXT: L22$pb: +; DARWIN-32-PIC: call L21$pb +; DARWIN-32-PIC-NEXT: L21$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L22$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L22$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L21$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L21$pb)+64(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux06: @@ -1546,11 +1546,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux07: -; DARWIN-32-PIC: call L23$pb -; DARWIN-32-PIC-NEXT: L23$pb: +; DARWIN-32-PIC: call L22$pb +; DARWIN-32-PIC-NEXT: L22$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L23$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L23$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L22$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L22$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux07: @@ -1613,11 +1613,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux08: -; DARWIN-32-PIC: call L24$pb -; DARWIN-32-PIC-NEXT: L24$pb: +; DARWIN-32-PIC: call L23$pb +; DARWIN-32-PIC-NEXT: L23$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L24$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L24$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L23$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L23$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1686,13 +1686,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind00: -; DARWIN-32-PIC: call L25$pb -; DARWIN-32-PIC-NEXT: L25$pb: +; DARWIN-32-PIC: call L24$pb +; DARWIN-32-PIC-NEXT: L24$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L25$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L25$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L24$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -1764,13 +1764,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd00: -; DARWIN-32-PIC: call L26$pb -; DARWIN-32-PIC-NEXT: L26$pb: +; DARWIN-32-PIC: call L25$pb +; DARWIN-32-PIC-NEXT: L25$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L26$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L26$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L25$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -1840,13 +1840,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind01: -; DARWIN-32-PIC: call L27$pb -; DARWIN-32-PIC-NEXT: L27$pb: +; DARWIN-32-PIC: call L26$pb +; DARWIN-32-PIC-NEXT: L26$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L27$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L26$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L26$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1916,13 +1916,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd01: -; DARWIN-32-PIC: call L28$pb -; DARWIN-32-PIC-NEXT: L28$pb: +; DARWIN-32-PIC: call L27$pb +; DARWIN-32-PIC-NEXT: L27$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L28$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L27$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2001,13 +2001,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind02: -; DARWIN-32-PIC: call L29$pb -; DARWIN-32-PIC-NEXT: L29$pb: +; DARWIN-32-PIC: call L28$pb +; DARWIN-32-PIC-NEXT: L28$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L29$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L28$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2090,13 +2090,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd02: -; DARWIN-32-PIC: call L30$pb -; DARWIN-32-PIC-NEXT: L30$pb: +; DARWIN-32-PIC: call L29$pb +; DARWIN-32-PIC-NEXT: L29$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L30$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L29$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L30$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2170,12 +2170,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind03: -; DARWIN-32-PIC: call L31$pb -; DARWIN-32-PIC-NEXT: L31$pb: +; DARWIN-32-PIC: call L30$pb +; DARWIN-32-PIC-NEXT: L30$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L31$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L31$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl _dsrc-L30$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L30$pb(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind03: @@ -2242,12 +2242,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind04: -; DARWIN-32-PIC: call L32$pb -; DARWIN-32-PIC-NEXT: L32$pb: +; DARWIN-32-PIC: call L31$pb +; DARWIN-32-PIC-NEXT: L31$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ddst-L32$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L32$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ddst-L31$pb(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L31$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind04: @@ -2320,12 +2320,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind05: -; DARWIN-32-PIC: call L33$pb -; DARWIN-32-PIC-NEXT: L33$pb: +; DARWIN-32-PIC: call L32$pb +; DARWIN-32-PIC-NEXT: L32$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L33$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L33$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dsrc-L32$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L32$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2395,12 +2395,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind06: -; DARWIN-32-PIC: call L34$pb -; DARWIN-32-PIC-NEXT: L34$pb: +; DARWIN-32-PIC: call L33$pb +; DARWIN-32-PIC-NEXT: L33$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L34$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L34$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl _lsrc-L33$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L33$pb(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind06: @@ -2466,12 +2466,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind07: -; DARWIN-32-PIC: call L35$pb -; DARWIN-32-PIC-NEXT: L35$pb: +; DARWIN-32-PIC: call L34$pb +; DARWIN-32-PIC-NEXT: L34$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ldst-L35$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L35$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ldst-L34$pb(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L34$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind07: @@ -2543,12 +2543,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind08: -; DARWIN-32-PIC: call L36$pb -; DARWIN-32-PIC-NEXT: L36$pb: +; DARWIN-32-PIC: call L35$pb +; DARWIN-32-PIC-NEXT: L35$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L36$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L36$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lsrc-L35$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L35$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2621,13 +2621,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off00: -; DARWIN-32-PIC: call L37$pb -; DARWIN-32-PIC-NEXT: L37$pb: +; DARWIN-32-PIC: call L36$pb +; DARWIN-32-PIC-NEXT: L36$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L37$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L36$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L37$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L36$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2700,13 +2700,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf00: -; DARWIN-32-PIC: call L38$pb -; DARWIN-32-PIC-NEXT: L38$pb: +; DARWIN-32-PIC: call L37$pb +; DARWIN-32-PIC-NEXT: L37$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L38$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L37$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L38$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L37$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2777,13 +2777,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off01: -; DARWIN-32-PIC: call L39$pb -; DARWIN-32-PIC-NEXT: L39$pb: +; DARWIN-32-PIC: call L38$pb +; DARWIN-32-PIC-NEXT: L38$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L39$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L38$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L38$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2854,13 +2854,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf01: -; DARWIN-32-PIC: call L40$pb -; DARWIN-32-PIC-NEXT: L40$pb: +; DARWIN-32-PIC: call L39$pb +; DARWIN-32-PIC-NEXT: L39$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L40$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L39$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2940,13 +2940,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off02: -; DARWIN-32-PIC: call L41$pb -; DARWIN-32-PIC-NEXT: L41$pb: +; DARWIN-32-PIC: call L40$pb +; DARWIN-32-PIC-NEXT: L40$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L41$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L40$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3030,13 +3030,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf02: -; DARWIN-32-PIC: call L42$pb -; DARWIN-32-PIC-NEXT: L42$pb: +; DARWIN-32-PIC: call L41$pb +; DARWIN-32-PIC-NEXT: L41$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L42$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L41$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L42$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3111,12 +3111,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off03: -; DARWIN-32-PIC: call L43$pb -; DARWIN-32-PIC-NEXT: L43$pb: +; DARWIN-32-PIC: call L42$pb +; DARWIN-32-PIC-NEXT: L42$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L43$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L43$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L42$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L42$pb)+64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off03: @@ -3184,12 +3184,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off04: -; DARWIN-32-PIC: call L44$pb -; DARWIN-32-PIC-NEXT: L44$pb: +; DARWIN-32-PIC: call L43$pb +; DARWIN-32-PIC-NEXT: L43$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L44$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L44$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L43$pb)+64(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L43$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off04: @@ -3263,12 +3263,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off05: -; DARWIN-32-PIC: call L45$pb -; DARWIN-32-PIC-NEXT: L45$pb: +; DARWIN-32-PIC: call L44$pb +; DARWIN-32-PIC-NEXT: L44$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L45$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L45$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L44$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L44$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3339,12 +3339,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off06: -; DARWIN-32-PIC: call L46$pb -; DARWIN-32-PIC-NEXT: L46$pb: +; DARWIN-32-PIC: call L45$pb +; DARWIN-32-PIC-NEXT: L45$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L46$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L46$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L45$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L45$pb)+64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off06: @@ -3411,12 +3411,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off07: -; DARWIN-32-PIC: call L47$pb -; DARWIN-32-PIC-NEXT: L47$pb: +; DARWIN-32-PIC: call L46$pb +; DARWIN-32-PIC-NEXT: L46$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L47$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L47$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L46$pb)+64(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L46$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off07: @@ -3489,12 +3489,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off08: -; DARWIN-32-PIC: call L48$pb -; DARWIN-32-PIC-NEXT: L48$pb: +; DARWIN-32-PIC: call L47$pb +; DARWIN-32-PIC-NEXT: L47$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L48$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L48$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L47$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L47$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3560,12 +3560,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo00: -; DARWIN-32-PIC: call L49$pb -; DARWIN-32-PIC-NEXT: L49$pb: +; DARWIN-32-PIC: call L48$pb +; DARWIN-32-PIC-NEXT: L48$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L49$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L48$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L49$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L48$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3626,12 +3626,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo01: -; DARWIN-32-PIC: call L50$pb -; DARWIN-32-PIC-NEXT: L50$pb: +; DARWIN-32-PIC: call L49$pb +; DARWIN-32-PIC-NEXT: L49$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl $262144, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L50$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L49$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L49$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3705,12 +3705,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo02: -; DARWIN-32-PIC: call L51$pb -; DARWIN-32-PIC-NEXT: L51$pb: +; DARWIN-32-PIC: call L50$pb +; DARWIN-32-PIC-NEXT: L50$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L51$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L50$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L51$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3778,11 +3778,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo03: -; DARWIN-32-PIC: call L52$pb -; DARWIN-32-PIC-NEXT: L52$pb: +; DARWIN-32-PIC: call L51$pb +; DARWIN-32-PIC-NEXT: L51$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L52$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L52$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L51$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L51$pb)+262144(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo03: @@ -3833,11 +3833,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo04: -; DARWIN-32-PIC: call L53$pb -; DARWIN-32-PIC-NEXT: L53$pb: +; DARWIN-32-PIC: call L52$pb +; DARWIN-32-PIC-NEXT: L52$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L53$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L53$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L52$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L52$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo04: @@ -3902,11 +3902,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo05: -; DARWIN-32-PIC: call L54$pb -; DARWIN-32-PIC-NEXT: L54$pb: +; DARWIN-32-PIC: call L53$pb +; DARWIN-32-PIC-NEXT: L53$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L54$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L54$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L53$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L53$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3965,11 +3965,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo06: -; DARWIN-32-PIC: call L55$pb -; DARWIN-32-PIC-NEXT: L55$pb: +; DARWIN-32-PIC: call L54$pb +; DARWIN-32-PIC-NEXT: L54$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L55$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L55$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L54$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L54$pb)+262144(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo06: @@ -4018,11 +4018,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo07: -; DARWIN-32-PIC: call L56$pb -; DARWIN-32-PIC-NEXT: L56$pb: +; DARWIN-32-PIC: call L55$pb +; DARWIN-32-PIC-NEXT: L55$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L56$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L56$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L55$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L55$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo07: @@ -4085,11 +4085,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo08: -; DARWIN-32-PIC: call L57$pb -; DARWIN-32-PIC-NEXT: L57$pb: +; DARWIN-32-PIC: call L56$pb +; DARWIN-32-PIC-NEXT: L56$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L57$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L57$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L56$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L56$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -4159,13 +4159,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big00: -; DARWIN-32-PIC: call L58$pb -; DARWIN-32-PIC-NEXT: L58$pb: +; DARWIN-32-PIC: call L57$pb +; DARWIN-32-PIC-NEXT: L57$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L58$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L57$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L57$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4236,13 +4236,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big01: -; DARWIN-32-PIC: call L59$pb -; DARWIN-32-PIC-NEXT: L59$pb: +; DARWIN-32-PIC: call L58$pb +; DARWIN-32-PIC-NEXT: L58$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L59$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L58$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -4322,13 +4322,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big02: -; DARWIN-32-PIC: call L60$pb -; DARWIN-32-PIC-NEXT: L60$pb: +; DARWIN-32-PIC: call L59$pb +; DARWIN-32-PIC-NEXT: L59$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L60$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L59$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L60$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4403,12 +4403,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big03: -; DARWIN-32-PIC: call L61$pb -; DARWIN-32-PIC-NEXT: L61$pb: +; DARWIN-32-PIC: call L60$pb +; DARWIN-32-PIC-NEXT: L60$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L61$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L61$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L60$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L60$pb)+262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big03: @@ -4476,12 +4476,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big04: -; DARWIN-32-PIC: call L62$pb -; DARWIN-32-PIC-NEXT: L62$pb: +; DARWIN-32-PIC: call L61$pb +; DARWIN-32-PIC-NEXT: L61$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L62$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L62$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L61$pb)+262144(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L61$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big04: @@ -4555,12 +4555,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big05: -; DARWIN-32-PIC: call L63$pb -; DARWIN-32-PIC-NEXT: L63$pb: +; DARWIN-32-PIC: call L62$pb +; DARWIN-32-PIC-NEXT: L62$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L63$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L63$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L62$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L62$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4631,12 +4631,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big06: -; DARWIN-32-PIC: call L64$pb -; DARWIN-32-PIC-NEXT: L64$pb: +; DARWIN-32-PIC: call L63$pb +; DARWIN-32-PIC-NEXT: L63$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L64$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L64$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L63$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L63$pb)+262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big06: @@ -4703,12 +4703,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big07: -; DARWIN-32-PIC: call L65$pb -; DARWIN-32-PIC-NEXT: L65$pb: +; DARWIN-32-PIC: call L64$pb +; DARWIN-32-PIC-NEXT: L64$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L65$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L65$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L64$pb)+262144(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L64$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big07: @@ -4781,12 +4781,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big08: -; DARWIN-32-PIC: call L66$pb -; DARWIN-32-PIC-NEXT: L66$pb: +; DARWIN-32-PIC: call L65$pb +; DARWIN-32-PIC-NEXT: L65$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L66$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L66$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L65$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L65$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4840,10 +4840,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar00: -; DARWIN-32-PIC: call L67$pb -; DARWIN-32-PIC-NEXT: L67$pb: +; DARWIN-32-PIC: call L66$pb +; DARWIN-32-PIC-NEXT: L66$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L67$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L66$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar00: @@ -4887,10 +4887,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxr00: -; DARWIN-32-PIC: call L68$pb -; DARWIN-32-PIC-NEXT: L68$pb: +; DARWIN-32-PIC: call L67$pb +; DARWIN-32-PIC-NEXT: L67$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L68$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L67$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr00: @@ -4934,10 +4934,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar01: -; DARWIN-32-PIC: call L69$pb -; DARWIN-32-PIC-NEXT: L69$pb: +; DARWIN-32-PIC: call L68$pb +; DARWIN-32-PIC-NEXT: L68$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L69$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L68$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar01: @@ -4981,10 +4981,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxr01: -; DARWIN-32-PIC: call L70$pb -; DARWIN-32-PIC-NEXT: L70$pb: +; DARWIN-32-PIC: call L69$pb +; DARWIN-32-PIC-NEXT: L69$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L70$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L69$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr01: @@ -5028,10 +5028,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar02: -; DARWIN-32-PIC: call L71$pb -; DARWIN-32-PIC-NEXT: L71$pb: +; DARWIN-32-PIC: call L70$pb +; DARWIN-32-PIC-NEXT: L70$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L71$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L70$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar02: @@ -5075,10 +5075,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar03: -; DARWIN-32-PIC: call L72$pb -; DARWIN-32-PIC-NEXT: L72$pb: +; DARWIN-32-PIC: call L71$pb +; DARWIN-32-PIC-NEXT: L71$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L72$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dsrc-L71$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar03: @@ -5122,10 +5122,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar04: -; DARWIN-32-PIC: call L73$pb -; DARWIN-32-PIC-NEXT: L73$pb: +; DARWIN-32-PIC: call L72$pb +; DARWIN-32-PIC-NEXT: L72$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L73$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ddst-L72$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar04: @@ -5169,10 +5169,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar05: -; DARWIN-32-PIC: call L74$pb -; DARWIN-32-PIC-NEXT: L74$pb: +; DARWIN-32-PIC: call L73$pb +; DARWIN-32-PIC-NEXT: L73$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dptr-L74$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dptr-L73$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar05: @@ -5216,10 +5216,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar06: -; DARWIN-32-PIC: call L75$pb -; DARWIN-32-PIC-NEXT: L75$pb: +; DARWIN-32-PIC: call L74$pb +; DARWIN-32-PIC-NEXT: L74$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L75$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lsrc-L74$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar06: @@ -5263,10 +5263,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar07: -; DARWIN-32-PIC: call L76$pb -; DARWIN-32-PIC-NEXT: L76$pb: +; DARWIN-32-PIC: call L75$pb +; DARWIN-32-PIC-NEXT: L75$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L76$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ldst-L75$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar07: @@ -5310,10 +5310,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar08: -; DARWIN-32-PIC: call L77$pb -; DARWIN-32-PIC-NEXT: L77$pb: +; DARWIN-32-PIC: call L76$pb +; DARWIN-32-PIC-NEXT: L76$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lptr-L77$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lptr-L76$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar08: @@ -5357,10 +5357,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har00: -; DARWIN-32-PIC: call L78$pb -; DARWIN-32-PIC-NEXT: L78$pb: +; DARWIN-32-PIC: call L77$pb +; DARWIN-32-PIC-NEXT: L77$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L78$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L77$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har00: @@ -5404,10 +5404,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _hxr00: -; DARWIN-32-PIC: call L79$pb -; DARWIN-32-PIC-NEXT: L79$pb: +; DARWIN-32-PIC: call L78$pb +; DARWIN-32-PIC-NEXT: L78$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L79$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L78$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr00: @@ -5451,10 +5451,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har01: -; DARWIN-32-PIC: call L80$pb -; DARWIN-32-PIC-NEXT: L80$pb: +; DARWIN-32-PIC: call L79$pb +; DARWIN-32-PIC-NEXT: L79$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L80$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L79$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har01: @@ -5498,10 +5498,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _hxr01: -; DARWIN-32-PIC: call L81$pb -; DARWIN-32-PIC-NEXT: L81$pb: +; DARWIN-32-PIC: call L80$pb +; DARWIN-32-PIC-NEXT: L80$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L81$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L80$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr01: @@ -5549,10 +5549,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har02: -; DARWIN-32-PIC: call L82$pb -; DARWIN-32-PIC-NEXT: L82$pb: +; DARWIN-32-PIC: call L81$pb +; DARWIN-32-PIC-NEXT: L81$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L82$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L81$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: ret @@ -5600,10 +5600,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har03: -; DARWIN-32-PIC: call L83$pb -; DARWIN-32-PIC-NEXT: L83$pb: +; DARWIN-32-PIC: call L82$pb +; DARWIN-32-PIC-NEXT: L82$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L83$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dsrc-L82$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har03: @@ -5647,10 +5647,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har04: -; DARWIN-32-PIC: call L84$pb -; DARWIN-32-PIC-NEXT: L84$pb: +; DARWIN-32-PIC: call L83$pb +; DARWIN-32-PIC-NEXT: L83$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L84$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ddst-L83$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har04: @@ -5697,10 +5697,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har05: -; DARWIN-32-PIC: call L85$pb -; DARWIN-32-PIC-NEXT: L85$pb: +; DARWIN-32-PIC: call L84$pb +; DARWIN-32-PIC-NEXT: L84$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L85$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L84$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har05: @@ -5744,10 +5744,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har06: -; DARWIN-32-PIC: call L86$pb -; DARWIN-32-PIC-NEXT: L86$pb: +; DARWIN-32-PIC: call L85$pb +; DARWIN-32-PIC-NEXT: L85$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L86$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lsrc-L85$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har06: @@ -5791,10 +5791,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har07: -; DARWIN-32-PIC: call L87$pb -; DARWIN-32-PIC-NEXT: L87$pb: +; DARWIN-32-PIC: call L86$pb +; DARWIN-32-PIC-NEXT: L86$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L87$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ldst-L86$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har07: @@ -5840,10 +5840,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har08: -; DARWIN-32-PIC: call L88$pb -; DARWIN-32-PIC-NEXT: L88$pb: +; DARWIN-32-PIC: call L87$pb +; DARWIN-32-PIC-NEXT: L87$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L88$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L87$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har08: @@ -5889,10 +5889,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat00: -; DARWIN-32-PIC: call L89$pb -; DARWIN-32-PIC-NEXT: L89$pb: +; DARWIN-32-PIC: call L88$pb +; DARWIN-32-PIC-NEXT: L88$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L89$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L88$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5942,10 +5942,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxt00: -; DARWIN-32-PIC: call L90$pb -; DARWIN-32-PIC-NEXT: L90$pb: +; DARWIN-32-PIC: call L89$pb +; DARWIN-32-PIC-NEXT: L89$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L90$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L89$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5995,10 +5995,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat01: -; DARWIN-32-PIC: call L91$pb -; DARWIN-32-PIC-NEXT: L91$pb: +; DARWIN-32-PIC: call L90$pb +; DARWIN-32-PIC-NEXT: L90$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L91$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L90$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6048,10 +6048,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxt01: -; DARWIN-32-PIC: call L92$pb -; DARWIN-32-PIC-NEXT: L92$pb: +; DARWIN-32-PIC: call L91$pb +; DARWIN-32-PIC-NEXT: L91$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L92$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L91$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6110,10 +6110,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat02: -; DARWIN-32-PIC: call L93$pb -; DARWIN-32-PIC-NEXT: L93$pb: +; DARWIN-32-PIC: call L92$pb +; DARWIN-32-PIC-NEXT: L92$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L93$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L92$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6166,10 +6166,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat03: -; DARWIN-32-PIC: call L94$pb -; DARWIN-32-PIC-NEXT: L94$pb: +; DARWIN-32-PIC: call L93$pb +; DARWIN-32-PIC-NEXT: L93$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L94$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L93$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat03: @@ -6214,10 +6214,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat04: -; DARWIN-32-PIC: call L95$pb -; DARWIN-32-PIC-NEXT: L95$pb: +; DARWIN-32-PIC: call L94$pb +; DARWIN-32-PIC-NEXT: L94$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L95$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L94$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat04: @@ -6271,10 +6271,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat05: -; DARWIN-32-PIC: call L96$pb -; DARWIN-32-PIC-NEXT: L96$pb: +; DARWIN-32-PIC: call L95$pb +; DARWIN-32-PIC-NEXT: L95$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L96$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L95$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6322,10 +6322,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat06: -; DARWIN-32-PIC: call L97$pb -; DARWIN-32-PIC-NEXT: L97$pb: +; DARWIN-32-PIC: call L96$pb +; DARWIN-32-PIC-NEXT: L96$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L97$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L96$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat06: @@ -6369,10 +6369,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat07: -; DARWIN-32-PIC: call L98$pb -; DARWIN-32-PIC-NEXT: L98$pb: +; DARWIN-32-PIC: call L97$pb +; DARWIN-32-PIC-NEXT: L97$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L98$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L97$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat07: @@ -6425,10 +6425,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat08: -; DARWIN-32-PIC: call L99$pb -; DARWIN-32-PIC-NEXT: L99$pb: +; DARWIN-32-PIC: call L98$pb +; DARWIN-32-PIC-NEXT: L98$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L99$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L98$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6478,11 +6478,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam00: -; DARWIN-32-PIC: call L100$pb -; DARWIN-32-PIC-NEXT: L100$pb: +; DARWIN-32-PIC: call L99$pb +; DARWIN-32-PIC-NEXT: L99$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L100$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L99$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam00: @@ -6531,11 +6531,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam01: -; DARWIN-32-PIC: call L101$pb -; DARWIN-32-PIC-NEXT: L101$pb: +; DARWIN-32-PIC: call L100$pb +; DARWIN-32-PIC-NEXT: L100$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L101$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L100$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam01: @@ -6584,11 +6584,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxm01: -; DARWIN-32-PIC: call L102$pb -; DARWIN-32-PIC-NEXT: L102$pb: +; DARWIN-32-PIC: call L101$pb +; DARWIN-32-PIC-NEXT: L101$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L102$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L101$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxm01: @@ -6646,10 +6646,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam02: -; DARWIN-32-PIC: call L103$pb -; DARWIN-32-PIC-NEXT: L103$pb: +; DARWIN-32-PIC: call L102$pb +; DARWIN-32-PIC-NEXT: L102$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L103$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L102$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax ; DARWIN-32-PIC-NEXT: addl (%ecx), %eax ; DARWIN-32-PIC-NEXT: ret @@ -6702,10 +6702,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam03: -; DARWIN-32-PIC: call L104$pb -; DARWIN-32-PIC-NEXT: L104$pb: +; DARWIN-32-PIC: call L103$pb +; DARWIN-32-PIC-NEXT: L103$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L104$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L103$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam03: @@ -6750,10 +6750,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam04: -; DARWIN-32-PIC: call L105$pb -; DARWIN-32-PIC-NEXT: L105$pb: +; DARWIN-32-PIC: call L104$pb +; DARWIN-32-PIC-NEXT: L104$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L105$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L104$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam04: @@ -6807,11 +6807,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam05: -; DARWIN-32-PIC: call L106$pb -; DARWIN-32-PIC-NEXT: L106$pb: +; DARWIN-32-PIC: call L105$pb +; DARWIN-32-PIC-NEXT: L105$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _dptr-L106$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _dptr-L105$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam05: @@ -6858,10 +6858,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam06: -; DARWIN-32-PIC: call L107$pb -; DARWIN-32-PIC-NEXT: L107$pb: +; DARWIN-32-PIC: call L106$pb +; DARWIN-32-PIC-NEXT: L106$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L107$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L106$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam06: @@ -6905,10 +6905,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam07: -; DARWIN-32-PIC: call L108$pb -; DARWIN-32-PIC-NEXT: L108$pb: +; DARWIN-32-PIC: call L107$pb +; DARWIN-32-PIC-NEXT: L107$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L108$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L107$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam07: @@ -6961,11 +6961,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam08: -; DARWIN-32-PIC: call L109$pb -; DARWIN-32-PIC-NEXT: L109$pb: +; DARWIN-32-PIC: call L108$pb +; DARWIN-32-PIC-NEXT: L108$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _lptr-L109$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _lptr-L108$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam08: @@ -7021,11 +7021,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat00: -; DARWIN-32-PIC: call L110$pb -; DARWIN-32-PIC-NEXT: L110$pb: +; DARWIN-32-PIC: call L109$pb +; DARWIN-32-PIC-NEXT: L109$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L110$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L109$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7082,11 +7082,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt00: -; DARWIN-32-PIC: call L111$pb -; DARWIN-32-PIC-NEXT: L111$pb: +; DARWIN-32-PIC: call L110$pb +; DARWIN-32-PIC-NEXT: L110$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L111$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L110$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7143,11 +7143,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat01: -; DARWIN-32-PIC: call L112$pb -; DARWIN-32-PIC-NEXT: L112$pb: +; DARWIN-32-PIC: call L111$pb +; DARWIN-32-PIC-NEXT: L111$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L112$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L111$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7204,11 +7204,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt01: -; DARWIN-32-PIC: call L113$pb -; DARWIN-32-PIC-NEXT: L113$pb: +; DARWIN-32-PIC: call L112$pb +; DARWIN-32-PIC-NEXT: L112$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L113$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L112$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7272,10 +7272,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat02: -; DARWIN-32-PIC: call L114$pb -; DARWIN-32-PIC-NEXT: L114$pb: +; DARWIN-32-PIC: call L113$pb +; DARWIN-32-PIC-NEXT: L113$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L114$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L113$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax @@ -7336,11 +7336,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat03: -; DARWIN-32-PIC: call L115$pb -; DARWIN-32-PIC-NEXT: L115$pb: +; DARWIN-32-PIC: call L114$pb +; DARWIN-32-PIC-NEXT: L114$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L115$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L114$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat03: @@ -7395,11 +7395,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat04: -; DARWIN-32-PIC: call L116$pb -; DARWIN-32-PIC-NEXT: L116$pb: +; DARWIN-32-PIC: call L115$pb +; DARWIN-32-PIC-NEXT: L115$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L116$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L115$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat04: @@ -7461,11 +7461,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat05: -; DARWIN-32-PIC: call L117$pb -; DARWIN-32-PIC-NEXT: L117$pb: +; DARWIN-32-PIC: call L116$pb +; DARWIN-32-PIC-NEXT: L116$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L117$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L116$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7521,11 +7521,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat06: -; DARWIN-32-PIC: call L118$pb -; DARWIN-32-PIC-NEXT: L118$pb: +; DARWIN-32-PIC: call L117$pb +; DARWIN-32-PIC-NEXT: L117$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L118$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L117$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat06: @@ -7580,11 +7580,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat07: -; DARWIN-32-PIC: call L119$pb -; DARWIN-32-PIC-NEXT: L119$pb: +; DARWIN-32-PIC: call L118$pb +; DARWIN-32-PIC-NEXT: L118$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L119$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L118$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat07: @@ -7645,11 +7645,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat08: -; DARWIN-32-PIC: call L120$pb -; DARWIN-32-PIC-NEXT: L120$pb: +; DARWIN-32-PIC: call L119$pb +; DARWIN-32-PIC-NEXT: L119$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L120$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L119$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7706,11 +7706,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam00: -; DARWIN-32-PIC: call L121$pb -; DARWIN-32-PIC-NEXT: L121$pb: +; DARWIN-32-PIC: call L120$pb +; DARWIN-32-PIC-NEXT: L120$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L121$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L120$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7767,11 +7767,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm00: -; DARWIN-32-PIC: call L122$pb -; DARWIN-32-PIC-NEXT: L122$pb: +; DARWIN-32-PIC: call L121$pb +; DARWIN-32-PIC-NEXT: L121$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L122$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L121$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7828,11 +7828,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam01: -; DARWIN-32-PIC: call L123$pb -; DARWIN-32-PIC-NEXT: L123$pb: +; DARWIN-32-PIC: call L122$pb +; DARWIN-32-PIC-NEXT: L122$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L123$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L122$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7889,11 +7889,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm01: -; DARWIN-32-PIC: call L124$pb -; DARWIN-32-PIC-NEXT: L124$pb: +; DARWIN-32-PIC: call L123$pb +; DARWIN-32-PIC-NEXT: L123$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L124$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L123$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7957,10 +7957,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam02: -; DARWIN-32-PIC: call L125$pb -; DARWIN-32-PIC-NEXT: L125$pb: +; DARWIN-32-PIC: call L124$pb +; DARWIN-32-PIC-NEXT: L124$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L125$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L124$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax @@ -8021,11 +8021,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam03: -; DARWIN-32-PIC: call L126$pb -; DARWIN-32-PIC-NEXT: L126$pb: +; DARWIN-32-PIC: call L125$pb +; DARWIN-32-PIC-NEXT: L125$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L126$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L125$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam03: @@ -8080,11 +8080,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam04: -; DARWIN-32-PIC: call L127$pb -; DARWIN-32-PIC-NEXT: L127$pb: +; DARWIN-32-PIC: call L126$pb +; DARWIN-32-PIC-NEXT: L126$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L127$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L126$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam04: @@ -8146,11 +8146,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam05: -; DARWIN-32-PIC: call L128$pb -; DARWIN-32-PIC-NEXT: L128$pb: +; DARWIN-32-PIC: call L127$pb +; DARWIN-32-PIC-NEXT: L127$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L128$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L127$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -8206,11 +8206,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam06: -; DARWIN-32-PIC: call L129$pb -; DARWIN-32-PIC-NEXT: L129$pb: +; DARWIN-32-PIC: call L128$pb +; DARWIN-32-PIC-NEXT: L128$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L129$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L128$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam06: @@ -8265,11 +8265,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam07: -; DARWIN-32-PIC: call L130$pb -; DARWIN-32-PIC-NEXT: L130$pb: +; DARWIN-32-PIC: call L129$pb +; DARWIN-32-PIC-NEXT: L129$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L130$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L129$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam07: @@ -8330,11 +8330,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam08: -; DARWIN-32-PIC: call L131$pb -; DARWIN-32-PIC-NEXT: L131$pb: +; DARWIN-32-PIC: call L130$pb +; DARWIN-32-PIC-NEXT: L130$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L131$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L130$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -8644,10 +8644,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _address: -; DARWIN-32-PIC: call L134$pb -; DARWIN-32-PIC-NEXT: L134$pb: +; DARWIN-32-PIC: call L133$pb +; DARWIN-32-PIC-NEXT: L133$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L134$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L133$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _address: @@ -8693,10 +8693,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _laddress: -; DARWIN-32-PIC: call L135$pb -; DARWIN-32-PIC-NEXT: L135$pb: +; DARWIN-32-PIC: call L134$pb +; DARWIN-32-PIC-NEXT: L134$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lcallee-L135$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lcallee-L134$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _laddress: @@ -8740,10 +8740,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _daddress: -; DARWIN-32-PIC: call L136$pb -; DARWIN-32-PIC-NEXT: L136$pb: +; DARWIN-32-PIC: call L135$pb +; DARWIN-32-PIC-NEXT: L135$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dcallee-L136$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dcallee-L135$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _daddress: @@ -9224,10 +9224,10 @@ entry: ; DARWIN-32-PIC: _icaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L143$pb -; DARWIN-32-PIC-NEXT: L143$pb: +; DARWIN-32-PIC-NEXT: call L142$pb +; DARWIN-32-PIC-NEXT: L142$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L143$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L142$pb(%eax), %esi ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9310,11 +9310,11 @@ entry: ; DARWIN-32-PIC: _dicaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L144$pb -; DARWIN-32-PIC-NEXT: L144$pb: +; DARWIN-32-PIC-NEXT: call L143$pb +; DARWIN-32-PIC-NEXT: L143$pb: ; DARWIN-32-PIC-NEXT: popl %esi -; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi) -; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_difunc-L143$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_difunc-L143$pb(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp ; DARWIN-32-PIC-NEXT: popl %esi ; DARWIN-32-PIC-NEXT: ret @@ -9391,11 +9391,11 @@ entry: ; DARWIN-32-PIC: _licaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L145$pb -; DARWIN-32-PIC-NEXT: L145$pb: +; DARWIN-32-PIC-NEXT: call L144$pb +; DARWIN-32-PIC-NEXT: L144$pb: ; DARWIN-32-PIC-NEXT: popl %esi -; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi) -; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_lifunc-L144$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_lifunc-L144$pb(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp ; DARWIN-32-PIC-NEXT: popl %esi ; DARWIN-32-PIC-NEXT: ret @@ -9476,10 +9476,10 @@ entry: ; DARWIN-32-PIC: _itailcaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L146$pb -; DARWIN-32-PIC-NEXT: L146$pb: +; DARWIN-32-PIC-NEXT: call L145$pb +; DARWIN-32-PIC-NEXT: L145$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L146$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L145$pb(%eax), %esi ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9553,10 +9553,10 @@ entry: ; DARWIN-32-PIC: _ditailcaller: ; DARWIN-32-PIC: subl $12, %esp -; DARWIN-32-PIC-NEXT: call L147$pb -; DARWIN-32-PIC-NEXT: L147$pb: +; DARWIN-32-PIC-NEXT: call L146$pb +; DARWIN-32-PIC-NEXT: L146$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: call *_difunc-L147$pb(%eax) +; DARWIN-32-PIC-NEXT: call *_difunc-L146$pb(%eax) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret @@ -9619,10 +9619,10 @@ entry: ; DARWIN-32-PIC: _litailcaller: ; DARWIN-32-PIC: subl $12, %esp -; DARWIN-32-PIC-NEXT: call L148$pb -; DARWIN-32-PIC-NEXT: L148$pb: +; DARWIN-32-PIC-NEXT: call L147$pb +; DARWIN-32-PIC-NEXT: L147$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: call *_lifunc-L148$pb(%eax) +; DARWIN-32-PIC-NEXT: call *_lifunc-L147$pb(%eax) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll index 3020eb3..3ed3bd6 100644 --- a/test/CodeGen/X86/aliases.ll +++ b/test/CodeGen/X86/aliases.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t -; RUN: grep { = } %t | count 7 -; RUN: grep set %t | count 16 +; RUN: grep { = } %t | count 16 +; RUN: grep set %t | count 18 ; RUN: grep globl %t | count 6 ; RUN: grep weak %t | count 1 ; RUN: grep hidden %t | count 1 diff --git a/test/CodeGen/X86/alignment.ll b/test/CodeGen/X86/alignment.ll new file mode 100644 index 0000000..06a4f3f --- /dev/null +++ b/test/CodeGen/X86/alignment.ll @@ -0,0 +1,18 @@ +; RUN: llc %s -o - -mtriple=x86_64-linux-gnu | FileCheck %s + +; This cannot get rounded up to the preferred alignment (16) if they have an +; explicit alignment specified. +@GlobalA = global { [384 x i8] } zeroinitializer, align 8 + +; CHECK: .bss +; CHECK: .globl GlobalA +; CHECK: .align 8 +; CHECK: GlobalA: +; CHECK: .zero 384 + +; Common variables should not get rounded up to the preferred alignment (16) if +; they have an explicit alignment specified. +; PR6921 +@GlobalB = common global { [384 x i8] } zeroinitializer, align 8 + +; CHECK: .comm GlobalB,384,8
\ No newline at end of file diff --git a/test/CodeGen/X86/avoid-loop-align.ll b/test/CodeGen/X86/avoid-loop-align.ll index d4c5c67..7957db7 100644 --- a/test/CodeGen/X86/avoid-loop-align.ll +++ b/test/CodeGen/X86/avoid-loop-align.ll @@ -3,9 +3,9 @@ ; CodeGen should align the top of the loop, which differs from the loop ; header in this case. -; CHECK: jmp LBB1_2 +; CHECK: jmp LBB0_2 ; CHECK: .align -; CHECK: LBB1_1: +; CHECK: LBB0_1: @A = common global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll index 130483a..5cdc100 100644 --- a/test/CodeGen/X86/brcond.ll +++ b/test/CodeGen/X86/brcond.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=core2 | FileCheck %s ; rdar://7475489 define i32 @test1(i32 %a, i32 %b) nounwind ssp { @@ -46,7 +46,7 @@ return: ; preds = %entry ; CHECK: test2: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax -; CHECK-NEXT: jne LBB2_2 +; CHECK-NEXT: jne LBB1_2 } ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 @@ -65,5 +65,44 @@ return: ; preds = %entry ; CHECK: test3: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax -; CHECK-NEXT: je LBB3_2 +; CHECK-NEXT: je LBB2_2 +} + +; <rdar://problem/7598384>: +; +; jCC L1 +; jmp L2 +; L1: +; ... +; L2: +; ... +; +; to: +; +; jnCC L2 +; L1: +; ... +; L2: +; ... +define float @test4(float %x, float %y) nounwind readnone optsize ssp { +entry: + %0 = fpext float %x to double ; <double> [#uses=1] + %1 = fpext float %y to double ; <double> [#uses=1] + %2 = fmul double %0, %1 ; <double> [#uses=3] + %3 = fcmp oeq double %2, 0.000000e+00 ; <i1> [#uses=1] + br i1 %3, label %bb2, label %bb1 + +; CHECK: jne +; CHECK-NEXT: jnp +; CHECK-NOT: jmp +; CHECK: LBB + +bb1: ; preds = %entry + %4 = fadd double %2, -1.000000e+00 ; <double> [#uses=1] + br label %bb2 + +bb2: ; preds = %entry, %bb1 + %.0.in = phi double [ %4, %bb1 ], [ %2, %entry ] ; <double> [#uses=1] + %.0 = fptrunc double %.0.in to float ; <float> [#uses=1] + ret float %.0 } diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll index 0da93ba..686ed9c 100644 --- a/test/CodeGen/X86/byval7.ll +++ b/test/CodeGen/X86/byval7.ll @@ -1,10 +1,17 @@ -; RUN: llc < %s -march=x86 -mcpu=yonah | egrep {add|lea} | grep 16 +; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s %struct.S = type { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, + <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } define i32 @main() nounwind { entry: +; CHECK: main: +; CHECK: movl $1, (%esp) +; CHECK: leal 16(%esp), %edi +; CHECK: movl $36, %ecx +; CHECK: leal 160(%esp), %esi +; CHECK: rep;movsl %s = alloca %struct.S ; <%struct.S*> [#uses=2] %tmp15 = getelementptr %struct.S* %s, i32 0, i32 0 ; <<2 x i64>*> [#uses=1] store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16 diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll index 3f27187..623ac75 100644 --- a/test/CodeGen/X86/clz.ll +++ b/test/CodeGen/X86/clz.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=x86 | grep bsr | count 2 -; RUN: llc < %s -march=x86 | grep bsf -; RUN: llc < %s -march=x86 | grep cmov | count 3 +; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s define i32 @t1(i32 %x) nounwind { %tmp = tail call i32 @llvm.ctlz.i32( i32 %x ) ret i32 %tmp +; CHECK: t1: +; CHECK: bsrl +; CHECK: cmov } declare i32 @llvm.ctlz.i32(i32) nounwind readnone @@ -12,6 +13,9 @@ declare i32 @llvm.ctlz.i32(i32) nounwind readnone define i32 @t2(i32 %x) nounwind { %tmp = tail call i32 @llvm.cttz.i32( i32 %x ) ret i32 %tmp +; CHECK: t2: +; CHECK: bsfl +; CHECK: cmov } declare i32 @llvm.cttz.i32(i32) nounwind readnone @@ -21,6 +25,9 @@ entry: %tmp1 = add i16 %x, %y %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1 ) ; <i16> [#uses=1] ret i16 %tmp2 +; CHECK: t3: +; CHECK: bsrw +; CHECK: cmov } declare i16 @llvm.ctlz.i16(i16) nounwind readnone diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll index 0fe4e56..e0f2796 100644 --- a/test/CodeGen/X86/coalesce-esp.ll +++ b/test/CodeGen/X86/coalesce-esp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {movl %esp, %eax} +; RUN: llc < %s | grep {movl %esp, %ecx} ; PR4572 ; Don't coalesce with %esp if it would end up putting %esp in diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll index ca8cc14..665984c 100644 --- a/test/CodeGen/X86/const-select.ll +++ b/test/CodeGen/X86/const-select.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin7" -; RUN: llc < %s | grep {LCPI1_0(,%eax,4)} +; RUN: llc < %s | grep {LCPI0_0(,%eax,4)} define float @f(i32 %x) nounwind readnone { entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/constant-pool-sharing.ll b/test/CodeGen/X86/constant-pool-sharing.ll index c3e97ad..33de576 100644 --- a/test/CodeGen/X86/constant-pool-sharing.ll +++ b/test/CodeGen/X86/constant-pool-sharing.ll @@ -3,7 +3,7 @@ ; llc should share constant pool entries between this integer vector ; and this floating-point vector since they have the same encoding. -; CHECK: LCPI1_0(%rip), %xmm0 +; CHECK: LCPI0_0(%rip), %xmm0 ; CHECK: movaps %xmm0, (%rdi) ; CHECK: movaps %xmm0, (%rsi) diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 1e13046..2f27f35 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -18,3 +18,115 @@ entry: volatile store i32 %conv19.i, i32* undef ret i32 undef } + +; PR6533 +define void @test2(i1 %x, i32 %y) nounwind { + %land.ext = zext i1 %x to i32 ; <i32> [#uses=1] + %and = and i32 %y, 1 ; <i32> [#uses=1] + %xor = xor i32 %and, %land.ext ; <i32> [#uses=1] + %cmp = icmp eq i32 %xor, 1 ; <i1> [#uses=1] + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %land.end + ret void + +if.end: ; preds = %land.end + ret void +} + +; PR6577 +%pair = type { i64, double } + +define void @test3() { +dependentGraph243.exit: + %subject19 = load %pair* undef ; <%1> [#uses=1] + %0 = extractvalue %pair %subject19, 1 ; <double> [#uses=2] + %1 = select i1 undef, double %0, double undef ; <double> [#uses=1] + %2 = select i1 undef, double %1, double %0 ; <double> [#uses=1] + %3 = insertvalue %pair undef, double %2, 1 ; <%1> [#uses=1] + store %pair %3, %pair* undef + ret void +} + +; PR6605 +define i64 @test4(i8* %P) nounwind ssp { +entry: + %tmp1 = load i8* %P ; <i8> [#uses=3] + %tobool = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1] + %tmp58 = sext i1 %tobool to i8 ; <i8> [#uses=1] + %mul.i = and i8 %tmp58, %tmp1 ; <i8> [#uses=1] + %conv6 = zext i8 %mul.i to i32 ; <i32> [#uses=1] + %cmp = icmp ne i8 %tmp1, 1 ; <i1> [#uses=1] + %conv11 = zext i1 %cmp to i32 ; <i32> [#uses=1] + %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1] + %and = and i32 %conv6, %call12 ; <i32> [#uses=1] + %tobool13 = icmp eq i32 %and, 0 ; <i1> [#uses=1] + br i1 %tobool13, label %if.else, label %return + +if.else: ; preds = %entry + br label %return + +return: ; preds = %if.else, %entry + ret i64 undef +} + +declare i32 @safe(i32) + +; PR6607 +define fastcc void @test5(i32 %FUNC) nounwind { +foo: + %0 = load i8* undef, align 1 ; <i8> [#uses=3] + %1 = sext i8 %0 to i32 ; <i32> [#uses=2] + %2 = zext i8 %0 to i32 ; <i32> [#uses=1] + %tmp1.i5037 = urem i32 %2, 10 ; <i32> [#uses=1] + %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15 ; <i1> [#uses=1] + %3 = zext i1 %tmp.i5038 to i8 ; <i8> [#uses=1] + %4 = icmp slt i8 %0, %3 ; <i1> [#uses=1] + %5 = add nsw i32 %1, 256 ; <i32> [#uses=1] + %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1] + %6 = shl i32 %storemerge.i.i57, 16 ; <i32> [#uses=1] + %7 = sdiv i32 %6, -256 ; <i32> [#uses=1] + %8 = trunc i32 %7 to i8 ; <i8> [#uses=1] + store i8 %8, i8* undef, align 1 + ret void +} + + +; Crash commoning identical asms. +; PR6803 +define void @test6(i1 %C) nounwind optsize ssp { +entry: + br i1 %C, label %do.body55, label %do.body92 + +do.body55: ; preds = %if.else36 + call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0 + ret void + +do.body92: ; preds = %if.then66 + call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1 + ret void +} + +!0 = metadata !{i32 633550} +!1 = metadata !{i32 634261} + + +; Crash during XOR optimization. +; <rdar://problem/7869290> + +define void @test7() nounwind ssp { +entry: + br i1 undef, label %bb14, label %bb67 + +bb14: + %tmp0 = trunc i16 undef to i1 + %tmp1 = load i8* undef, align 8 + %tmp2 = shl i8 %tmp1, 4 + %tmp3 = lshr i8 %tmp2, 7 + %tmp4 = trunc i8 %tmp3 to i1 + %tmp5 = icmp ne i1 %tmp0, %tmp4 + br i1 %tmp5, label %bb14, label %bb67 + +bb67: + ret void +} diff --git a/test/CodeGen/X86/dagcombine-buildvector.ll b/test/CodeGen/X86/dagcombine-buildvector.ll index c0ee2ac..5cc6eaa 100644 --- a/test/CodeGen/X86/dagcombine-buildvector.ll +++ b/test/CodeGen/X86/dagcombine-buildvector.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx -o %t -; RUN: grep unpcklpd %t | count 1 -; RUN: grep movapd %t | count 1 -; RUN: grep movaps %t | count 1 +; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s ; Shows a dag combine bug that will generate an illegal build vector ; with v2i64 build_vector i32, i32. +; CHECK: test: +; CHECK: unpcklpd +; CHECK: movapd define void @test(<2 x double>* %dst, <4 x double> %src) nounwind { entry: %tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> < i32 0, i32 2 > @@ -13,6 +13,8 @@ entry: ret void } +; CHECK: test2: +; CHECK: movdqa define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind { entry: %tmp1 = load <4 x i16>* %src diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll index 2c699bf..bdbaac0 100644 --- a/test/CodeGen/X86/dllexport.ll +++ b/test/CodeGen/X86/dllexport.ll @@ -9,4 +9,4 @@ entry: } ; CHECK: .section .drectve -; CHECK: -export:@foo@0
\ No newline at end of file +; CHECK: -export:@foo@0 diff --git a/test/CodeGen/X86/fast-isel-constpool.ll b/test/CodeGen/X86/fast-isel-constpool.ll index 84d10f3..323c853 100644 --- a/test/CodeGen/X86/fast-isel-constpool.ll +++ b/test/CodeGen/X86/fast-isel-constpool.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel | grep {LCPI1_0(%rip)} +; RUN: llc < %s -fast-isel | grep {LCPI0_0(%rip)} ; Make sure fast isel uses rip-relative addressing when required. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin9.0" diff --git a/test/CodeGen/X86/fast-isel-phys.ll b/test/CodeGen/X86/fast-isel-phys.ll deleted file mode 100644 index 158ef55..0000000 --- a/test/CodeGen/X86/fast-isel-phys.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 - -define i8 @t2(i8 %a, i8 %c) nounwind { - %tmp = shl i8 %a, %c - ret i8 %tmp -} - -define i8 @t1(i8 %a) nounwind { - %tmp = mul i8 %a, 17 - ret i8 %tmp -} diff --git a/test/CodeGen/X86/fast-isel-trunc.ll b/test/CodeGen/X86/fast-isel-trunc.ll deleted file mode 100644 index 69b26c5..0000000 --- a/test/CodeGen/X86/fast-isel-trunc.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort -; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort - -define i8 @t1(i32 %x) signext nounwind { - %tmp1 = trunc i32 %x to i8 - ret i8 %tmp1 -} - -define i8 @t2(i16 signext %x) signext nounwind { - %tmp1 = trunc i16 %x to i8 - ret i8 %tmp1 -} diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index 84b3fd7..3d26ae7 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2 +; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 ; This tests very minimal fast-isel functionality. @@ -65,6 +66,26 @@ define i8* @inttoptr_i32(i32 %p) nounwind { ret i8* %t } +define i8 @trunc_i32_i8(i32 %x) signext nounwind { + %tmp1 = trunc i32 %x to i8 + ret i8 %tmp1 +} + +define i8 @trunc_i16_i8(i16 signext %x) signext nounwind { + %tmp1 = trunc i16 %x to i8 + ret i8 %tmp1 +} + +define i8 @shl_i8(i8 %a, i8 %c) nounwind { + %tmp = shl i8 %a, %c + ret i8 %tmp +} + +define i8 @mul_i8(i8 %a) nounwind { + %tmp = mul i8 %a, 17 + ret i8 %tmp +} + define void @store_i1(i1* %p, i1 %t) nounwind { store i1 %t, i1* %p ret void diff --git a/test/CodeGen/X86/field-extract-use-trunc.ll b/test/CodeGen/X86/field-extract-use-trunc.ll index 6020530..735e134 100644 --- a/test/CodeGen/X86/field-extract-use-trunc.ll +++ b/test/CodeGen/X86/field-extract-use-trunc.ll @@ -1,38 +1,38 @@ ; RUN: llc < %s -march=x86 | grep sar | count 1 ; RUN: llc < %s -march=x86-64 | not grep sar -define i32 @test(i32 %f12) { +define i32 @test(i32 %f12) nounwind { %tmp7.25 = lshr i32 %f12, 16 %tmp7.26 = trunc i32 %tmp7.25 to i8 %tmp78.2 = sext i8 %tmp7.26 to i32 ret i32 %tmp78.2 } -define i32 @test2(i32 %f12) { +define i32 @test2(i32 %f12) nounwind { %f11 = shl i32 %f12, 8 %tmp7.25 = ashr i32 %f11, 24 ret i32 %tmp7.25 } -define i32 @test3(i32 %f12) { +define i32 @test3(i32 %f12) nounwind { %f11 = shl i32 %f12, 13 %tmp7.25 = ashr i32 %f11, 24 ret i32 %tmp7.25 } -define i64 @test4(i64 %f12) { +define i64 @test4(i64 %f12) nounwind { %f11 = shl i64 %f12, 32 %tmp7.25 = ashr i64 %f11, 32 ret i64 %tmp7.25 } -define i16 @test5(i16 %f12) { +define i16 @test5(i16 %f12) nounwind { %f11 = shl i16 %f12, 2 %tmp7.25 = ashr i16 %f11, 8 ret i16 %tmp7.25 } -define i16 @test6(i16 %f12) { +define i16 @test6(i16 %f12) nounwind { %f11 = shl i16 %f12, 8 %tmp7.25 = ashr i16 %f11, 8 ret i16 %tmp7.25 diff --git a/test/CodeGen/X86/fold-pcmpeqd-0.ll b/test/CodeGen/X86/fold-pcmpeqd-0.ll index ef5202f..e5be58e 100644 --- a/test/CodeGen/X86/fold-pcmpeqd-0.ll +++ b/test/CodeGen/X86/fold-pcmpeqd-0.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI1_2 | count 2 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI0_2 | count 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 ; This testcase shouldn't need to spill the -1 value, diff --git a/test/CodeGen/X86/fp-elim.ll b/test/CodeGen/X86/fp-elim.ll new file mode 100644 index 0000000..60892a2 --- /dev/null +++ b/test/CodeGen/X86/fp-elim.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=FP-ELIM +; RUN: llc < %s -march=x86 -asm-verbose=false -disable-fp-elim | FileCheck %s -check-prefix=NO-ELIM +; RUN: llc < %s -march=x86 -asm-verbose=false -disable-non-leaf-fp-elim | FileCheck %s -check-prefix=NON-LEAF + +; Implement -momit-leaf-frame-pointer +; rdar://7886181 + +define i32 @t1() nounwind readnone { +entry: +; FP-ELIM: t1: +; FP-ELIM-NEXT: movl +; FP-ELIM-NEXT: ret + +; NO-ELIM: t1: +; NO-ELIM-NEXT: pushl %ebp +; NO-ELIM: popl %ebp +; NO-ELIM-NEXT: ret + +; NON-LEAF: t1: +; NON-LEAF-NEXT: movl +; NON-LEAF-NEXT: ret + ret i32 10 +} + +define void @t2() nounwind { +entry: +; FP-ELIM: t2: +; FP-ELIM-NOT: pushl %ebp +; FP-ELIM: ret + +; NO-ELIM: t2: +; NO-ELIM-NEXT: pushl %ebp +; NO-ELIM: popl %ebp +; NO-ELIM-NEXT: ret + +; NON-LEAF: t2: +; NON-LEAF-NEXT: pushl %ebp +; NON-LEAF: popl %ebp +; NON-LEAF-NEXT: ret + tail call void @foo(i32 0) nounwind + ret void +} + +declare void @foo(i32) diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll new file mode 100644 index 0000000..134ee28 --- /dev/null +++ b/test/CodeGen/X86/gather-addresses.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s +; rdar://7398554 + +; When doing vector gather-scatter index calculation with 32-bit indices, +; bounce the vector off of cache rather than shuffling each individual +; element out of the index vector. + +; CHECK: andps (%rdx), %xmm0 +; CHECK: movaps %xmm0, -24(%rsp) +; CHECK: movslq -24(%rsp), %rax +; CHECK: movsd (%rdi,%rax,8), %xmm0 +; CHECK: movslq -20(%rsp), %rax +; CHECK: movhpd (%rdi,%rax,8), %xmm0 +; CHECK: movslq -16(%rsp), %rax +; CHECK: movsd (%rdi,%rax,8), %xmm1 +; CHECK: movslq -12(%rsp), %rax +; CHECK: movhpd (%rdi,%rax,8), %xmm1 + +define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind { + %a = load <4 x i32>* %i + %b = load <4 x i32>* %h + %j = and <4 x i32> %a, %b + %d0 = extractelement <4 x i32> %j, i32 0 + %d1 = extractelement <4 x i32> %j, i32 1 + %d2 = extractelement <4 x i32> %j, i32 2 + %d3 = extractelement <4 x i32> %j, i32 3 + %q0 = getelementptr double* %p, i32 %d0 + %q1 = getelementptr double* %p, i32 %d1 + %q2 = getelementptr double* %p, i32 %d2 + %q3 = getelementptr double* %p, i32 %d3 + %r0 = load double* %q0 + %r1 = load double* %q1 + %r2 = load double* %q2 + %r3 = load double* %q3 + %v0 = insertelement <4 x double> undef, double %r0, i32 0 + %v1 = insertelement <4 x double> %v0, double %r1, i32 1 + %v2 = insertelement <4 x double> %v1, double %r2, i32 2 + %v3 = insertelement <4 x double> %v2, double %r3, i32 3 + ret <4 x double> %v3 +} diff --git a/test/CodeGen/X86/ghc-cc.ll b/test/CodeGen/X86/ghc-cc.ll new file mode 100644 index 0000000..9393cf5 --- /dev/null +++ b/test/CodeGen/X86/ghc-cc.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -tailcallopt -mtriple=i686-linux-gnu | FileCheck %s + +; Test the GHC call convention works (x86-32) + +@base = external global i32 ; assigned to register: EBX +@sp = external global i32 ; assigned to register: EBP +@hp = external global i32 ; assigned to register: EDI +@r1 = external global i32 ; assigned to register: ESI + +define void @zap(i32 %a, i32 %b) nounwind { +entry: + ; CHECK: movl {{[0-9]*}}(%esp), %ebx + ; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp + ; CHECK-NEXT: call addtwo + %0 = call cc 10 i32 @addtwo(i32 %a, i32 %b) + ; CHECK: call foo + call void @foo() nounwind + ret void +} + +define cc 10 i32 @addtwo(i32 %x, i32 %y) nounwind { +entry: + ; CHECK: leal (%ebx,%ebp), %eax + %0 = add i32 %x, %y + ; CHECK-NEXT: ret + ret i32 %0 +} + +define cc 10 void @foo() nounwind { +entry: + ; CHECK: movl base, %ebx + ; CHECK-NEXT: movl sp, %ebp + ; CHECK-NEXT: movl hp, %edi + ; CHECK-NEXT: movl r1, %esi + %0 = load i32* @r1 + %1 = load i32* @hp + %2 = load i32* @sp + %3 = load i32* @base + ; CHECK: jmp bar + tail call cc 10 void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind + ret void +} + +declare cc 10 void @bar(i32, i32, i32, i32) + diff --git a/test/CodeGen/X86/ghc-cc64.ll b/test/CodeGen/X86/ghc-cc64.ll new file mode 100644 index 0000000..fcf7e17 --- /dev/null +++ b/test/CodeGen/X86/ghc-cc64.ll @@ -0,0 +1,86 @@ +; RUN: llc < %s -tailcallopt -mtriple=x86_64-linux-gnu | FileCheck %s + +; Check the GHC call convention works (x86-64) + +@base = external global i64 ; assigned to register: R13 +@sp = external global i64 ; assigned to register: RBP +@hp = external global i64 ; assigned to register: R12 +@r1 = external global i64 ; assigned to register: RBX +@r2 = external global i64 ; assigned to register: R14 +@r3 = external global i64 ; assigned to register: RSI +@r4 = external global i64 ; assigned to register: RDI +@r5 = external global i64 ; assigned to register: R8 +@r6 = external global i64 ; assigned to register: R9 +@splim = external global i64 ; assigned to register: R15 + +@f1 = external global float ; assigned to register: XMM1 +@f2 = external global float ; assigned to register: XMM2 +@f3 = external global float ; assigned to register: XMM3 +@f4 = external global float ; assigned to register: XMM4 +@d1 = external global double ; assigned to register: XMM5 +@d2 = external global double ; assigned to register: XMM6 + +define void @zap(i64 %a, i64 %b) nounwind { +entry: + ; CHECK: movq %rdi, %r13 + ; CHECK-NEXT: movq %rsi, %rbp + ; CHECK-NEXT: callq addtwo + %0 = call cc 10 i64 @addtwo(i64 %a, i64 %b) + ; CHECK: callq foo + call void @foo() nounwind + ret void +} + +define cc 10 i64 @addtwo(i64 %x, i64 %y) nounwind { +entry: + ; CHECK: leaq (%r13,%rbp), %rax + %0 = add i64 %x, %y + ; CHECK-NEXT: ret + ret i64 %0 +} + +define cc 10 void @foo() nounwind { +entry: + ; CHECK: movq base(%rip), %r13 + ; CHECK-NEXT: movq sp(%rip), %rbp + ; CHECK-NEXT: movq hp(%rip), %r12 + ; CHECK-NEXT: movq r1(%rip), %rbx + ; CHECK-NEXT: movq r2(%rip), %r14 + ; CHECK-NEXT: movq r3(%rip), %rsi + ; CHECK-NEXT: movq r4(%rip), %rdi + ; CHECK-NEXT: movq r5(%rip), %r8 + ; CHECK-NEXT: movq r6(%rip), %r9 + ; CHECK-NEXT: movq splim(%rip), %r15 + ; CHECK-NEXT: movss f1(%rip), %xmm1 + ; CHECK-NEXT: movss f2(%rip), %xmm2 + ; CHECK-NEXT: movss f3(%rip), %xmm3 + ; CHECK-NEXT: movss f4(%rip), %xmm4 + ; CHECK-NEXT: movsd d1(%rip), %xmm5 + ; CHECK-NEXT: movsd d2(%rip), %xmm6 + %0 = load double* @d2 + %1 = load double* @d1 + %2 = load float* @f4 + %3 = load float* @f3 + %4 = load float* @f2 + %5 = load float* @f1 + %6 = load i64* @splim + %7 = load i64* @r6 + %8 = load i64* @r5 + %9 = load i64* @r4 + %10 = load i64* @r3 + %11 = load i64* @r2 + %12 = load i64* @r1 + %13 = load i64* @hp + %14 = load i64* @sp + %15 = load i64* @base + ; CHECK: jmp bar + tail call cc 10 void @bar( i64 %15, i64 %14, i64 %13, i64 %12, i64 %11, + i64 %10, i64 %9, i64 %8, i64 %7, i64 %6, + float %5, float %4, float %3, float %2, double %1, + double %0 ) nounwind + ret void +} + +declare cc 10 void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, + float, float, float, float, double, double) + diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll index d79c56b..732d764 100644 --- a/test/CodeGen/X86/global-sections.ll +++ b/test/CodeGen/X86/global-sections.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX ; RUN: llc < %s -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -fdata-sections | FileCheck %s -check-prefix=LINUX-SECTIONS ; int G1; @@ -32,6 +33,12 @@ ; DARWIN: _G3: ; DARWIN: .long _G1 +; LINUX: .section .rodata,"a",@progbits +; LINUX: .globl G3 + +; LINUX-SECTIONS: .section .rodata.G3,"a",@progbits +; LINUX-SECTIONS: .globl G3 + ; _Complex long long const G4 = 34; @G4 = constant {i64,i64} { i64 34, i64 0 } @@ -97,6 +104,9 @@ ; LINUX: G7: ; LINUX: .asciz "abcdefghi" +; LINUX-SECTIONS: .section .rodata.G7,"aMS",@progbits,1 +; LINUX-SECTIONS: .globl G7 + @G8 = constant [4 x i16] [ i16 1, i16 2, i16 3, i16 0 ] diff --git a/test/CodeGen/X86/licm-symbol.ll b/test/CodeGen/X86/licm-symbol.ll index d61bbfc..08306c2 100644 --- a/test/CodeGen/X86/licm-symbol.ll +++ b/test/CodeGen/X86/licm-symbol.ll @@ -3,7 +3,7 @@ ; MachineLICM should be able to hoist the sF reference out of the loop. ; CHECK: pushl %esi -; CHECK: subl $8, %esp +; CHECK: subl $4, %esp ; CHECK: movl $176, %esi ; CHECK: addl L___sF$non_lazy_ptr, %esi ; CHECK: .align 4, 0x90 diff --git a/test/CodeGen/X86/liveness-local-regalloc.ll b/test/CodeGen/X86/liveness-local-regalloc.ll new file mode 100644 index 0000000..17e65d8 --- /dev/null +++ b/test/CodeGen/X86/liveness-local-regalloc.ll @@ -0,0 +1,60 @@ +; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10 +; <rdar://problem/7755473> + +%0 = type { i32, i8*, i8*, %1*, i8*, i64, i64, i32, i32, i32, i32, [1024 x i8] } +%1 = type { i8*, i32, i32, i16, i16, %2, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %2, %3*, i32, [3 x i8], [1 x i8], %2, i32, i64 } +%2 = type { i8*, i32 } +%3 = type opaque + +declare fastcc i32 @func(%0*, i32, i32) nounwind ssp + +define fastcc void @func2(%0* %arg, i32 %arg1) nounwind ssp { +bb: + br label %.exit3 + +.exit3: ; preds = %.exit3, %bb + switch i32 undef, label %.exit3 [ + i32 -1, label %.loopexit + i32 37, label %bb2 + ] + +bb2: ; preds = %bb5, %bb3, %.exit3 + br i1 undef, label %bb3, label %bb5 + +bb3: ; preds = %bb2 + switch i32 undef, label %infloop [ + i32 125, label %.loopexit + i32 -1, label %bb4 + i32 37, label %bb2 + ] + +bb4: ; preds = %bb3 + %tmp = add nsw i32 undef, 1 ; <i32> [#uses=1] + br label %.loopexit + +bb5: ; preds = %bb2 + switch i32 undef, label %infloop1 [ + i32 -1, label %.loopexit + i32 37, label %bb2 + ] + +.loopexit: ; preds = %bb5, %bb4, %bb3, %.exit3 + %.04 = phi i32 [ %tmp, %bb4 ], [ undef, %bb3 ], [ undef, %.exit3 ], [ undef, %bb5 ] ; <i32> [#uses=2] + br i1 undef, label %bb8, label %bb6 + +bb6: ; preds = %.loopexit + %tmp7 = tail call fastcc i32 @func(%0* %arg, i32 %.04, i32 undef) nounwind ssp ; <i32> [#uses=0] + ret void + +bb8: ; preds = %.loopexit + %tmp9 = sext i32 %.04 to i64 ; <i64> [#uses=1] + %tmp10 = getelementptr inbounds %0* %arg, i64 0, i32 11, i64 %tmp9 ; <i8*> [#uses=1] + store i8 0, i8* %tmp10, align 1 + ret void + +infloop: ; preds = %infloop, %bb3 + br label %infloop + +infloop1: ; preds = %infloop1, %bb5 + br label %infloop1 +} diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll index a125e54..354d082 100644 --- a/test/CodeGen/X86/loop-blocks.ll +++ b/test/CodeGen/X86/loop-blocks.ll @@ -7,11 +7,11 @@ ; order to avoid a branch within the loop. ; CHECK: simple: -; CHECK: jmp .LBB1_1 +; CHECK: jmp .LBB0_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: callq loop_header define void @simple() nounwind { @@ -37,11 +37,11 @@ done: ; falls through into the loop, avoiding a branch within the loop. ; CHECK: slightly_more_involved: -; CHECK: jmp .LBB2_1 +; CHECK: jmp .LBB1_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: callq bar99 -; CHECK-NEXT: .LBB2_1: +; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: callq body define void @slightly_more_involved() nounwind { @@ -72,20 +72,20 @@ exit: ; fallthrough edges which should be preserved. ; CHECK: yet_more_involved: -; CHECK: jmp .LBB3_1 +; CHECK: jmp .LBB2_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: callq bar99 ; CHECK-NEXT: callq get ; CHECK-NEXT: cmpl $2999, %eax -; CHECK-NEXT: jg .LBB3_6 +; CHECK-NEXT: jg .LBB2_6 ; CHECK-NEXT: callq block_a_true_func -; CHECK-NEXT: jmp .LBB3_7 -; CHECK-NEXT: .LBB3_6: +; CHECK-NEXT: jmp .LBB2_7 +; CHECK-NEXT: .LBB2_6: ; CHECK-NEXT: callq block_a_false_func -; CHECK-NEXT: .LBB3_7: +; CHECK-NEXT: .LBB2_7: ; CHECK-NEXT: callq block_a_merge_func -; CHECK-NEXT: .LBB3_1: +; CHECK-NEXT: .LBB2_1: ; CHECK-NEXT: callq body define void @yet_more_involved() nounwind { @@ -131,20 +131,20 @@ exit: ; loop. ; CHECK: cfg_islands: -; CHECK: jmp .LBB4_1 +; CHECK: jmp .LBB3_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB4_7: +; CHECK-NEXT: .LBB3_7: ; CHECK-NEXT: callq bar100 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_8: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_8: ; CHECK-NEXT: callq bar101 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_9: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_9: ; CHECK-NEXT: callq bar102 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_5: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_5: ; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: .LBB4_1: +; CHECK-NEXT: .LBB3_1: ; CHECK-NEXT: callq loop_header define void @cfg_islands() nounwind { diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll index b9008e5..c103e29 100644 --- a/test/CodeGen/X86/loop-hoist.ll +++ b/test/CodeGen/X86/loop-hoist.ll @@ -4,7 +4,7 @@ ; CHECK: _foo: ; CHECK: L_Arr$non_lazy_ptr -; CHECK: LBB1_1: +; CHECK: LBB0_1: @Arr = external global [0 x i32] ; <[0 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/loop-strength-reduce8.ll b/test/CodeGen/X86/loop-strength-reduce8.ll index 6b2247d..1d04276 100644 --- a/test/CodeGen/X86/loop-strength-reduce8.ll +++ b/test/CodeGen/X86/loop-strength-reduce8.ll @@ -4,7 +4,7 @@ ; CHECK: align ; CHECK: addl $4, %edx ; CHECK: decl %ecx -; CHECK: jne LBB1_2 +; CHECK: jne LBB0_2 %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 } %struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] } diff --git a/test/CodeGen/X86/lsr-delayed-fold.ll b/test/CodeGen/X86/lsr-delayed-fold.ll new file mode 100644 index 0000000..17d6a4c --- /dev/null +++ b/test/CodeGen/X86/lsr-delayed-fold.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=x86-64 < %s > /dev/null + +; ScalarEvolution misses an opportunity to fold ((trunc x) + (trunc -x) + y), +; but LSR should tolerate this. +; rdar://7886751 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0" + +define fastcc void @formatValue(i64 %arg5) nounwind { +bb12: ; preds = %bb11 + %t = trunc i64 %arg5 to i32 ; <i32> [#uses=1] + %t13 = sub i64 0, %arg5 ; <i64> [#uses=1] + %t14 = and i64 %t13, 4294967295 ; <i64> [#uses=1] + br label %bb15 + +bb15: ; preds = %bb21, %bb12 + %t16 = phi i64 [ 0, %bb12 ], [ %t23, %bb15 ] ; <i64> [#uses=2] + %t17 = mul i64 %t14, %t16 ; <i64> [#uses=1] + %t18 = add i64 undef, %t17 ; <i64> [#uses=1] + %t19 = trunc i64 %t18 to i32 ; <i32> [#uses=1] + %t22 = icmp eq i32 %t19, %t ; <i1> [#uses=1] + %t23 = add i64 %t16, 1 ; <i64> [#uses=1] + br i1 %t22, label %bb24, label %bb15 + +bb24: ; preds = %bb21, %bb11 + unreachable +} + +; ScalarEvolution should be able to correctly expand the crazy addrec here. +; PR6914 + +define void @int323() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %lbl_264, %for.inc, %entry + %g_263.tmp.1 = phi i8 [ undef, %entry ], [ %g_263.tmp.1, %for.cond ] + %p_95.addr.0 = phi i8 [ 0, %entry ], [ %add, %for.cond ] + %add = add i8 %p_95.addr.0, 1 ; <i8> [#uses=1] + br i1 undef, label %for.cond, label %lbl_264 + +lbl_264: ; preds = %if.end, %lbl_264.preheader + %g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1] + %tmp7 = load i16* undef ; <i16> [#uses=1] + %conv8 = trunc i16 %tmp7 to i8 ; <i8> [#uses=1] + %mul.i = mul i8 %p_95.addr.0, %p_95.addr.0 ; <i8> [#uses=1] + %mul.i18 = mul i8 %mul.i, %conv8 ; <i8> [#uses=1] + %tobool12 = icmp eq i8 %mul.i18, 0 ; <i1> [#uses=1] + unreachable +} diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index 2f6fb3f..b80ee08 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -8,10 +8,10 @@ target triple = "x86_64-unknown-unknown" ; CHECK: full_me_0: ; CHECK: movsd (%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: mulsd (%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, (%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -53,10 +53,10 @@ return: ; CHECK: mulsd -2048(%rdx), %xmm0 ; CHECK: movsd %xmm0, -2048(%rdi) ; CHECK: movsd (%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: divsd (%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, (%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -99,10 +99,10 @@ return: ; CHECK: mulsd (%rdx), %xmm0 ; CHECK: movsd %xmm0, (%rdi) ; CHECK: movsd -2048(%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: divsd -2048(%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, -2048(%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -144,10 +144,10 @@ return: ; CHECK: mulsd (%rdx), %xmm0 ; CHECK: movsd %xmm0, (%rdi) ; CHECK: movsd -4096(%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: divsd -4096(%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, -4096(%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -260,7 +260,7 @@ return: ; CHECK: count_me_2: ; CHECK: movl $10, %eax ; CHECK: align -; CHECK: BB7_1: +; CHECK: BB6_1: ; CHECK: movsd -40(%rdi,%rax,8), %xmm0 ; CHECK: addsd -40(%rsi,%rax,8), %xmm0 ; CHECK: movsd %xmm0, -40(%rdx,%rax,8) @@ -305,15 +305,15 @@ return: ; CHECK: full_me_1: ; CHECK: align -; CHECK: BB8_1: +; CHECK: BB7_1: ; CHECK: movsd (%rdi), %xmm0 ; CHECK: addsd (%rsi), %xmm0 ; CHECK: movsd %xmm0, (%rdx) ; CHECK: movsd 40(%rdi), %xmm0 -; CHECK: addq $8, %rdi ; CHECK: subsd 40(%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: movsd %xmm0, 40(%rdx) +; CHECK: addq $8, %rdi +; CHECK: addq $8, %rsi ; CHECK: addq $8, %rdx ; CHECK: decq %rcx ; CHECK: jne @@ -389,7 +389,7 @@ return: ; rdar://7657764 ; CHECK: asd: -; CHECK: BB10_5: +; CHECK: BB9_5: ; CHECK-NEXT: addl (%r{{[^,]*}},%rdi,4), %e ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: cmpq %rdi, %r{{[^,]*}} diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll new file mode 100644 index 0000000..a8afdc8 --- /dev/null +++ b/test/CodeGen/X86/machine-cse.ll @@ -0,0 +1,39 @@ +; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; rdar://7610418 + +%ptr = type { i8* } +%struct.s1 = type { %ptr, %ptr } +%struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] } +%struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 } + +define fastcc i8* @t(i64 %size) nounwind { +entry: +; CHECK: t: +; CHECK: leaq (%rax,%rax,4) + %0 = zext i32 undef to i64 + %1 = getelementptr inbounds %struct.s2* null, i64 %0 + br i1 undef, label %bb1, label %bb2 + +bb1: +; CHECK: %bb1 +; CHECK-NOT: shlq $9 +; CHECK-NOT: leaq +; CHECK: call + %2 = getelementptr inbounds %struct.s2* null, i64 %0, i32 0 + call void @bar(i32* %2) nounwind + unreachable + +bb2: +; CHECK: %bb2 +; CHECK-NOT: leaq +; CHECK: callq + %3 = call fastcc i8* @foo(%struct.s2* %1) nounwind + unreachable + +bb3: + ret i8* undef +} + +declare void @bar(i32*) + +declare fastcc i8* @foo(%struct.s2*) nounwind diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll index 2dc939e..17cd8e8 100644 --- a/test/CodeGen/X86/memcpy-2.ll +++ b/test/CodeGen/X86/memcpy-2.ll @@ -1,15 +1,167 @@ -; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7 -; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 5 +; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1 +; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64 - %struct.ParmT = type { [25 x i8], i8, i8* } -@.str12 = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" ; <[25 x i8]*> [#uses=1] +@.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" +@.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4 -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind +define void @t1(i32 %argc, i8** %argv) nounwind { +entry: +; SSE2: t1: +; SSE2: movaps _.str, %xmm0 +; SSE2: movaps %xmm0 +; SSE2: movb $0 +; SSE2: movl $0 +; SSE2: movl $0 + +; SSE1: t1: +; SSE1: movaps _.str, %xmm0 +; SSE1: movaps %xmm0 +; SSE1: movb $0 +; SSE1: movl $0 +; SSE1: movl $0 + +; NOSSE: t1: +; NOSSE: movb $0 +; NOSSE: movl $0 +; NOSSE: movl $0 +; NOSSE: movl $0 +; NOSSE: movl $0 +; NOSSE: movl $101 +; NOSSE: movl $1734438249 + +; X86-64: t1: +; X86-64: movaps _.str(%rip), %xmm0 +; X86-64: movaps %xmm0 +; X86-64: movb $0 +; X86-64: movq $0 + %tmp1 = alloca [25 x i8] + %tmp2 = bitcast [25 x i8]* %tmp1 to i8* + call void @llvm.memcpy.i32( i8* %tmp2, i8* getelementptr ([25 x i8]* @.str, i32 0, i32 0), i32 25, i32 1 ) nounwind + unreachable +} + +;rdar://7774704 +%struct.s0 = type { [2 x double] } + +define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp { +entry: +; SSE2: t2: +; SSE2: movaps (%eax), %xmm0 +; SSE2: movaps %xmm0, (%eax) + +; SSE1: t2: +; SSE1: movaps (%eax), %xmm0 +; SSE1: movaps %xmm0, (%eax) + +; NOSSE: t2: +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl + +; X86-64: t2: +; X86-64: movaps (%rsi), %xmm0 +; X86-64: movaps %xmm0, (%rdi) + %tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1] + %tmp3 = bitcast %struct.s0* %b to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 16) + ret void +} -define void @t(i32 %argc, i8** %argv) nounwind { +define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp { entry: - %parms.i = alloca [13 x %struct.ParmT] ; <[13 x %struct.ParmT]*> [#uses=1] - %parms1.i = getelementptr [13 x %struct.ParmT]* %parms.i, i32 0, i32 0, i32 0, i32 0 ; <i8*> [#uses=1] - call void @llvm.memcpy.i32( i8* %parms1.i, i8* getelementptr ([25 x i8]* @.str12, i32 0, i32 0), i32 25, i32 1 ) nounwind - unreachable +; SSE2: t3: +; SSE2: movsd (%eax), %xmm0 +; SSE2: movsd 8(%eax), %xmm1 +; SSE2: movsd %xmm1, 8(%eax) +; SSE2: movsd %xmm0, (%eax) + +; SSE1: t3: +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl + +; NOSSE: t3: +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl + +; X86-64: t3: +; X86-64: movq (%rsi), %rax +; X86-64: movq 8(%rsi), %rcx +; X86-64: movq %rcx, 8(%rdi) +; X86-64: movq %rax, (%rdi) + %tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1] + %tmp3 = bitcast %struct.s0* %b to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 8) + ret void } + +define void @t4() nounwind { +entry: +; SSE2: t4: +; SSE2: movw $120 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 + +; SSE1: t4: +; SSE1: movw $120 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 + +; NOSSE: t4: +; NOSSE: movw $120 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 + +; X86-64: t4: +; X86-64: movabsq $8680820740569200760, %rax +; X86-64: movq %rax +; X86-64: movq %rax +; X86-64: movq %rax +; X86-64: movw $120 +; X86-64: movl $2021161080 + %tmp1 = alloca [30 x i8] + %tmp2 = bitcast [30 x i8]* %tmp1 to i8* + call void @llvm.memcpy.i32(i8* %tmp2, i8* getelementptr inbounds ([30 x i8]* @.str2, i32 0, i32 0), i32 30, i32 1) + unreachable +} + +declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll index 24530cd..5a3ae77 100644 --- a/test/CodeGen/X86/memcpy.ll +++ b/test/CodeGen/X86/memcpy.ll @@ -2,13 +2,13 @@ declare void @llvm.memcpy.i64(i8*, i8*, i64, i32) -define i8* @my_memcpy(i8* %a, i8* %b, i64 %n) { +define i8* @my_memcpy(i8* %a, i8* %b, i64 %n) nounwind { entry: tail call void @llvm.memcpy.i64( i8* %a, i8* %b, i64 %n, i32 1 ) ret i8* %a } -define i8* @my_memcpy2(i64* %a, i64* %b, i64 %n) { +define i8* @my_memcpy2(i64* %a, i64* %b, i64 %n) nounwind { entry: %tmp14 = bitcast i64* %a to i8* %tmp25 = bitcast i64* %b to i8* diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll index 7deb52f..0e15595 100644 --- a/test/CodeGen/X86/memset-2.ll +++ b/test/CodeGen/X86/memset-2.ll @@ -1,47 +1,19 @@ -; RUN: llc < %s | not grep rep -; RUN: llc < %s | grep memset - -target triple = "i386" +; RUN: llc -mtriple=i386-apple-darwin < %s | FileCheck %s declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind -define fastcc i32 @cli_scanzip(i32 %desc) nounwind { +define fastcc void @t1() nounwind { entry: - br label %bb8.i.i.i.i - -bb8.i.i.i.i: ; preds = %bb8.i.i.i.i, %entry - icmp eq i32 0, 0 ; <i1>:0 [#uses=1] - br i1 %0, label %bb61.i.i.i, label %bb8.i.i.i.i - -bb32.i.i.i: ; preds = %bb61.i.i.i - ptrtoint i8* %tail.0.i.i.i to i32 ; <i32>:1 [#uses=1] - sub i32 0, %1 ; <i32>:2 [#uses=1] - icmp sgt i32 %2, 19 ; <i1>:3 [#uses=1] - br i1 %3, label %bb34.i.i.i, label %bb61.i.i.i - -bb34.i.i.i: ; preds = %bb32.i.i.i - load i32* null, align 4 ; <i32>:4 [#uses=1] - icmp eq i32 %4, 101010256 ; <i1>:5 [#uses=1] - br i1 %5, label %bb8.i11.i.i.i, label %bb61.i.i.i - -bb8.i11.i.i.i: ; preds = %bb8.i11.i.i.i, %bb34.i.i.i - icmp eq i32 0, 0 ; <i1>:6 [#uses=1] - br i1 %6, label %cli_dbgmsg.exit49.i, label %bb8.i11.i.i.i - -cli_dbgmsg.exit49.i: ; preds = %bb8.i11.i.i.i - icmp eq [32768 x i8]* null, null ; <i1>:7 [#uses=1] - br i1 %7, label %bb1.i28.i, label %bb8.i.i - -bb61.i.i.i: ; preds = %bb61.i.i.i, %bb34.i.i.i, %bb32.i.i.i, %bb8.i.i.i.i - %tail.0.i.i.i = getelementptr [1024 x i8]* null, i32 0, i32 0 ; <i8*> [#uses=2] - load i8* %tail.0.i.i.i, align 1 ; <i8>:8 [#uses=1] - icmp eq i8 %8, 80 ; <i1>:9 [#uses=1] - br i1 %9, label %bb32.i.i.i, label %bb61.i.i.i - -bb1.i28.i: ; preds = %cli_dbgmsg.exit49.i - call void @llvm.memset.i32( i8* null, i8 0, i32 88, i32 1 ) nounwind - unreachable +; CHECK: t1: +; CHECK: call _memset + call void @llvm.memset.i32( i8* null, i8 0, i32 188, i32 1 ) nounwind + unreachable +} -bb8.i.i: ; preds = %bb8.i.i, %cli_dbgmsg.exit49.i - br label %bb8.i.i +define fastcc void @t2(i8 signext %c) nounwind { +entry: +; CHECK: t2: +; CHECK: call _memset + call void @llvm.memset.i32( i8* undef, i8 %c, i32 76, i32 1 ) nounwind + unreachable } diff --git a/test/CodeGen/X86/memset-3.ll b/test/CodeGen/X86/memset-3.ll new file mode 100644 index 0000000..9b20ad5 --- /dev/null +++ b/test/CodeGen/X86/memset-3.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=i386-apple-darwin < %s | not grep memset +; PR6767 + +define void @t() nounwind ssp { +entry: + %buf = alloca [512 x i8], align 1 + %ptr = getelementptr inbounds [512 x i8]* %buf, i32 0, i32 0 + call void @llvm.memset.i32(i8* %ptr, i8 undef, i32 512, i32 1) + unreachable +} + +declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind diff --git a/test/CodeGen/X86/memset64-on-x86-32.ll b/test/CodeGen/X86/memset64-on-x86-32.ll index da8fc51..c0cd271 100644 --- a/test/CodeGen/X86/memset64-on-x86-32.ll +++ b/test/CodeGen/X86/memset64-on-x86-32.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | grep stosl -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq | count 10 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=nehalem | grep movaps | count 5 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 | grep movl | count 20 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | grep movq | count 10 define void @bork() nounwind { entry: diff --git a/test/CodeGen/X86/multiple-loop-post-inc.ll b/test/CodeGen/X86/multiple-loop-post-inc.ll new file mode 100644 index 0000000..51a0611 --- /dev/null +++ b/test/CodeGen/X86/multiple-loop-post-inc.ll @@ -0,0 +1,304 @@ +; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 < %s | FileCheck %s +; rdar://7236213 + +; CodeGen shouldn't require any lea instructions inside the marked loop. +; It should properly set up post-increment uses and do coalescing for +; the induction variables. + +; CHECK: # Start +; CHECK-NOT: lea +; CHECK: # Stop + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @foo(float* %I, i64 %IS, float* nocapture %Start, float* nocapture %Step, float* %O, i64 %OS, i64 %N) nounwind { +entry: + %times4 = alloca float, align 4 ; <float*> [#uses=3] + %timesN = alloca float, align 4 ; <float*> [#uses=2] + %0 = load float* %Step, align 4 ; <float> [#uses=8] + %1 = ptrtoint float* %I to i64 ; <i64> [#uses=1] + %2 = ptrtoint float* %O to i64 ; <i64> [#uses=1] + %tmp = xor i64 %2, %1 ; <i64> [#uses=1] + %tmp16 = and i64 %tmp, 15 ; <i64> [#uses=1] + %3 = icmp eq i64 %tmp16, 0 ; <i1> [#uses=1] + %4 = trunc i64 %IS to i32 ; <i32> [#uses=1] + %5 = xor i32 %4, 1 ; <i32> [#uses=1] + %6 = trunc i64 %OS to i32 ; <i32> [#uses=1] + %7 = xor i32 %6, 1 ; <i32> [#uses=1] + %8 = or i32 %7, %5 ; <i32> [#uses=1] + %9 = icmp eq i32 %8, 0 ; <i1> [#uses=1] + br i1 %9, label %bb, label %return + +bb: ; preds = %entry + %10 = load float* %Start, align 4 ; <float> [#uses=1] + br label %bb2 + +bb1: ; preds = %bb3 + %11 = load float* %I_addr.0, align 4 ; <float> [#uses=1] + %12 = fmul float %11, %x.0 ; <float> [#uses=1] + store float %12, float* %O_addr.0, align 4 + %13 = fadd float %x.0, %0 ; <float> [#uses=1] + %indvar.next53 = add i64 %14, 1 ; <i64> [#uses=1] + br label %bb2 + +bb2: ; preds = %bb1, %bb + %14 = phi i64 [ %indvar.next53, %bb1 ], [ 0, %bb ] ; <i64> [#uses=21] + %x.0 = phi float [ %13, %bb1 ], [ %10, %bb ] ; <float> [#uses=6] + %N_addr.0 = sub i64 %N, %14 ; <i64> [#uses=4] + %O_addr.0 = getelementptr float* %O, i64 %14 ; <float*> [#uses=4] + %I_addr.0 = getelementptr float* %I, i64 %14 ; <float*> [#uses=3] + %15 = icmp slt i64 %N_addr.0, 1 ; <i1> [#uses=1] + br i1 %15, label %bb4, label %bb3 + +bb3: ; preds = %bb2 + %16 = ptrtoint float* %O_addr.0 to i64 ; <i64> [#uses=1] + %17 = and i64 %16, 15 ; <i64> [#uses=1] + %18 = icmp eq i64 %17, 0 ; <i1> [#uses=1] + br i1 %18, label %bb4, label %bb1 + +bb4: ; preds = %bb3, %bb2 + %19 = fmul float %0, 4.000000e+00 ; <float> [#uses=1] + store float %19, float* %times4, align 4 + %20 = fmul float %0, 1.600000e+01 ; <float> [#uses=1] + store float %20, float* %timesN, align 4 + %21 = fmul float %0, 0.000000e+00 ; <float> [#uses=1] + %22 = fadd float %21, %x.0 ; <float> [#uses=1] + %23 = fadd float %x.0, %0 ; <float> [#uses=1] + %24 = fmul float %0, 2.000000e+00 ; <float> [#uses=1] + %25 = fadd float %24, %x.0 ; <float> [#uses=1] + %26 = fmul float %0, 3.000000e+00 ; <float> [#uses=1] + %27 = fadd float %26, %x.0 ; <float> [#uses=1] + %28 = insertelement <4 x float> undef, float %22, i32 0 ; <<4 x float>> [#uses=1] + %29 = insertelement <4 x float> %28, float %23, i32 1 ; <<4 x float>> [#uses=1] + %30 = insertelement <4 x float> %29, float %25, i32 2 ; <<4 x float>> [#uses=1] + %31 = insertelement <4 x float> %30, float %27, i32 3 ; <<4 x float>> [#uses=5] + %asmtmp.i = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %times4) nounwind ; <<4 x float>> [#uses=3] + %32 = fadd <4 x float> %31, %asmtmp.i ; <<4 x float>> [#uses=3] + %33 = fadd <4 x float> %32, %asmtmp.i ; <<4 x float>> [#uses=3] + %34 = fadd <4 x float> %33, %asmtmp.i ; <<4 x float>> [#uses=2] + %asmtmp.i18 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %timesN) nounwind ; <<4 x float>> [#uses=8] + %35 = icmp sgt i64 %N_addr.0, 15 ; <i1> [#uses=2] + br i1 %3, label %bb6.preheader, label %bb8 + +bb6.preheader: ; preds = %bb4 + br i1 %35, label %bb.nph43, label %bb7 + +bb.nph43: ; preds = %bb6.preheader + %tmp108 = add i64 %14, 16 ; <i64> [#uses=1] + %tmp111 = add i64 %14, 4 ; <i64> [#uses=1] + %tmp115 = add i64 %14, 8 ; <i64> [#uses=1] + %tmp119 = add i64 %14, 12 ; <i64> [#uses=1] + %tmp134 = add i64 %N, -16 ; <i64> [#uses=1] + %tmp135 = sub i64 %tmp134, %14 ; <i64> [#uses=1] + call void asm sideeffect "# Start.", "~{dirflag},~{fpsr},~{flags}"() nounwind + br label %bb5 + +bb5: ; preds = %bb.nph43, %bb5 + %indvar102 = phi i64 [ 0, %bb.nph43 ], [ %indvar.next103, %bb5 ] ; <i64> [#uses=3] + %vX3.041 = phi <4 x float> [ %34, %bb.nph43 ], [ %45, %bb5 ] ; <<4 x float>> [#uses=2] + %vX0.039 = phi <4 x float> [ %31, %bb.nph43 ], [ %41, %bb5 ] ; <<4 x float>> [#uses=2] + %vX2.037 = phi <4 x float> [ %33, %bb.nph43 ], [ %46, %bb5 ] ; <<4 x float>> [#uses=2] + %vX1.036 = phi <4 x float> [ %32, %bb.nph43 ], [ %47, %bb5 ] ; <<4 x float>> [#uses=2] + %tmp104 = shl i64 %indvar102, 4 ; <i64> [#uses=5] + %tmp105 = add i64 %14, %tmp104 ; <i64> [#uses=2] + %scevgep106 = getelementptr float* %I, i64 %tmp105 ; <float*> [#uses=1] + %scevgep106107 = bitcast float* %scevgep106 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp109 = add i64 %tmp108, %tmp104 ; <i64> [#uses=2] + %tmp112 = add i64 %tmp111, %tmp104 ; <i64> [#uses=2] + %scevgep113 = getelementptr float* %I, i64 %tmp112 ; <float*> [#uses=1] + %scevgep113114 = bitcast float* %scevgep113 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp116 = add i64 %tmp115, %tmp104 ; <i64> [#uses=2] + %scevgep117 = getelementptr float* %I, i64 %tmp116 ; <float*> [#uses=1] + %scevgep117118 = bitcast float* %scevgep117 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp120 = add i64 %tmp119, %tmp104 ; <i64> [#uses=2] + %scevgep121 = getelementptr float* %I, i64 %tmp120 ; <float*> [#uses=1] + %scevgep121122 = bitcast float* %scevgep121 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep123 = getelementptr float* %O, i64 %tmp105 ; <float*> [#uses=1] + %scevgep123124 = bitcast float* %scevgep123 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep126 = getelementptr float* %O, i64 %tmp112 ; <float*> [#uses=1] + %scevgep126127 = bitcast float* %scevgep126 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep128 = getelementptr float* %O, i64 %tmp116 ; <float*> [#uses=1] + %scevgep128129 = bitcast float* %scevgep128 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep130 = getelementptr float* %O, i64 %tmp120 ; <float*> [#uses=1] + %scevgep130131 = bitcast float* %scevgep130 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp132 = mul i64 %indvar102, -16 ; <i64> [#uses=1] + %tmp136 = add i64 %tmp135, %tmp132 ; <i64> [#uses=2] + %36 = load <4 x float>* %scevgep106107, align 16 ; <<4 x float>> [#uses=1] + %37 = load <4 x float>* %scevgep113114, align 16 ; <<4 x float>> [#uses=1] + %38 = load <4 x float>* %scevgep117118, align 16 ; <<4 x float>> [#uses=1] + %39 = load <4 x float>* %scevgep121122, align 16 ; <<4 x float>> [#uses=1] + %40 = fmul <4 x float> %36, %vX0.039 ; <<4 x float>> [#uses=1] + %41 = fadd <4 x float> %vX0.039, %asmtmp.i18 ; <<4 x float>> [#uses=2] + %42 = fmul <4 x float> %37, %vX1.036 ; <<4 x float>> [#uses=1] + %43 = fmul <4 x float> %38, %vX2.037 ; <<4 x float>> [#uses=1] + %44 = fmul <4 x float> %39, %vX3.041 ; <<4 x float>> [#uses=1] + store <4 x float> %40, <4 x float>* %scevgep123124, align 16 + store <4 x float> %42, <4 x float>* %scevgep126127, align 16 + store <4 x float> %43, <4 x float>* %scevgep128129, align 16 + store <4 x float> %44, <4 x float>* %scevgep130131, align 16 + %45 = fadd <4 x float> %vX3.041, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %46 = fadd <4 x float> %vX2.037, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %47 = fadd <4 x float> %vX1.036, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %48 = icmp sgt i64 %tmp136, 15 ; <i1> [#uses=1] + %indvar.next103 = add i64 %indvar102, 1 ; <i64> [#uses=1] + br i1 %48, label %bb5, label %bb6.bb7_crit_edge + +bb6.bb7_crit_edge: ; preds = %bb5 + call void asm sideeffect "# Stop.", "~{dirflag},~{fpsr},~{flags}"() nounwind + %scevgep110 = getelementptr float* %I, i64 %tmp109 ; <float*> [#uses=1] + %scevgep125 = getelementptr float* %O, i64 %tmp109 ; <float*> [#uses=1] + br label %bb7 + +bb7: ; preds = %bb6.bb7_crit_edge, %bb6.preheader + %I_addr.1.lcssa = phi float* [ %scevgep110, %bb6.bb7_crit_edge ], [ %I_addr.0, %bb6.preheader ] ; <float*> [#uses=1] + %O_addr.1.lcssa = phi float* [ %scevgep125, %bb6.bb7_crit_edge ], [ %O_addr.0, %bb6.preheader ] ; <float*> [#uses=1] + %vX0.0.lcssa = phi <4 x float> [ %41, %bb6.bb7_crit_edge ], [ %31, %bb6.preheader ] ; <<4 x float>> [#uses=1] + %N_addr.1.lcssa = phi i64 [ %tmp136, %bb6.bb7_crit_edge ], [ %N_addr.0, %bb6.preheader ] ; <i64> [#uses=1] + %asmtmp.i17 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %times4) nounwind ; <<4 x float>> [#uses=0] + br label %bb11 + +bb8: ; preds = %bb4 + br i1 %35, label %bb.nph, label %bb11 + +bb.nph: ; preds = %bb8 + %I_addr.0.sum = add i64 %14, -1 ; <i64> [#uses=1] + %49 = getelementptr inbounds float* %I, i64 %I_addr.0.sum ; <float*> [#uses=1] + %50 = bitcast float* %49 to <4 x float>* ; <<4 x float>*> [#uses=1] + %51 = load <4 x float>* %50, align 16 ; <<4 x float>> [#uses=1] + %tmp54 = add i64 %14, 16 ; <i64> [#uses=1] + %tmp56 = add i64 %14, 3 ; <i64> [#uses=1] + %tmp60 = add i64 %14, 7 ; <i64> [#uses=1] + %tmp64 = add i64 %14, 11 ; <i64> [#uses=1] + %tmp68 = add i64 %14, 15 ; <i64> [#uses=1] + %tmp76 = add i64 %14, 4 ; <i64> [#uses=1] + %tmp80 = add i64 %14, 8 ; <i64> [#uses=1] + %tmp84 = add i64 %14, 12 ; <i64> [#uses=1] + %tmp90 = add i64 %N, -16 ; <i64> [#uses=1] + %tmp91 = sub i64 %tmp90, %14 ; <i64> [#uses=1] + br label %bb9 + +bb9: ; preds = %bb.nph, %bb9 + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb9 ] ; <i64> [#uses=3] + %vX3.125 = phi <4 x float> [ %34, %bb.nph ], [ %69, %bb9 ] ; <<4 x float>> [#uses=2] + %vX0.223 = phi <4 x float> [ %31, %bb.nph ], [ %65, %bb9 ] ; <<4 x float>> [#uses=2] + %vX2.121 = phi <4 x float> [ %33, %bb.nph ], [ %70, %bb9 ] ; <<4 x float>> [#uses=2] + %vX1.120 = phi <4 x float> [ %32, %bb.nph ], [ %71, %bb9 ] ; <<4 x float>> [#uses=2] + %vI0.019 = phi <4 x float> [ %51, %bb.nph ], [ %55, %bb9 ] ; <<4 x float>> [#uses=1] + %tmp51 = shl i64 %indvar, 4 ; <i64> [#uses=9] + %tmp55 = add i64 %tmp54, %tmp51 ; <i64> [#uses=2] + %tmp57 = add i64 %tmp56, %tmp51 ; <i64> [#uses=1] + %scevgep58 = getelementptr float* %I, i64 %tmp57 ; <float*> [#uses=1] + %scevgep5859 = bitcast float* %scevgep58 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp61 = add i64 %tmp60, %tmp51 ; <i64> [#uses=1] + %scevgep62 = getelementptr float* %I, i64 %tmp61 ; <float*> [#uses=1] + %scevgep6263 = bitcast float* %scevgep62 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp65 = add i64 %tmp64, %tmp51 ; <i64> [#uses=1] + %scevgep66 = getelementptr float* %I, i64 %tmp65 ; <float*> [#uses=1] + %scevgep6667 = bitcast float* %scevgep66 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp69 = add i64 %tmp68, %tmp51 ; <i64> [#uses=1] + %scevgep70 = getelementptr float* %I, i64 %tmp69 ; <float*> [#uses=1] + %scevgep7071 = bitcast float* %scevgep70 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp72 = add i64 %14, %tmp51 ; <i64> [#uses=1] + %scevgep73 = getelementptr float* %O, i64 %tmp72 ; <float*> [#uses=1] + %scevgep7374 = bitcast float* %scevgep73 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp77 = add i64 %tmp76, %tmp51 ; <i64> [#uses=1] + %scevgep78 = getelementptr float* %O, i64 %tmp77 ; <float*> [#uses=1] + %scevgep7879 = bitcast float* %scevgep78 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp81 = add i64 %tmp80, %tmp51 ; <i64> [#uses=1] + %scevgep82 = getelementptr float* %O, i64 %tmp81 ; <float*> [#uses=1] + %scevgep8283 = bitcast float* %scevgep82 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp85 = add i64 %tmp84, %tmp51 ; <i64> [#uses=1] + %scevgep86 = getelementptr float* %O, i64 %tmp85 ; <float*> [#uses=1] + %scevgep8687 = bitcast float* %scevgep86 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp88 = mul i64 %indvar, -16 ; <i64> [#uses=1] + %tmp92 = add i64 %tmp91, %tmp88 ; <i64> [#uses=2] + %52 = load <4 x float>* %scevgep5859, align 16 ; <<4 x float>> [#uses=2] + %53 = load <4 x float>* %scevgep6263, align 16 ; <<4 x float>> [#uses=2] + %54 = load <4 x float>* %scevgep6667, align 16 ; <<4 x float>> [#uses=2] + %55 = load <4 x float>* %scevgep7071, align 16 ; <<4 x float>> [#uses=2] + %56 = shufflevector <4 x float> %vI0.019, <4 x float> %52, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %57 = shufflevector <4 x float> %56, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %58 = shufflevector <4 x float> %52, <4 x float> %53, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %59 = shufflevector <4 x float> %58, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %60 = shufflevector <4 x float> %53, <4 x float> %54, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %61 = shufflevector <4 x float> %60, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %62 = shufflevector <4 x float> %54, <4 x float> %55, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %63 = shufflevector <4 x float> %62, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %64 = fmul <4 x float> %57, %vX0.223 ; <<4 x float>> [#uses=1] + %65 = fadd <4 x float> %vX0.223, %asmtmp.i18 ; <<4 x float>> [#uses=2] + %66 = fmul <4 x float> %59, %vX1.120 ; <<4 x float>> [#uses=1] + %67 = fmul <4 x float> %61, %vX2.121 ; <<4 x float>> [#uses=1] + %68 = fmul <4 x float> %63, %vX3.125 ; <<4 x float>> [#uses=1] + store <4 x float> %64, <4 x float>* %scevgep7374, align 16 + store <4 x float> %66, <4 x float>* %scevgep7879, align 16 + store <4 x float> %67, <4 x float>* %scevgep8283, align 16 + store <4 x float> %68, <4 x float>* %scevgep8687, align 16 + %69 = fadd <4 x float> %vX3.125, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %70 = fadd <4 x float> %vX2.121, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %71 = fadd <4 x float> %vX1.120, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %72 = icmp sgt i64 %tmp92, 15 ; <i1> [#uses=1] + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1] + br i1 %72, label %bb9, label %bb10.bb11.loopexit_crit_edge + +bb10.bb11.loopexit_crit_edge: ; preds = %bb9 + %scevgep = getelementptr float* %I, i64 %tmp55 ; <float*> [#uses=1] + %scevgep75 = getelementptr float* %O, i64 %tmp55 ; <float*> [#uses=1] + br label %bb11 + +bb11: ; preds = %bb8, %bb10.bb11.loopexit_crit_edge, %bb7 + %N_addr.2 = phi i64 [ %N_addr.1.lcssa, %bb7 ], [ %tmp92, %bb10.bb11.loopexit_crit_edge ], [ %N_addr.0, %bb8 ] ; <i64> [#uses=2] + %vX0.1 = phi <4 x float> [ %vX0.0.lcssa, %bb7 ], [ %65, %bb10.bb11.loopexit_crit_edge ], [ %31, %bb8 ] ; <<4 x float>> [#uses=1] + %O_addr.2 = phi float* [ %O_addr.1.lcssa, %bb7 ], [ %scevgep75, %bb10.bb11.loopexit_crit_edge ], [ %O_addr.0, %bb8 ] ; <float*> [#uses=1] + %I_addr.2 = phi float* [ %I_addr.1.lcssa, %bb7 ], [ %scevgep, %bb10.bb11.loopexit_crit_edge ], [ %I_addr.0, %bb8 ] ; <float*> [#uses=1] + %73 = extractelement <4 x float> %vX0.1, i32 0 ; <float> [#uses=2] + %74 = icmp sgt i64 %N_addr.2, 0 ; <i1> [#uses=1] + br i1 %74, label %bb12, label %bb14 + +bb12: ; preds = %bb11, %bb12 + %indvar94 = phi i64 [ %indvar.next95, %bb12 ], [ 0, %bb11 ] ; <i64> [#uses=3] + %x.130 = phi float [ %77, %bb12 ], [ %73, %bb11 ] ; <float> [#uses=2] + %I_addr.433 = getelementptr float* %I_addr.2, i64 %indvar94 ; <float*> [#uses=1] + %O_addr.432 = getelementptr float* %O_addr.2, i64 %indvar94 ; <float*> [#uses=1] + %75 = load float* %I_addr.433, align 4 ; <float> [#uses=1] + %76 = fmul float %75, %x.130 ; <float> [#uses=1] + store float %76, float* %O_addr.432, align 4 + %77 = fadd float %x.130, %0 ; <float> [#uses=2] + %indvar.next95 = add i64 %indvar94, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %indvar.next95, %N_addr.2 ; <i1> [#uses=1] + br i1 %exitcond, label %bb14, label %bb12 + +bb14: ; preds = %bb12, %bb11 + %x.1.lcssa = phi float [ %73, %bb11 ], [ %77, %bb12 ] ; <float> [#uses=1] + store float %x.1.lcssa, float* %Start, align 4 + ret void + +return: ; preds = %entry + ret void +} + +; Codegen shouldn't crash on this testcase. + +define void @bar(i32 %a, i32 %b) nounwind { +entry: ; preds = %bb1, %entry, %for.end204 + br label %outer + +outer: ; preds = %bb1, %entry + %i6 = phi i32 [ %storemerge171, %bb1 ], [ %a, %entry ] ; <i32> [#uses=2] + %storemerge171 = add i32 %i6, 1 ; <i32> [#uses=1] + br label %inner + +inner: ; preds = %bb0, %if.end275 + %i8 = phi i32 [ %a, %outer ], [ %indvar.next159, %bb0 ] ; <i32> [#uses=2] + %t338 = load i32* undef ; <i32> [#uses=1] + %t191 = mul i32 %i8, %t338 ; <i32> [#uses=1] + %t179 = add i32 %i6, %t191 ; <i32> [#uses=1] + br label %bb0 + +bb0: ; preds = %for.body332 + %indvar.next159 = add i32 %i8, 1 ; <i32> [#uses=1] + br i1 undef, label %bb1, label %inner + +bb1: ; preds = %bb0, %outer + %midx.4 = phi i32 [ %t179, %bb0 ] ; <i32> [#uses=0] + br label %outer +} diff --git a/test/CodeGen/X86/object-size.ll b/test/CodeGen/X86/object-size.ll index eed3cfc..bbe6b23 100644 --- a/test/CodeGen/X86/object-size.ll +++ b/test/CodeGen/X86/object-size.ll @@ -12,7 +12,7 @@ entry: %tmp = load i8** @p ; <i8*> [#uses=1] %0 = call i64 @llvm.objectsize.i64(i8* %tmp, i1 0) ; <i64> [#uses=1] %cmp = icmp ne i64 %0, -1 ; <i1> [#uses=1] -; X64: movq $-1, %rax +; X64: movabsq $-1, %rax ; X64: cmpq $-1, %rax br i1 %cmp, label %cond.true, label %cond.false diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll new file mode 100644 index 0000000..bf8bfa2 --- /dev/null +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; LSR's OptimizeMax should eliminate the select (max). + +; CHECK: foo: +; CHECK-NOT: cmov +; CHECK: jle + +define void @foo(i64 %n, double* nocapture %p) nounwind { +entry: + %cmp6 = icmp slt i64 %n, 0 ; <i1> [#uses=1] + br i1 %cmp6, label %for.end, label %for.body.preheader + +for.body.preheader: ; preds = %entry + %tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1] + %n.op = add i64 %n, 1 ; <i64> [#uses=1] + %tmp1 = select i1 %tmp, i64 %n.op, i64 1 ; <i64> [#uses=1] + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i = phi i64 [ %i.next, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2] + %arrayidx = getelementptr double* %p, i64 %i ; <double*> [#uses=2] + %t4 = load double* %arrayidx ; <double> [#uses=1] + %mul = fmul double %t4, 2.200000e+00 ; <double> [#uses=1] + store double %mul, double* %arrayidx + %i.next = add nsw i64 %i, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %i.next, %tmp1 ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll new file mode 100644 index 0000000..6447680 --- /dev/null +++ b/test/CodeGen/X86/or-address.ll @@ -0,0 +1,90 @@ +; PR1135 +; RUN: llc %s -o - | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.3" + + +; CHECK: movl %{{.*}}, (%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 8(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 4(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 12(%rdi,%rdx,4) + +define void @test(i32* nocapture %array, i32 %r0) nounwind ssp noredzone { +bb.nph: + br label %bb + +bb: ; preds = %bb, %bb.nph + %j.010 = phi i8 [ 0, %bb.nph ], [ %14, %bb ] ; <i8> [#uses=1] + %k.19 = phi i8 [ 0, %bb.nph ], [ %.k.1, %bb ] ; <i8> [#uses=1] + %i0.08 = phi i8 [ 0, %bb.nph ], [ %15, %bb ] ; <i8> [#uses=3] + %0 = icmp slt i8 %i0.08, 4 ; <i1> [#uses=1] + %iftmp.0.0 = select i1 %0, i8 %i0.08, i8 0 ; <i8> [#uses=2] + %1 = icmp eq i8 %i0.08, 4 ; <i1> [#uses=1] + %2 = zext i1 %1 to i8 ; <i8> [#uses=1] + %.k.1 = add i8 %2, %k.19 ; <i8> [#uses=2] + %3 = shl i8 %.k.1, 2 ; <i8> [#uses=1] + %4 = add i8 %3, %iftmp.0.0 ; <i8> [#uses=1] + %5 = shl i8 %4, 2 ; <i8> [#uses=1] + %6 = zext i8 %5 to i64 ; <i64> [#uses=4] + %7 = getelementptr inbounds i32* %array, i64 %6 ; <i32*> [#uses=1] + store i32 %r0, i32* %7, align 4 + %8 = or i64 %6, 2 ; <i64> [#uses=1] + %9 = getelementptr inbounds i32* %array, i64 %8 ; <i32*> [#uses=1] + store i32 %r0, i32* %9, align 4 + %10 = or i64 %6, 1 ; <i64> [#uses=1] + %11 = getelementptr inbounds i32* %array, i64 %10 ; <i32*> [#uses=1] + store i32 %r0, i32* %11, align 4 + %12 = or i64 %6, 3 ; <i64> [#uses=1] + %13 = getelementptr inbounds i32* %array, i64 %12 ; <i32*> [#uses=1] + store i32 %r0, i32* %13, align 4 + %14 = add nsw i8 %j.010, 1 ; <i8> [#uses=2] + %15 = add i8 %iftmp.0.0, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %14, 32 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} + +; CHECK: test1: +; CHECK: movl %{{.*}}, (%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 8(%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 4(%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 12(%rdi,%rcx,4) + +define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind { +bb.nph: + br label %for.body + +for.body: ; preds = %for.body, %bb.nph + %j.065 = phi i8 [ 0, %bb.nph ], [ %inc52, %for.body ] ; <i8> [#uses=1] + %i0.addr.064 = phi i8 [ %i0, %bb.nph ], [ %add, %for.body ] ; <i8> [#uses=3] + %k.addr.163 = phi i8 [ %k, %bb.nph ], [ %inc.k.addr.1, %for.body ] ; <i8> [#uses=1] + %cmp5 = icmp slt i8 %i0.addr.064, 4 ; <i1> [#uses=1] + %cond = select i1 %cmp5, i8 %i0.addr.064, i8 0 ; <i8> [#uses=2] + %cmp12 = icmp eq i8 %i0.addr.064, 4 ; <i1> [#uses=1] + %inc = zext i1 %cmp12 to i8 ; <i8> [#uses=1] + %inc.k.addr.1 = add i8 %inc, %k.addr.163 ; <i8> [#uses=2] + %mul = shl i8 %cond, 2 ; <i8> [#uses=1] + %mul22 = shl i8 %inc.k.addr.1, 4 ; <i8> [#uses=1] + %add23 = add i8 %mul22, %mul ; <i8> [#uses=1] + %idxprom = zext i8 %add23 to i64 ; <i64> [#uses=4] + %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx + %add3356 = or i64 %idxprom, 2 ; <i64> [#uses=1] + %arrayidx36 = getelementptr inbounds i32* %array, i64 %add3356 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx36 + %add4058 = or i64 %idxprom, 1 ; <i64> [#uses=1] + %arrayidx43 = getelementptr inbounds i32* %array, i64 %add4058 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx43 + %add4760 = or i64 %idxprom, 3 ; <i64> [#uses=1] + %arrayidx50 = getelementptr inbounds i32* %array, i64 %add4760 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx50 + %inc52 = add nsw i8 %j.065, 1 ; <i8> [#uses=2] + %add = add i8 %cond, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %inc52, 32 ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/CodeGen/X86/personality.ll b/test/CodeGen/X86/personality.ll index ce57e8f..6789bb0 100644 --- a/test/CodeGen/X86/personality.ll +++ b/test/CodeGen/X86/personality.ll @@ -38,10 +38,10 @@ declare void @__gxx_personality_v0() declare void @__cxa_end_catch() -; X64: Leh_frame_common_begin: -; X64: .long (___gxx_personality_v0@GOTPCREL)+4 +; X64: Leh_frame_common_begin0: +; X64: .long ___gxx_personality_v0@GOTPCREL+4 -; X32: Leh_frame_common_begin: +; X32: Leh_frame_common_begin0: ; X32: .long L___gxx_personality_v0$non_lazy_ptr- ; .... diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll new file mode 100644 index 0000000..f23669e --- /dev/null +++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s +; rdar://5571034 + +define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp { +; CHECK: foo: +entry: + %j.03 = add i32 %bbSize, -1 ; <i32> [#uses=2] + %0 = icmp sgt i32 %j.03, -1 ; <i1> [#uses=1] + br i1 %0, label %bb.nph, label %return + +bb.nph: ; preds = %entry + %tmp9 = add i32 %bbStart, %bbSize ; <i32> [#uses=1] + %tmp10 = add i32 %tmp9, -1 ; <i32> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph +; CHECK: %bb +; CHECK-NOT: movb {{.*}}l, %cl +; CHECK: sarl %cl + %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3] + %j.06 = sub i32 %j.03, %indvar ; <i32> [#uses=1] + %tmp11 = sub i32 %tmp10, %indvar ; <i32> [#uses=1] + %scevgep = getelementptr i32* %ptr, i32 %tmp11 ; <i32*> [#uses=1] + %1 = load i32* %scevgep, align 4 ; <i32> [#uses=1] + %2 = ashr i32 %j.06, %shifts ; <i32> [#uses=1] + %3 = and i32 %2, 65535 ; <i32> [#uses=1] + %4 = getelementptr inbounds i32* %quadrant, i32 %1 ; <i32*> [#uses=1] + store i32 %3, i32* %4, align 4 + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %bbSize ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index d3c28a0..9506c9b 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -4,18 +4,18 @@ @dst = external global i32 @src = external global i32 -define void @test1() nounwind { +define void @test0() nounwind { entry: store i32* @dst, i32** @ptr %tmp.s = load i32* @src store i32 %tmp.s, i32* @dst ret void -; LINUX: test1: -; LINUX: call .L1$pb -; LINUX-NEXT: .L1$pb: +; LINUX: test0: +; LINUX: call .L0$pb +; LINUX-NEXT: .L0$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref1-.L1$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L0$pb), ; LINUX: movl dst@GOT(%eax), ; LINUX: movl ptr@GOT(%eax), ; LINUX: movl src@GOT(%eax), @@ -26,18 +26,18 @@ entry: @dst2 = global i32 0 @src2 = global i32 0 -define void @test2() nounwind { +define void @test1() nounwind { entry: store i32* @dst2, i32** @ptr2 %tmp.s = load i32* @src2 store i32 %tmp.s, i32* @dst2 ret void -; LINUX: test2: -; LINUX: call .L2$pb -; LINUX-NEXT: .L2$pb: +; LINUX: test1: +; LINUX: call .L1$pb +; LINUX-NEXT: .L1$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref2-.L2$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), %eax ; LINUX: movl dst2@GOT(%eax), ; LINUX: movl ptr2@GOT(%eax), ; LINUX: movl src2@GOT(%eax), @@ -47,17 +47,17 @@ entry: declare i8* @malloc(i32) -define void @test3() nounwind { +define void @test2() nounwind { entry: %ptr = call i8* @malloc(i32 40) ret void -; LINUX: test3: +; LINUX: test2: ; LINUX: pushl %ebx ; LINUX-NEXT: subl $8, %esp -; LINUX-NEXT: call .L3$pb -; LINUX-NEXT: .L3$pb: +; LINUX-NEXT: call .L2$pb +; LINUX-NEXT: .L2$pb: ; LINUX-NEXT: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref3-.L3$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %ebx ; LINUX: movl $40, (%esp) ; LINUX: call malloc@PLT ; LINUX: addl $8, %esp @@ -67,18 +67,18 @@ entry: @pfoo = external global void(...)* -define void @test4() nounwind { +define void @test3() nounwind { entry: %tmp = call void(...)*(...)* @afoo() store void(...)* %tmp, void(...)** @pfoo %tmp1 = load void(...)** @pfoo call void(...)* %tmp1() ret void -; LINUX: test4: -; LINUX: call .L4$pb -; LINUX-NEXT: .L4$pb: +; LINUX: test3: +; LINUX: call .L3$pb +; LINUX-NEXT: .L3$pb: ; LINUX: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref4-.L4$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), ; LINUX: movl pfoo@GOT(%esi), ; LINUX: call afoo@PLT ; LINUX: call * @@ -86,14 +86,14 @@ entry: declare void(...)* @afoo(...) -define void @test5() nounwind { +define void @test4() nounwind { entry: call void(...)* @foo() ret void -; LINUX: test5: -; LINUX: call .L5$pb +; LINUX: test4: +; LINUX: call .L4$pb ; LINUX: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref5-.L5$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx ; LINUX: call foo@PLT } @@ -104,18 +104,18 @@ declare void @foo(...) @dst6 = internal global i32 0 @src6 = internal global i32 0 -define void @test6() nounwind { +define void @test5() nounwind { entry: store i32* @dst6, i32** @ptr6 %tmp.s = load i32* @src6 store i32 %tmp.s, i32* @dst6 ret void -; LINUX: test6: -; LINUX: call .L6$pb -; LINUX-NEXT: .L6$pb: +; LINUX: test5: +; LINUX: call .L5$pb +; LINUX-NEXT: .L5$pb: ; LINUX-NEXT: popl %eax -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref6-.L6$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %eax ; LINUX: leal dst6@GOTOFF(%eax), %ecx ; LINUX: movl %ecx, ptr6@GOTOFF(%eax) ; LINUX: movl src6@GOTOFF(%eax), %ecx @@ -125,24 +125,24 @@ entry: ;; Test constant pool references. -define double @test7(i32 %a.u) nounwind { +define double @test6(i32 %a.u) nounwind { entry: %tmp = icmp eq i32 %a.u,0 %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02 ret double %retval -; LINUX: .LCPI7_0: +; LINUX: .LCPI6_0: -; LINUX: test7: -; LINUX: call .L7$pb -; LINUX: .L7$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref7-.L7$pb), -; LINUX: fldl .LCPI7_0@GOTOFF( +; LINUX: test6: +; LINUX: call .L6$pb +; LINUX: .L6$pb: +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), +; LINUX: fldl .LCPI6_0@GOTOFF( } ;; Test jump table references. -define void @test8(i32 %n.u) nounwind { +define void @test7(i32 %n.u) nounwind { entry: switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ] bb: @@ -185,19 +185,19 @@ bb12: tail call void(...)* @foo6() ret void -; LINUX: test8: -; LINUX: call .L8$pb -; LINUX: .L8$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref8-.L8$pb), -; LINUX: addl .LJTI8_0@GOTOFF( +; LINUX: test7: +; LINUX: call .L7$pb +; LINUX: .L7$pb: +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), +; LINUX: addl .LJTI7_0@GOTOFF( ; LINUX: jmpl * -; LINUX: .LJTI8_0: -; LINUX: .long .LBB8_2@GOTOFF -; LINUX: .long .LBB8_2@GOTOFF -; LINUX: .long .LBB8_7@GOTOFF -; LINUX: .long .LBB8_3@GOTOFF -; LINUX: .long .LBB8_7@GOTOFF +; LINUX: .LJTI7_0: +; LINUX: .long .LBB7_2@GOTOFF +; LINUX: .long .LBB7_8@GOTOFF +; LINUX: .long .LBB7_14@GOTOFF +; LINUX: .long .LBB7_9@GOTOFF +; LINUX: .long .LBB7_10@GOTOFF } declare void @foo1(...) diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll index b3750c1..31071bc 100644 --- a/test/CodeGen/X86/pic_jumptable.ll +++ b/test/CodeGen/X86/pic_jumptable.ll @@ -1,13 +1,18 @@ ; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2 +; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI' ; rdar://6971437 +; rdar://7738756 declare void @_Z3bari(i32) define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind { entry: +; CHECK: L0$pb +; CHECK-NOT: leal +; CHECK: Ltmp0 = LJTI0_0-L0$pb +; CHECK-NEXT: addl Ltmp0(%eax,%ecx,4) +; CHECK-NEXT: jmpl *%eax %Y_addr = alloca i32 ; <i32*> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 %Y, i32* %Y_addr diff --git a/test/CodeGen/X86/pmul.ll b/test/CodeGen/X86/pmul.ll index e2746a8..bf5229a 100644 --- a/test/CodeGen/X86/pmul.ll +++ b/test/CodeGen/X86/pmul.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 > %t ; RUN: grep pmul %t | count 12 -; RUN: grep mov %t | count 12 +; RUN: grep mov %t | count 11 define <4 x i32> @a(<4 x i32> %i) nounwind { %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 > diff --git a/test/CodeGen/X86/pmulld.ll b/test/CodeGen/X86/pmulld.ll new file mode 100644 index 0000000..3ef5941 --- /dev/null +++ b/test/CodeGen/X86/pmulld.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse41 -asm-verbose=0 | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: test1: +; CHECK-NEXT: pmulld + %C = mul <4 x i32> %A, %B + ret <4 x i32> %C +} + +define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind { +; CHECK: test1a: +; CHECK-NEXT: pmulld + %B = load <4 x i32>* %Bp + %C = mul <4 x i32> %A, %B + ret <4 x i32> %C +} diff --git a/test/CodeGen/X86/postalloc-coalescing.ll b/test/CodeGen/X86/postalloc-coalescing.ll index a171436..fe6f521 100644 --- a/test/CodeGen/X86/postalloc-coalescing.ll +++ b/test/CodeGen/X86/postalloc-coalescing.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | grep mov | count 3 -define fastcc i32 @_Z18yy_get_next_bufferv() { +define fastcc i32 @_Z18yy_get_next_bufferv() nounwind { entry: br label %bb131 diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll new file mode 100644 index 0000000..97cc7b4 --- /dev/null +++ b/test/CodeGen/X86/postra-licm.ll @@ -0,0 +1,185 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-32 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-64 + +; MachineLICM should be able to hoist loop invariant reload out of the loop. +; rdar://7233099 + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } +%struct.epoch_t = type { %struct.trans_t*, %struct.trans_t*, i32, i32, i32, i32, i32 } +%struct.trans_t = type { i32, i32, i32, i8* } + +@.str12 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1] +@.str19 = external constant [7 x i8], align 1 ; <[7 x i8]*> [#uses=1] +@.str24 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] + +define i32 @t1(i32 %c, i8** nocapture %v) nounwind ssp { +; X86-32: t1: +entry: + br i1 undef, label %bb, label %bb3 + +bb: ; preds = %entry + unreachable + +bb3: ; preds = %entry + br i1 undef, label %bb.i, label %bb.nph41 + +bb.i: ; preds = %bb3 + unreachable + +bb.nph41: ; preds = %bb3 + %0 = call %struct.FILE* @"\01_fopen$UNIX2003"(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str12, i32 0, i32 0)) nounwind ; <%struct.FILE*> [#uses=3] + br i1 undef, label %bb4, label %bb5.preheader + +bb5.preheader: ; preds = %bb.nph41 + br label %bb5 + +bb4: ; preds = %bb.nph41 + unreachable + +bb5: ; preds = %bb5, %bb5.preheader + br i1 undef, label %bb7, label %bb5 + +bb7: ; preds = %bb5 + br i1 undef, label %bb9, label %bb12 + +bb9: ; preds = %bb7 + unreachable + +bb12: ; preds = %bb7 + br i1 undef, label %bb16, label %bb22 + +bb16: ; preds = %bb12 + unreachable + +bb22: ; preds = %bb12 + br label %bb.i1 + +bb.i1: ; preds = %bb.i1, %bb22 + %1 = icmp eq i8 undef, 69 ; <i1> [#uses=1] + br i1 %1, label %imix_test.exit, label %bb.i1 + +imix_test.exit: ; preds = %bb.i1 + br i1 undef, label %bb23, label %bb26.preheader + +bb26.preheader: ; preds = %imix_test.exit + br i1 undef, label %bb28, label %bb30 + +bb23: ; preds = %imix_test.exit + unreachable +; X86-32: %bb26.preheader.bb28_crit_edge +; X86-32: movl -16(%ebp), +; X86-32-NEXT: .align 4 +; X86-32-NEXT: %bb28 + +bb28: ; preds = %bb28, %bb26.preheader + %counter.035 = phi i32 [ %3, %bb28 ], [ 0, %bb26.preheader ] ; <i32> [#uses=2] + %tmp56 = shl i32 %counter.035, 2 ; <i32> [#uses=0] + %2 = call i8* @fgets(i8* undef, i32 50, %struct.FILE* %0) nounwind ; <i8*> [#uses=0] + %3 = add nsw i32 %counter.035, 1 ; <i32> [#uses=1] + %4 = call i32 @feof(%struct.FILE* %0) nounwind ; <i32> [#uses=0] + br label %bb28 + +bb30: ; preds = %bb26.preheader + %5 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([7 x i8]* @.str19, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] + br i1 undef, label %bb34, label %bb70 + +bb32.loopexit: ; preds = %bb45 + %6 = icmp eq i32 undef, 0 ; <i1> [#uses=1] + %indvar.next55 = add i32 %indvar54, 1 ; <i32> [#uses=1] + br i1 %6, label %bb34, label %bb70 + +bb34: ; preds = %bb32.loopexit, %bb30 + %indvar54 = phi i32 [ %indvar.next55, %bb32.loopexit ], [ 0, %bb30 ] ; <i32> [#uses=3] + br i1 false, label %bb35, label %bb39.preheader + +bb35: ; preds = %bb34 + unreachable + +bb39.preheader: ; preds = %bb34 + %7 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 3 ; <i32*> [#uses=1] + %8 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 2 ; <i32*> [#uses=0] + br i1 false, label %bb42, label %bb45 + +bb42: ; preds = %bb39.preheader + unreachable + +bb45: ; preds = %bb39.preheader + %9 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([4 x i8]* @.str24, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] + br i1 false, label %bb47, label %bb32.loopexit + +bb47: ; preds = %bb45 + %10 = load i32* %7, align 4 ; <i32> [#uses=0] + unreachable + +bb70: ; preds = %bb32.loopexit, %bb30 + br i1 undef, label %bb78, label %bb76 + +bb76: ; preds = %bb70 + unreachable + +bb78: ; preds = %bb70 + br i1 undef, label %bb83, label %bb79 + +bb79: ; preds = %bb78 + unreachable + +bb83: ; preds = %bb78 + call void @rewind(%struct.FILE* %0) nounwind + unreachable +} + +declare %struct.FILE* @"\01_fopen$UNIX2003"(i8*, i8*) + +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind + +declare void @rewind(%struct.FILE* nocapture) nounwind + +declare i32 @feof(%struct.FILE* nocapture) nounwind + +declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly + +@map_4_to_16 = external constant [16 x i16], align 32 ; <[16 x i16]*> [#uses=2] + +define void @t2(i8* nocapture %bufp, i8* nocapture %data, i32 %dsize) nounwind ssp { +; X86-64: t2: +entry: + br i1 undef, label %return, label %bb.nph + +bb.nph: ; preds = %entry +; X86-64: movq _map_4_to_16@GOTPCREL(%rip) +; X86-64: .align 4 + %tmp5 = zext i32 undef to i64 ; <i64> [#uses=1] + %tmp6 = add i64 %tmp5, 1 ; <i64> [#uses=1] + %tmp11 = shl i64 undef, 1 ; <i64> [#uses=1] + %tmp14 = mul i64 undef, 3 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %tmp9 = mul i64 undef, undef ; <i64> [#uses=2] + %tmp12 = add i64 %tmp11, %tmp9 ; <i64> [#uses=1] + %scevgep13 = getelementptr i8* %bufp, i64 %tmp12 ; <i8*> [#uses=1] + %tmp15 = add i64 %tmp14, %tmp9 ; <i64> [#uses=1] + %scevgep16 = getelementptr i8* %bufp, i64 %tmp15 ; <i8*> [#uses=1] + %0 = load i8* undef, align 1 ; <i8> [#uses=1] + %1 = zext i8 %0 to i32 ; <i32> [#uses=1] + %2 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 0 ; <i16*> [#uses=1] + %3 = load i16* %2, align 2 ; <i16> [#uses=1] + %4 = trunc i16 %3 to i8 ; <i8> [#uses=1] + store i8 %4, i8* undef, align 1 + %5 = and i32 %1, 15 ; <i32> [#uses=1] + %6 = zext i32 %5 to i64 ; <i64> [#uses=1] + %7 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 %6 ; <i16*> [#uses=1] + %8 = load i16* %7, align 2 ; <i16> [#uses=2] + %9 = lshr i16 %8, 8 ; <i16> [#uses=1] + %10 = trunc i16 %9 to i8 ; <i8> [#uses=1] + store i8 %10, i8* %scevgep13, align 1 + %11 = trunc i16 %8 to i8 ; <i8> [#uses=1] + store i8 %11, i8* %scevgep16, align 1 + %exitcond = icmp eq i64 undef, %tmp6 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index 0760e4c..27047df 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5 +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s ; PR2659 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @@ -13,6 +14,11 @@ forcond.preheader: ; preds = %entry %cmp44 = icmp eq i32 %k, 0 ; <i1> [#uses=1] br i1 %cmp44, label %afterfor, label %forbody +; CHECK: %forcond.preheader.forbody_crit_edge +; CHECK: movl $1 +; CHECK-NOT: xorl +; CHECK-NEXT: movl $1 + ifthen: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/X86/pre-split6.ll b/test/CodeGen/X86/pre-split6.ll index d38e630..837e238 100644 --- a/test/CodeGen/X86/pre-split6.ll +++ b/test/CodeGen/X86/pre-split6.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split | grep {divsd 8} | count 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split | grep {divsd 24} | count 1 @current_surfaces.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/X86/tailcall2.ll b/test/CodeGen/X86/sibcall.ll index 90315fd..8e52a7c 100644 --- a/test/CodeGen/X86/tailcall2.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -57,11 +57,11 @@ define void @t5(void ()* nocapture %x) nounwind ssp { entry: ; 32: t5: ; 32-NOT: call -; 32: jmpl * +; 32: jmpl *4(%esp) ; 64: t5: ; 64-NOT: call -; 64: jmpq * +; 64: jmpq *%rdi tail call void %x() nounwind ret void } @@ -215,4 +215,101 @@ entry: ret %struct.ns* %0 } +; rdar://6195379 +; llvm can't do sibcall for this in 32-bit mode (yet). declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp + +%struct.__block_descriptor = type { i64, i64 } +%struct.__block_descriptor_withcopydispose = type { i64, i64, i8*, i8* } +%struct.__block_literal_1 = type { i8*, i32, i32, i8*, %struct.__block_descriptor* } +%struct.__block_literal_2 = type { i8*, i32, i32, i8*, %struct.__block_descriptor_withcopydispose*, void ()* } + +define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp { +entry: +; 64: t14: +; 64: movq 32(%rdi) +; 64-NOT: movq 16(%rdi) +; 64: jmpq *16(%rdi) + %0 = getelementptr inbounds %struct.__block_literal_2* %.block_descriptor, i64 0, i32 5 ; <void ()**> [#uses=1] + %1 = load void ()** %0, align 8 ; <void ()*> [#uses=2] + %2 = bitcast void ()* %1 to %struct.__block_literal_1* ; <%struct.__block_literal_1*> [#uses=1] + %3 = getelementptr inbounds %struct.__block_literal_1* %2, i64 0, i32 3 ; <i8**> [#uses=1] + %4 = load i8** %3, align 8 ; <i8*> [#uses=1] + %5 = bitcast i8* %4 to void (i8*)* ; <void (i8*)*> [#uses=1] + %6 = bitcast void ()* %1 to i8* ; <i8*> [#uses=1] + tail call void %5(i8* %6) nounwind + ret void +} + +; rdar://7726868 +%struct.foo = type { [4 x i32] } + +define void @t15(%struct.foo* noalias sret %agg.result) nounwind { +; 32: t15: +; 32: call {{_?}}f +; 32: ret $4 + +; 64: t15: +; 64: callq {{_?}}f +; 64: ret + tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind + ret void +} + +declare void @f(%struct.foo* noalias sret) nounwind + +define void @t16() nounwind ssp { +entry: +; 32: t16: +; 32: call {{_?}}bar4 +; 32: fstp + +; 64: t16: +; 64: jmp {{_?}}bar4 + %0 = tail call double @bar4() nounwind + ret void +} + +declare double @bar4() + +; rdar://6283267 +define void @t17() nounwind ssp { +entry: +; 32: t17: +; 32: jmp {{_?}}bar5 + +; 64: t17: +; 64: xorb %al, %al +; 64: jmp {{_?}}bar5 + tail call void (...)* @bar5() nounwind + ret void +} + +declare void @bar5(...) + +; rdar://7774847 +define void @t18() nounwind ssp { +entry: +; 32: t18: +; 32: call {{_?}}bar6 +; 32: fstp %st(0) + +; 64: t18: +; 64: xorb %al, %al +; 64: jmp {{_?}}bar6 + %0 = tail call double (...)* @bar6() nounwind + ret void +} + +declare double @bar6(...) + +define void @t19() alignstack(32) nounwind { +entry: +; CHECK: t19: +; CHECK: andl $-32 +; CHECK: call {{_?}}foo + tail call void @foo() nounwind + ret void +} + +declare void @foo() diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 01d7373..031c01e 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -61,9 +61,9 @@ entry: ; Codegen should hoist and CSE these constants. ; CHECK: vv: -; CHECK: LCPI4_0(%rip), %xmm0 -; CHECK: LCPI4_1(%rip), %xmm1 -; CHECK: LCPI4_2(%rip), %xmm2 +; CHECK: LCPI3_0(%rip), %xmm0 +; CHECK: LCPI3_1(%rip), %xmm1 +; CHECK: LCPI3_2(%rip), %xmm2 ; CHECK: align ; CHECK-NOT: LCPI ; CHECK: ret diff --git a/test/CodeGen/X86/small-byval-memcpy.ll b/test/CodeGen/X86/small-byval-memcpy.ll index 9ec9182e..1b596b5 100644 --- a/test/CodeGen/X86/small-byval-memcpy.ll +++ b/test/CodeGen/X86/small-byval-memcpy.ll @@ -1,7 +1,5 @@ -; RUN: llc < %s | not grep movs - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-apple-darwin8" +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 | grep movsd | count 8 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=nehalem | grep movups | count 2 define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 }* byval align 4 %z) nounwind { entry: diff --git a/test/CodeGen/X86/sse-align-12.ll b/test/CodeGen/X86/sse-align-12.ll index 4f025b9..118e393 100644 --- a/test/CodeGen/X86/sse-align-12.ll +++ b/test/CodeGen/X86/sse-align-12.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: grep unpck %t | count 2 -; RUN: grep shuf %t | count 2 -; RUN: grep ps %t | count 4 -; RUN: grep pd %t | count 4 -; RUN: grep movup %t | count 4 +; RUN: llc < %s -march=x86-64 | FileCheck %s +; CHECK: a: +; CHECK: movdqu +; CHECK: pshufd define <4 x float> @a(<4 x float>* %y) nounwind { %x = load <4 x float>* %y, align 4 %a = extractelement <4 x float> %x, i32 0 @@ -17,6 +15,10 @@ define <4 x float> @a(<4 x float>* %y) nounwind { %s = insertelement <4 x float> %r, float %a, i32 3 ret <4 x float> %s } + +; CHECK: b: +; CHECK: movups +; CHECK: unpckhps define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind { %x = load <4 x float>* %y, align 4 %a = extractelement <4 x float> %x, i32 2 @@ -29,6 +31,10 @@ define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind { %s = insertelement <4 x float> %r, float %b, i32 3 ret <4 x float> %s } + +; CHECK: c: +; CHECK: movupd +; CHECK: shufpd define <2 x double> @c(<2 x double>* %y) nounwind { %x = load <2 x double>* %y, align 8 %a = extractelement <2 x double> %x, i32 0 @@ -37,6 +43,10 @@ define <2 x double> @c(<2 x double>* %y) nounwind { %r = insertelement <2 x double> %p, double %a, i32 1 ret <2 x double> %r } + +; CHECK: d: +; CHECK: movupd +; CHECK: unpckhpd define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind { %x = load <2 x double>* %y, align 8 %a = extractelement <2 x double> %x, i32 1 diff --git a/test/CodeGen/X86/sse-align-6.ll b/test/CodeGen/X86/sse-align-6.ll index 0bbf422..fcea1b1 100644 --- a/test/CodeGen/X86/sse-align-6.ll +++ b/test/CodeGen/X86/sse-align-6.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep movups | count 1 +; RUN: llc < %s -march=x86-64 | grep movdqu | count 1 define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind { %t = load <2 x i64>* %p, align 8 diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll index f2b8010..20b8eac 100644 --- a/test/CodeGen/X86/sse2.ll +++ b/test/CodeGen/X86/sse2.ll @@ -10,10 +10,10 @@ define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ; CHECK: t1: ; CHECK: movl 8(%esp), %eax -; CHECK-NEXT: movl 4(%esp), %ecx ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movlpd 12(%esp), %xmm0 -; CHECK-NEXT: movapd %xmm0, (%ecx) +; CHECK-NEXT: movl 4(%esp), %eax +; CHECK-NEXT: movapd %xmm0, (%eax) ; CHECK-NEXT: ret } @@ -26,9 +26,9 @@ define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ; CHECK: t2: ; CHECK: movl 8(%esp), %eax -; CHECK-NEXT: movl 4(%esp), %ecx ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movhpd 12(%esp), %xmm0 -; CHECK-NEXT: movapd %xmm0, (%ecx) +; CHECK-NEXT: movl 4(%esp), %eax +; CHECK-NEXT: movapd %xmm0, (%eax) ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 921161e..b969ecb 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -17,10 +17,10 @@ entry: ; X64: t0: ; X64: movddup (%rsi), %xmm0 -; X64: xorl %eax, %eax ; X64: pshuflw $0, %xmm0, %xmm0 +; X64: xorl %eax, %eax ; X64: pinsrw $0, %eax, %xmm0 -; X64: movaps %xmm0, (%rdi) +; X64: movdqa %xmm0, (%rdi) ; X64: ret } @@ -32,7 +32,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; X64: t1: ; X64: movl (%rsi), %eax -; X64: movaps (%rdi), %xmm0 +; X64: movdqa (%rdi), %xmm0 ; X64: pinsrw $0, %eax, %xmm0 ; X64: ret } @@ -66,7 +66,7 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64: pshufhw $100, %xmm0, %xmm2 ; X64: pinsrw $1, %eax, %xmm2 ; X64: pextrw $1, %xmm0, %eax -; X64: movaps %xmm2, %xmm0 +; X64: movdqa %xmm2, %xmm0 ; X64: pinsrw $4, %eax, %xmm0 ; X64: ret } @@ -122,7 +122,7 @@ define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind { ; X64: t8: ; X64: pshuflw $-58, (%rsi), %xmm0 ; X64: pshufhw $-58, %xmm0, %xmm0 -; X64: movaps %xmm0, (%rdi) +; X64: movdqa %xmm0, (%rdi) ; X64: ret } @@ -169,11 +169,11 @@ define internal void @t10() nounwind { ret void ; X64: t10: ; X64: pextrw $4, %xmm0, %eax -; X64: pextrw $6, %xmm0, %edx ; X64: movlhps %xmm1, %xmm1 ; X64: pshuflw $8, %xmm1, %xmm1 ; X64: pinsrw $2, %eax, %xmm1 -; X64: pinsrw $3, %edx, %xmm1 +; X64: pextrw $6, %xmm0, %eax +; X64: pinsrw $3, %eax, %xmm1 } @@ -184,8 +184,8 @@ entry: ret <8 x i16> %tmp7 ; X64: t11: -; X64: movlhps %xmm0, %xmm0 ; X64: movd %xmm1, %eax +; X64: movlhps %xmm0, %xmm0 ; X64: pshuflw $1, %xmm0, %xmm0 ; X64: pinsrw $1, %eax, %xmm0 ; X64: ret @@ -198,8 +198,8 @@ entry: ret <8 x i16> %tmp9 ; X64: t12: -; X64: movlhps %xmm0, %xmm0 ; X64: pextrw $3, %xmm1, %eax +; X64: movlhps %xmm0, %xmm0 ; X64: pshufhw $3, %xmm0, %xmm0 ; X64: pinsrw $5, %eax, %xmm0 ; X64: ret diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll index a734c05..ef66d1a 100644 --- a/test/CodeGen/X86/sse41.ll +++ b/test/CodeGen/X86/sse41.ll @@ -123,11 +123,11 @@ define float @ext_1(<4 x float> %v) nounwind { ; X32: _ext_1: ; X32: pshufd $3, %xmm0, %xmm0 -; X32: addss LCPI8_0, %xmm0 +; X32: addss LCPI7_0, %xmm0 ; X64: _ext_1: ; X64: pshufd $3, %xmm0, %xmm0 -; X64: addss LCPI8_0(%rip), %xmm0 +; X64: addss LCPI7_0(%rip), %xmm0 } define float @ext_2(<4 x float> %v) nounwind { %s = extractelement <4 x float> %v, i32 3 diff --git a/test/CodeGen/X86/sse42.ll b/test/CodeGen/X86/sse42.ll index c9c4d01..1723909 100644 --- a/test/CodeGen/X86/sse42.ll +++ b/test/CodeGen/X86/sse42.ll @@ -9,10 +9,10 @@ define i32 @crc32_8(i32 %a, i8 %b) nounwind { %tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b) ret i32 %tmp ; X32: _crc32_8: -; X32: crc32 8(%esp), %eax +; X32: crc32b 8(%esp), %eax ; X64: _crc32_8: -; X64: crc32 %sil, %eax +; X64: crc32b %sil, %eax } @@ -20,10 +20,10 @@ define i32 @crc32_16(i32 %a, i16 %b) nounwind { %tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b) ret i32 %tmp ; X32: _crc32_16: -; X32: crc32 8(%esp), %eax +; X32: crc32w 8(%esp), %eax ; X64: _crc32_16: -; X64: crc32 %si, %eax +; X64: crc32w %si, %eax } @@ -31,8 +31,8 @@ define i32 @crc32_32(i32 %a, i32 %b) nounwind { %tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b) ret i32 %tmp ; X32: _crc32_32: -; X32: crc32 8(%esp), %eax +; X32: crc32l 8(%esp), %eax ; X64: _crc32_32: -; X64: crc32 %esi, %eax +; X64: crc32l %esi, %eax } diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll index 42e7a39..001a540 100644 --- a/test/CodeGen/X86/stack-color-with-reg.ll +++ b/test/CodeGen/X86/stack-color-with-reg.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t -; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 8 +; RUN: grep asm-printer %t | grep 166 +; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll new file mode 100644 index 0000000..a656697 --- /dev/null +++ b/test/CodeGen/X86/store-narrow.ll @@ -0,0 +1,127 @@ +; rdar://7860110 +; RUN: llc < %s | FileCheck %s -check-prefix=X64 +; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=X32 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.2" + +define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -256 ; 0xFFFFFF00 + %C = zext i8 %a1 to i32 + %D = or i32 %C, %B + store i32 %D, i32* %a0, align 4 + ret void + +; X64: test1: +; X64: movb %sil, (%rdi) + +; X32: test1: +; X32: movb 8(%esp), %al +; X32: movb %al, (%{{.*}}) +} + +define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -65281 ; 0xFFFF00FF + %C = zext i8 %a1 to i32 + %CS = shl i32 %C, 8 + %D = or i32 %B, %CS + store i32 %D, i32* %a0, align 4 + ret void +; X64: test2: +; X64: movb %sil, 1(%rdi) + +; X32: test2: +; X32: movb 8(%esp), %al +; X32: movb %al, 1(%{{.*}}) +} + +define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -65536 ; 0xFFFF0000 + %C = zext i16 %a1 to i32 + %D = or i32 %B, %C + store i32 %D, i32* %a0, align 4 + ret void +; X64: test3: +; X64: movw %si, (%rdi) + +; X32: test3: +; X32: movw 8(%esp), %ax +; X32: movw %ax, (%{{.*}}) +} + +define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, 65535 ; 0x0000FFFF + %C = zext i16 %a1 to i32 + %CS = shl i32 %C, 16 + %D = or i32 %B, %CS + store i32 %D, i32* %a0, align 4 + ret void +; X64: test4: +; X64: movw %si, 2(%rdi) + +; X32: test4: +; X32: movw 8(%esp), %ax +; X32: movw %ax, 2(%{{.*}}) +} + +define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i64* %a0, align 4 + %B = and i64 %A, -4294901761 ; 0xFFFFFFFF0000FFFF + %C = zext i16 %a1 to i64 + %CS = shl i64 %C, 16 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret void +; X64: test5: +; X64: movw %si, 2(%rdi) + +; X32: test5: +; X32: movw 8(%esp), %ax +; X32: movw %ax, 2(%{{.*}}) +} + +define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i64* %a0, align 4 + %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF + %C = zext i8 %a1 to i64 + %CS = shl i64 %C, 40 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret void +; X64: test6: +; X64: movb %sil, 5(%rdi) + + +; X32: test6: +; X32: movb 8(%esp), %al +; X32: movb %al, 5(%{{.*}}) +} + +define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind { +entry: + %OtherLoad = load i32 *%P2 + %A = load i64* %a0, align 4 + %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF + %C = zext i8 %a1 to i64 + %CS = shl i64 %C, 40 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret i32 %OtherLoad +; X64: test7: +; X64: movb %sil, 5(%rdi) + + +; X32: test7: +; X32: movb 8(%esp), %cl +; X32: movb %cl, 5(%{{.*}}) +} + diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 7b21e1b..4d93bd7 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -110,16 +110,16 @@ altret: ; CHECK: dont_merge_oddly: ; CHECK-NOT: ret ; CHECK: ucomiss %xmm1, %xmm2 -; CHECK-NEXT: jbe .LBB3_3 +; CHECK-NEXT: jbe .LBB2_3 ; CHECK-NEXT: ucomiss %xmm0, %xmm1 -; CHECK-NEXT: ja .LBB3_4 -; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ja .LBB2_4 +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: ucomiss %xmm0, %xmm2 -; CHECK-NEXT: jbe .LBB3_2 -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: jbe .LBB2_2 +; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: xorb %al, %al ; CHECK-NEXT: ret @@ -153,19 +153,19 @@ bb30: ; an unconditional jump to complete a two-way conditional branch. ; CHECK: c_expand_expr_stmt: -; CHECK: jmp .LBB4_7 -; CHECK-NEXT: .LBB4_12: +; CHECK: jmp .LBB3_7 +; CHECK-NEXT: .LBB3_12: ; CHECK-NEXT: movq 8(%rax), %rax ; CHECK-NEXT: movb 16(%rax), %al ; CHECK-NEXT: cmpb $16, %al -; CHECK-NEXT: je .LBB4_6 +; CHECK-NEXT: je .LBB3_6 ; CHECK-NEXT: cmpb $23, %al -; CHECK-NEXT: je .LBB4_6 -; CHECK-NEXT: jmp .LBB4_15 -; CHECK-NEXT: .LBB4_14: +; CHECK-NEXT: je .LBB3_6 +; CHECK-NEXT: jmp .LBB3_15 +; CHECK-NEXT: .LBB3_14: ; CHECK-NEXT: cmpb $23, %bl -; CHECK-NEXT: jne .LBB4_15 -; CHECK-NEXT: .LBB4_15: +; CHECK-NEXT: jne .LBB3_15 +; CHECK-NEXT: .LBB3_15: %0 = type { %struct.rtx_def* } %struct.lang_decl = type opaque @@ -275,7 +275,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind ; CHECK: foo: ; CHECK: callq func -; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: .LBB4_2: ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: ret diff --git a/test/CodeGen/X86/tailcall-largecode.ll b/test/CodeGen/X86/tailcall-largecode.ll index 8ddc405..c7070f2 100644 --- a/test/CodeGen/X86/tailcall-largecode.ll +++ b/test/CodeGen/X86/tailcall-largecode.ll @@ -20,7 +20,7 @@ define fastcc i32 @indirect_manyargs(i32(i32,i32,i32,i32,i32,i32,i32)* %target) ; CHECK: subq $8, %rsp ; Put the call target into R11, which won't be clobbered while restoring ; callee-saved registers and won't be used for passing arguments. -; CHECK: movq %rdi, %r11 +; CHECK: movq %rdi, %rax ; Pass the stack argument. ; CHECK: movl $7, 16(%rsp) ; Pass the register arguments, in the right registers. @@ -33,7 +33,7 @@ define fastcc i32 @indirect_manyargs(i32(i32,i32,i32,i32,i32,i32,i32)* %target) ; Adjust the stack to "return". ; CHECK: addq $8, %rsp ; And tail-call to the target. -; CHECK: jmpq *%r11 # TAILCALL +; CHECK: jmpq *%rax # TAILCALL %res = tail call fastcc i32 %target(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7) ret i32 %res @@ -60,11 +60,11 @@ define fastcc i32 @direct_manyargs() { ; the jmp instruction. Put it into R11, which won't be clobbered ; while restoring callee-saved registers and won't be used for passing ; arguments. -; CHECK: movabsq $manyargs_callee, %r11 +; CHECK: movabsq $manyargs_callee, %rax ; Adjust the stack to "return". ; CHECK: addq $8, %rsp ; And tail-call to the target. -; CHECK: jmpq *%r11 # TAILCALL +; CHECK: jmpq *%rax # TAILCALL %res = tail call fastcc i32 @manyargs_callee(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7) ret i32 %res diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll index 3841f51..4ec127f 100644 --- a/test/CodeGen/X86/tailcallfp2.ll +++ b/test/CodeGen/X86/tailcallfp2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax} +; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%edx} declare i32 @putchar(i32) diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index b61803d..b26097f 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -mcpu=core2 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck -check-prefix=I386 %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -mcpu=core2 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck -check-prefix=CORE2 %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -mcpu=corei7 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck -check-prefix=COREI7 %s @.str1 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8 @.str3 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, 2'ND STRING\00", align 8 @@ -11,7 +13,13 @@ entry: bb: %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0 call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1) -; CHECK: movups _.str3 +; I386: call {{_?}}memcpy + +; CORE2: movabsq +; CORE2: movabsq +; CORE2: movabsq + +; COREI7: movups _.str3 br label %bb return: @@ -20,8 +28,9 @@ return: declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind -; CHECK: .align 3 -; CHECK-NEXT: _.str1: -; CHECK-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" -; CHECK: .align 3 -; CHECK-NEXT: _.str3: +; CORE2: .section +; CORE2: .align 3 +; CORE2-NEXT: _.str1: +; CORE2-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" +; CORE2: .align 3 +; CORE2-NEXT: _.str3: diff --git a/test/CodeGen/X86/unreachable-loop-sinking.ll b/test/CodeGen/X86/unreachable-loop-sinking.ll new file mode 100644 index 0000000..35f6917 --- /dev/null +++ b/test/CodeGen/X86/unreachable-loop-sinking.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s +; PR6777 + +; MachineSink shouldn't try to sink code in unreachable blocks, as it's +; not worthwhile, and there are corner cases which it doesn't handle. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define double @fn1(i8* %arg, i64 %arg1) { +Entry: + br i1 undef, label %Body, label %Exit + +Exit: ; preds = %Brancher7, %Entry + ret double undef + +Body: ; preds = %Entry + br i1 false, label %Brancher7, label %Body3 + +Body3: ; preds = %Body6, %Body3, %Body + br label %Body3 + +Body6: ; preds = %Brancher7 + %tmp = fcmp oeq double 0xC04FBB2E40000000, undef ; <i1> [#uses=1] + br i1 %tmp, label %Body3, label %Brancher7 + +Brancher7: ; preds = %Body6, %Body + %tmp2 = icmp ult i32 undef, 10 ; <i1> [#uses=1] + br i1 %tmp2, label %Body6, label %Exit +} diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll index c8c7257..39c9b77 100644 --- a/test/CodeGen/X86/vec_compare.ll +++ b/test/CodeGen/X86/vec_compare.ll @@ -15,7 +15,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test2: ; CHECK: pcmp ; CHECK: pcmp -; CHECK: xorps +; CHECK: pxor ; CHECK: ret %C = icmp sge <4 x i32> %A, %B %D = sext <4 x i1> %C to <4 x i32> @@ -25,7 +25,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test3: ; CHECK: pcmpgtd -; CHECK: movaps +; CHECK: movdqa ; CHECK: ret %C = icmp slt <4 x i32> %A, %B %D = sext <4 x i1> %C to <4 x i32> @@ -34,7 +34,7 @@ define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test4: -; CHECK: movaps +; CHECK: movdqa ; CHECK: pcmpgtd ; CHECK: ret %C = icmp ugt <4 x i32> %A, %B diff --git a/test/CodeGen/X86/vec_insert_4.ll b/test/CodeGen/X86/vec_insert-4.ll index 2c31e56..2c31e56 100644 --- a/test/CodeGen/X86/vec_insert_4.ll +++ b/test/CodeGen/X86/vec_insert-4.ll diff --git a/test/CodeGen/X86/vec_insert-9.ll b/test/CodeGen/X86/vec_insert-9.ll new file mode 100644 index 0000000..2e829df --- /dev/null +++ b/test/CodeGen/X86/vec_insert-9.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=x86 -mattr=+sse41 > %t +; RUN: grep pinsrd %t | count 2 + +define <4 x i32> @var_insert2(<4 x i32> %x, i32 %val, i32 %idx) nounwind { +entry: + %tmp3 = insertelement <4 x i32> undef, i32 %val, i32 0 ; <<4 x i32>> [#uses=1] + %tmp4 = insertelement <4 x i32> %tmp3, i32 %idx, i32 3 ; <<4 x i32>> [#uses=1] + ret <4 x i32> %tmp4 +} diff --git a/test/CodeGen/X86/vec_return.ll b/test/CodeGen/X86/vec_return.ll index 66762b4..676be9b 100644 --- a/test/CodeGen/X86/vec_return.ll +++ b/test/CodeGen/X86/vec_return.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 > %t -; RUN: grep xorps %t | count 1 +; RUN: grep pxor %t | count 1 ; RUN: grep movaps %t | count 1 ; RUN: not grep shuf %t diff --git a/test/CodeGen/X86/vec_set.ll b/test/CodeGen/X86/vec_set.ll index c316df8..7f5f8dd 100644 --- a/test/CodeGen/X86/vec_set.ll +++ b/test/CodeGen/X86/vec_set.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpckl | count 7 +; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep punpckl | count 7 define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1] diff --git a/test/CodeGen/X86/vec_shuffle-36.ll b/test/CodeGen/X86/vec_shuffle-36.ll index 1ea37c8..8090afc 100644 --- a/test/CodeGen/X86/vec_shuffle-36.ll +++ b/test/CodeGen/X86/vec_shuffle-36.ll @@ -13,4 +13,4 @@ define <8 x i16> @shuf7(<8 x i16> %t0) { ; CHECK: pshufd %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef > ret <8 x i16> %tmp10 -}
\ No newline at end of file +} diff --git a/test/CodeGen/X86/vec_shuffle-7.ll b/test/CodeGen/X86/vec_shuffle-7.ll index 4cdca09..64bd6a3 100644 --- a/test/CodeGen/X86/vec_shuffle-7.ll +++ b/test/CodeGen/X86/vec_shuffle-7.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t -; RUN: grep xorps %t | count 1 +; RUN: grep pxor %t | count 1 ; RUN: not grep shufps %t define void @test() { diff --git a/test/CodeGen/X86/vec_shuffle-9.ll b/test/CodeGen/X86/vec_shuffle-9.ll index fc16a26..0719586 100644 --- a/test/CodeGen/X86/vec_shuffle-9.ll +++ b/test/CodeGen/X86/vec_shuffle-9.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define <4 x i32> @test(i8** %ptr) { -; CHECK: xorps +; CHECK: pxor ; CHECK: punpcklbw ; CHECK: punpcklwd diff --git a/test/CodeGen/X86/vec_shuffle.ll b/test/CodeGen/X86/vec_shuffle.ll index c05b79a..2a48de2 100644 --- a/test/CodeGen/X86/vec_shuffle.ll +++ b/test/CodeGen/X86/vec_shuffle.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mcpu=core2 -o %t -; RUN: grep shufp %t | count 1 +; RUN: grep movq %t | count 1 +; RUN: grep pshufd %t | count 1 ; RUN: grep movupd %t | count 1 ; RUN: grep pshufhw %t | count 1 diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll index c8b2927..3bd3f7b 100644 --- a/test/CodeGen/X86/vec_ss_load_fold.ll +++ b/test/CodeGen/X86/vec_ss_load_fold.ll @@ -16,9 +16,9 @@ define i16 @test1(float %f) nounwind { %tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1] ret i16 %tmp69 ; CHECK: test1: -; CHECK: subss LCPI1_ -; CHECK: mulss LCPI1_ -; CHECK: minss LCPI1_ +; CHECK: subss LCPI0_ +; CHECK: mulss LCPI0_ +; CHECK: minss LCPI0_ } define i16 @test2(float %f) nounwind { @@ -31,9 +31,9 @@ define i16 @test2(float %f) nounwind { %tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1] ret i16 %tmp69 ; CHECK: test2: -; CHECK: addss LCPI2_ -; CHECK: mulss LCPI2_ -; CHECK: minss LCPI2_ +; CHECK: addss LCPI1_ +; CHECK: mulss LCPI1_ +; CHECK: minss LCPI1_ } declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) diff --git a/test/CodeGen/X86/vec_zero.ll b/test/CodeGen/X86/vec_zero.ll index ae5af58..4d1f056 100644 --- a/test/CodeGen/X86/vec_zero.ll +++ b/test/CodeGen/X86/vec_zero.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xorps | count 2 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; CHECK: xorps define void @foo(<4 x float>* %P) { %T = load <4 x float>* %P ; <<4 x float>> [#uses=1] %S = fadd <4 x float> zeroinitializer, %T ; <<4 x float>> [#uses=1] @@ -7,6 +8,7 @@ define void @foo(<4 x float>* %P) { ret void } +; CHECK: pxor define void @bar(<4 x i32>* %P) { %T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1] %S = add <4 x i32> zeroinitializer, %T ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/X86/vec_zero_cse.ll b/test/CodeGen/X86/vec_zero_cse.ll index 296378c..3b15d4c 100644 --- a/test/CodeGen/X86/vec_zero_cse.ll +++ b/test/CodeGen/X86/vec_zero_cse.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1 -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1 +; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 2 ; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 2 @M1 = external global <1 x i64> diff --git a/test/CodeGen/X86/widen_arith-5.ll b/test/CodeGen/X86/widen_arith-5.ll index f7f3408..bae5c54 100644 --- a/test/CodeGen/X86/widen_arith-5.ll +++ b/test/CodeGen/X86/widen_arith-5.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s -; CHECK: movaps +; CHECK: movdqa ; CHECK: pmulld ; CHECK: psubd diff --git a/test/CodeGen/X86/widen_cast-2.ll b/test/CodeGen/X86/widen_cast-2.ll index 1e626a2..14e8f75 100644 --- a/test/CodeGen/X86/widen_cast-2.ll +++ b/test/CodeGen/X86/widen_cast-2.ll @@ -2,7 +2,7 @@ ; CHECK: pextrd ; CHECK: pextrd ; CHECK: movd -; CHECK: movaps +; CHECK: movdqa ; bitcast v14i16 to v7i32 diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll index 11383fa..551704c 100644 --- a/test/CodeGen/X86/widen_load-2.ll +++ b/test/CodeGen/X86/widen_load-2.ll @@ -5,7 +5,7 @@ %i32vec3 = type <3 x i32> define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq @@ -24,22 +24,22 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq - %a = load %i32vec3* %ap - %b = load %i32vec3* %bp + %a = load %i32vec3* %ap, align 8 + %b = load %i32vec3* %bp, align 8 %x = add %i32vec3 %a, %b - store %i32vec3 %x, %i32vec3* %ret + store %i32vec3 %x, %i32vec3* %ret, align 8 ret void } %i32vec7 = type <7 x i32> define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddd ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq -; CHECK: movaps +; CHECK: movdqa %a = load %i32vec7* %ap, align 16 %b = load %i32vec7* %bp, align 16 %x = add %i32vec7 %a, %b @@ -49,15 +49,15 @@ define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { %i32vec12 = type <12 x i32> define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { -; CHECK: movaps -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddd ; CHECK: paddd ; CHECK: paddd -; CHECK: movaps -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa +; CHECK: movdqa %a = load %i32vec12* %ap, align 16 %b = load %i32vec12* %bp, align 16 %x = add %i32vec12 %a, %b @@ -68,7 +68,7 @@ define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { %i16vec3 = type <3 x i16> define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddw ; CHECK: movd ; CHECK: pextrw @@ -81,7 +81,7 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp %i16vec4 = type <4 x i16> define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddw ; CHECK: movq %a = load %i16vec4* %ap, align 16 @@ -93,12 +93,12 @@ define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp %i16vec12 = type <12 x i16> define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddw ; CHECK: paddw ; CHECK: movq -; CHECK: movaps +; CHECK: movdqa %a = load %i16vec12* %ap, align 16 %b = load %i16vec12* %bp, align 16 %x = add %i16vec12 %a, %b @@ -108,15 +108,15 @@ define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %i16vec18 = type <18 x i16> define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { -; CHECK: movaps -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddw ; CHECK: paddw ; CHECK: paddw ; CHECK: movd -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa %a = load %i16vec18* %ap, align 16 %b = load %i16vec18* %bp, align 16 %x = add %i16vec18 %a, %b @@ -127,7 +127,7 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %i8vec3 = type <3 x i8> define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddb ; CHECK: pextrb ; CHECK: movb @@ -140,8 +140,8 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no %i8vec31 = type <31 x i8> define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddb ; CHECK: paddb ; CHECK: movq @@ -152,4 +152,28 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp %x = add %i8vec31 %a, %b store %i8vec31 %x, %i8vec31* %ret, align 16 ret void -}
\ No newline at end of file +} + + +%i8vec3pack = type { <3 x i8>, i8 } +define %i8vec3pack @rot() nounwind { +; CHECK: shrb +entry: + %X = alloca %i8vec3pack, align 4 + %rot = alloca %i8vec3pack, align 4 + %result = alloca %i8vec3pack, align 4 + %storetmp = bitcast %i8vec3pack* %X to <3 x i8>* + store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp + %storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>* + store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1 + %tmp = load %i8vec3pack* %X + %extractVec = extractvalue %i8vec3pack %tmp, 0 + %tmp2 = load %i8vec3pack* %rot + %extractVec3 = extractvalue %i8vec3pack %tmp2, 0 + %shr = lshr <3 x i8> %extractVec, %extractVec3 + %storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>* + store <3 x i8> %shr, <3 x i8>* %storetmp4 + %tmp5 = load %i8vec3pack* %result + ret %i8vec3pack %tmp5 +} + diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll index 2d75c5d..34875ed 100644 --- a/test/CodeGen/X86/xor-icmp.ll +++ b/test/CodeGen/X86/xor-icmp.ll @@ -43,7 +43,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp { ; X32: cmpl ; X32: sete ; X32-NOT: xor -; X32: je +; X32: jne ; X64: t2: ; X64: testl @@ -51,7 +51,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp { ; X64: testl ; X64: sete ; X64-NOT: xor -; X64: je +; X64: jne entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] %1 = icmp eq i32 %y, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index 9bfff8a..f270d9d 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -7,7 +7,7 @@ define <4 x i32> @test1() nounwind { ret <4 x i32> %tmp ; X32: test1: -; X32: xorps %xmm0, %xmm0 +; X32: pxor %xmm0, %xmm0 ; X32: ret } diff --git a/test/CodeGen/XCore/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/XCore/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 0000000..f24e1d1 --- /dev/null +++ b/test/CodeGen/XCore/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=xcore -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index a1494ad..d062480 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -1,12 +1,59 @@ -; RUN: llc < %s -march=xcore -mcpu=xs1b-generic > %t1.s -; RUN: grep ladd %t1.s | count 2 -; RUN: grep lsub %t1.s | count 2 +; RUN: llc < %s -march=xcore | FileCheck %s define i64 @add64(i64 %a, i64 %b) { %result = add i64 %a, %b ret i64 %result } +; CHECK: add64 +; CHECK: ldc r11, 0 +; CHECK-NEXT: ladd r2, r0, r0, r2, r11 +; CHECK-NEXT: ladd r2, r1, r1, r3, r2 +; CHECK-NEXT: retsp 0 define i64 @sub64(i64 %a, i64 %b) { %result = sub i64 %a, %b ret i64 %result } +; CHECK: sub64 +; CHECK: ldc r11, 0 +; CHECK-NEXT: lsub r2, r0, r0, r2, r11 +; CHECK-NEXT: lsub r2, r1, r1, r3, r2 +; CHECK-NEXT: retsp 0 + +define i64 @maccu(i64 %a, i32 %b, i32 %c) { +entry: + %0 = zext i32 %b to i64 + %1 = zext i32 %c to i64 + %2 = mul i64 %1, %0 + %3 = add i64 %2, %a + ret i64 %3 +} +; CHECK: maccu: +; CHECK: maccu r1, r0, r3, r2 +; CHECK-NEXT: retsp 0 + +define i64 @maccs(i64 %a, i32 %b, i32 %c) { +entry: + %0 = sext i32 %b to i64 + %1 = sext i32 %c to i64 + %2 = mul i64 %1, %0 + %3 = add i64 %2, %a + ret i64 %3 +} +; CHECK: maccs: +; CHECK: maccs r1, r0, r3, r2 +; CHECK-NEXT: retsp 0 + +define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + %0 = zext i32 %a to i64 + %1 = zext i32 %b to i64 + %2 = zext i32 %c to i64 + %3 = zext i32 %d to i64 + %4 = mul i64 %1, %0 + %5 = add i64 %4, %2 + %6 = add i64 %5, %3 + ret i64 %6 +} +; CHECK: lmul: +; CHECK: lmul r1, r0, r1, r0, r2, r3 +; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/constants.ll b/test/CodeGen/XCore/constants.ll index 95fa11e..cad1a21 100644 --- a/test/CodeGen/XCore/constants.ll +++ b/test/CodeGen/XCore/constants.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -march=xcore -mcpu=xs1b-generic | FileCheck %s ; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4 -; CHECK: .LCPI1_0: +; CHECK: .LCPI0_0: ; CHECK: .long 12345678 ; CHECK: f: -; CHECK: ldw r0, cp[.LCPI1_0] +; CHECK: ldw r0, cp[.LCPI0_0] define i32 @f() { entry: ret i32 12345678 diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll index a8f00cc..9269002 100644 --- a/test/CodeGen/XCore/indirectbr.ll +++ b/test/CodeGen/XCore/indirectbr.ll @@ -38,7 +38,7 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; CHECK: ldap r11, .LBA3_foo_L5 +; CHECK: ldap r11, .Ltmp0 ; CHECK: stw r11, dp[nextaddr] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 diff --git a/test/CodeGen/XCore/ladd_lsub_combine.ll b/test/CodeGen/XCore/ladd_lsub_combine.ll new file mode 100644 index 0000000..a693ee2 --- /dev/null +++ b/test/CodeGen/XCore/ladd_lsub_combine.ll @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=xcore | FileCheck %s + +; Only needs one ladd +define i64 @f1(i32 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %x to i64 ; <i64> [#uses=1] + %1 = zext i32 %y to i64 ; <i64> [#uses=1] + %2 = add i64 %1, %0 ; <i64> [#uses=1] + ret i64 %2 +} +; CHECK: f1: +; CHECK: ldc r2, 0 +; CHECK-NEXT: ladd r1, r0, r1, r0, r2 +; CHECK-NEXT: retsp 0 + +; Only needs one lsub and one neg +define i64 @f2(i32 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %x to i64 ; <i64> [#uses=1] + %1 = zext i32 %y to i64 ; <i64> [#uses=1] + %2 = sub i64 %1, %0 ; <i64> [#uses=1] + ret i64 %2 +} +; CHECK: f2: +; CHECK: ldc r2, 0 +; CHECK-NEXT: lsub r1, r0, r1, r0, r2 +; CHECK-NEXT: neg r1, r1 +; CHECK-NEXT: retsp 0 + +; Should compile to one ladd and one add +define i64 @f3(i64 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %y to i64 ; <i64> [#uses=1] + %1 = add i64 %x, %0 ; <i64> [#uses=1] + ret i64 %1 +} +; CHECK: f3: +; CHECK: ldc r3, 0 +; CHECK-NEXT: ladd r2, r0, r0, r2, r3 +; CHECK-NEXT: add r1, r1, r2 +; CHECK-NEXT: retsp 0 + +; Should compile to one ladd and one add +define i64 @f4(i32 %x, i64 %y) nounwind { +entry: + %0 = zext i32 %x to i64 ; <i64> [#uses=1] + %1 = add i64 %0, %y ; <i64> [#uses=1] + ret i64 %1 +} +; CHECK: f4: +; CHECK: ldc r3, 0 +; CHECK-NEXT: ladd r1, r0, r0, r1, r3 +; CHECK-NEXT: add r1, r2, r1 +; CHECK-NEXT: retsp 0 + +; Should compile to one lsub and one sub +define i64 @f5(i64 %x, i32 %y) nounwind { +entry: + %0 = zext i32 %y to i64 ; <i64> [#uses=1] + %1 = sub i64 %x, %0 ; <i64> [#uses=1] + ret i64 %1 +} +; CHECK: f5: +; CHECK: ldc r3, 0 +; CHECK-NEXT: lsub r2, r0, r0, r2, r3 +; CHECK-NEXT: sub r1, r1, r2 +; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll new file mode 100644 index 0000000..1dc9471 --- /dev/null +++ b/test/CodeGen/XCore/mul64.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +define i64 @umul_lohi(i32 %a, i32 %b) { +entry: + %0 = zext i32 %a to i64 + %1 = zext i32 %b to i64 + %2 = mul i64 %1, %0 + ret i64 %2 +} +; CHECK: umul_lohi: +; CHECK: ldc r2, 0 +; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2 +; CHECK-NEXT: retsp 0 + +define i64 @smul_lohi(i32 %a, i32 %b) { +entry: + %0 = sext i32 %a to i64 + %1 = sext i32 %b to i64 + %2 = mul i64 %1, %0 + ret i64 %2 +} +; CHECK: smul_lohi: +; CHECK: ldc r2, 0 +; CHECK-NEXT: mov r3, r2 +; CHECK-NEXT: maccs r2, r3, r1, r0 +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: mov r1, r2 +; CHECK-NEXT: retsp 0 + +define i64 @mul64(i64 %a, i64 %b) { +entry: + %0 = mul i64 %a, %b + ret i64 %0 +} +; CHECK: mul64: +; CHECK: ldc r11, 0 +; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11 +; CHECK-NEXT: mul r0, r0, r3 +; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0 +; CHECK-NEXT: mov r0, r4 + +define i64 @mul64_2(i64 %a, i32 %b) { +entry: + %0 = zext i32 %b to i64 + %1 = mul i64 %a, %0 + ret i64 %1 +} +; CHECK: mul64_2: +; CHECK: ldc r3, 0 +; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3 +; CHECK-NEXT: mul r1, r1, r2 +; CHECK-NEXT: add r1, r3, r1 +; CHECK-NEXT: retsp 0 diff --git a/test/DebugInfo/2009-10-16-Phi.ll b/test/DebugInfo/2009-10-16-Phi.ll index fc03751..0f799e3 100644 --- a/test/DebugInfo/2009-10-16-Phi.ll +++ b/test/DebugInfo/2009-10-16-Phi.ll @@ -10,4 +10,4 @@ B2: ret i32 %0 } -!0 = metadata !{i32 42}
\ No newline at end of file +!0 = metadata !{i32 42} diff --git a/test/DebugInfo/2009-11-03-InsertExtractValue.ll b/test/DebugInfo/2009-11-03-InsertExtractValue.ll index d9a67d6..8782e44 100644 --- a/test/DebugInfo/2009-11-03-InsertExtractValue.ll +++ b/test/DebugInfo/2009-11-03-InsertExtractValue.ll @@ -3,9 +3,9 @@ !0 = metadata !{i32 42} define <{i32, i32}> @f1() { -; CHECK: !dbg !0 - %r = insertvalue <{ i32, i32 }> zeroinitializer, i32 4, 1, !dbg !0 -; CHECK: !dbg !0 - %e = extractvalue <{ i32, i32 }> %r, 0, !dbg !0 +; CHECK: !dbgx !0 + %r = insertvalue <{ i32, i32 }> zeroinitializer, i32 4, 1, !dbgx !0 +; CHECK: !dbgx !0 + %e = extractvalue <{ i32, i32 }> %r, 0, !dbgx !0 ret <{ i32, i32 }> %r } diff --git a/test/DebugInfo/2010-03-12-llc-crash.ll b/test/DebugInfo/2010-03-12-llc-crash.ll new file mode 100644 index 0000000..f6de234 --- /dev/null +++ b/test/DebugInfo/2010-03-12-llc-crash.ll @@ -0,0 +1,20 @@ +; RUN: llc -O0 < %s -o /dev/null +; llc should not crash on this invalid input. +; PR6588 +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define void @foo() { +entry: + call void @llvm.dbg.declare(metadata !{i32* undef}, metadata !0) + ret void +} + +!0 = metadata !{i32 524545, metadata !1, metadata !"sy", metadata !2, i32 890, metadata !7} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 892, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"qpainter.h", metadata !"QtGui", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 4, metadata !"splineeditor.cpp", metadata !"editor", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !5, metadata !"", metadata !5, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 524329, metadata !"splineeditor.cpp", metadata !"src", metadata !3} ; [ DW_TAG_file_type ] +!6 = metadata !{null} +!7 = metadata !{i32 524324, metadata !5, metadata !"int", metadata !5, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] + diff --git a/test/DebugInfo/2010-03-19-DbgDeclare.ll b/test/DebugInfo/2010-03-19-DbgDeclare.ll new file mode 100644 index 0000000..1f7a889 --- /dev/null +++ b/test/DebugInfo/2010-03-19-DbgDeclare.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | opt -verify -disable-output + +define void @Foo(i32 %a, i32 %b) { +entry: + call void @llvm.dbg.declare(metadata !{i32* null}, metadata !1) + ret void +} + +!0 = metadata !{i32 662302, i32 26, metadata !1, null} +!1 = metadata !{i32 4, metadata !"foo"} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone diff --git a/test/DebugInfo/2010-03-24-MemberFn.ll b/test/DebugInfo/2010-03-24-MemberFn.ll new file mode 100644 index 0000000..20c0b8e --- /dev/null +++ b/test/DebugInfo/2010-03-24-MemberFn.ll @@ -0,0 +1,62 @@ +; RUN: llc -O0 < %s | grep AT_decl_file | grep 2 +; Here _ZN1S3fooEv is defined in header file identified as AT_decl_file no. 2 in debug info. +%struct.S = type <{ i8 }> + +define i32 @_Z3barv() nounwind ssp { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %s1 = alloca %struct.S ; <%struct.S*> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.S* %s1}, metadata !0), !dbg !16 + %1 = call i32 @_ZN1S3fooEv(%struct.S* %s1) nounwind, !dbg !17 ; <i32> [#uses=1] + store i32 %1, i32* %0, align 4, !dbg !17 + %2 = load i32* %0, align 4, !dbg !17 ; <i32> [#uses=1] + store i32 %2, i32* %retval, align 4, !dbg !17 + br label %return, !dbg !17 + +return: ; preds = %entry + %retval1 = load i32* %retval, !dbg !17 ; <i32> [#uses=1] + ret i32 %retval1, !dbg !16 +} + +define linkonce_odr i32 @_ZN1S3fooEv(%struct.S* %this) nounwind ssp align 2 { +entry: + %this_addr = alloca %struct.S* ; <%struct.S**> [#uses=1] + %retval = alloca i32 ; <i32*> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.S** %this_addr}, metadata !18), !dbg !21 + store %struct.S* %this, %struct.S** %this_addr + br label %return, !dbg !21 + +return: ; preds = %entry + %retval1 = load i32* %retval, !dbg !21 ; <i32> [#uses=1] + ret i32 %retval1, !dbg !22 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{i32 524544, metadata !1, metadata !"s1", metadata !4, i32 3, metadata !9} ; [ DW_TAG_auto_variable ] +!1 = metadata !{i32 524299, metadata !2, i32 3, i32 0} ; [ DW_TAG_lexical_block ] +!2 = metadata !{i32 524299, metadata !3, i32 3, i32 0} ; [ DW_TAG_lexical_block ] +!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"bar", metadata !"bar", metadata !"_Z3barv", metadata !4, i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!4 = metadata !{i32 524329, metadata !"one.cc", metadata !"/tmp/", metadata !5} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 524305, i32 0, i32 4, metadata !"one.cc", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!7 = metadata !{metadata !8} +!8 = metadata !{i32 524324, metadata !4, metadata !"int", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 524307, metadata !4, metadata !"S", metadata !10, i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!10 = metadata !{i32 524329, metadata !"one.h", metadata !"/tmp/", metadata !5} ; [ DW_TAG_file_type ] +!11 = metadata !{metadata !12} +!12 = metadata !{i32 524334, i32 0, metadata !9, metadata !"foo", metadata !"foo", metadata !"_ZN1S3fooEv", metadata !10, i32 3, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, null} ; [ DW_TAG_subroutine_type ] +!14 = metadata !{metadata !8, metadata !15} +!15 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !9} ; [ DW_TAG_pointer_type ] +!16 = metadata !{i32 3, i32 0, metadata !1, null} +!17 = metadata !{i32 3, i32 0, metadata !3, null} +!18 = metadata !{i32 524545, metadata !12, metadata !"this", metadata !10, i32 3, metadata !19} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 524326, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !20} ; [ DW_TAG_const_type ] +!20 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] +!21 = metadata !{i32 3, i32 0, metadata !12, null} +!22 = metadata !{i32 3, i32 0, metadata !23, null} +!23 = metadata !{i32 524299, metadata !12, i32 3, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll b/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll new file mode 100644 index 0000000..9bb35fa --- /dev/null +++ b/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -o /dev/null + +define void @baz(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !0, metadata !1), !dbg !0 + ret void, !dbg !0 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{{ [0 x i8] }** undef} +!1 = metadata !{i32 524544, metadata !2, metadata !"x", metadata !4, i32 11, metadata !9} ; [ DW_TAG_auto_variable ] +!2 = metadata !{i32 524299, metadata !3, i32 8, i32 0} ; [ DW_TAG_lexical_block ] +!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"baz", metadata !"baz", metadata !"baz", metadata !4, i32 8, metadata !6, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!4 = metadata !{i32 524329, metadata !"2007-12-VarArrayDebug.c", metadata !"/Users/sabre/llvm/test/FrontendC/", metadata !5} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 524305, i32 0, i32 1, metadata !"2007-12-VarArrayDebug.c", metadata !"/Users/sabre/llvm/test/FrontendC/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!7 = metadata !{null, metadata !8} +!8 = metadata !{i32 524324, metadata !4, metadata !"int", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 524307, metadata !3, metadata !"", metadata !4, i32 11, i64 8, i64 8, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!11 = metadata !{metadata !12} +!12 = metadata !{i32 524301, metadata !10, metadata !"b", metadata !4, i32 11, i64 8, i64 8, i64 0, i32 0, metadata !13} ; [ DW_TAG_member ] +!13 = metadata !{i32 524310, metadata !3, metadata !"A", metadata !4, i32 11, i64 0, i64 0, i64 0, i32 0, metadata !14} ; [ DW_TAG_typedef ] +!14 = metadata !{i32 524289, metadata !4, metadata !"", metadata !4, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !15, metadata !16, i32 0, null} ; [ DW_TAG_array_type ] +!15 = metadata !{i32 524324, metadata !4, metadata !"char", metadata !4, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!16 = metadata !{metadata !17} +!17 = metadata !{i32 524321, i64 0, i64 0} ; [ DW_TAG_subrange_type ] +!18 = metadata !{metadata !"llvm.mdnode.fwdref.19"} +!19 = metadata !{metadata !"llvm.mdnode.fwdref.23"} diff --git a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll new file mode 100644 index 0000000..dd6c5a9 --- /dev/null +++ b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll @@ -0,0 +1,89 @@ +; RUN: llvm-as < %s | llc -asm-verbose -O0 | grep AT_specification | count 2 +; Radar 7833483 +; Do not emit AT_specification for nested function foo. + +%class.A = type { i8 } +%class.B = type { i8 } + +define i32 @main() ssp { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=3] + %b = alloca %class.A, align 1 ; <%class.A*> [#uses=1] + store i32 0, i32* %retval + call void @llvm.dbg.declare(metadata !{%class.A* %b}, metadata !0), !dbg !14 + %call = call i32 @_ZN1B2fnEv(%class.A* %b), !dbg !15 ; <i32> [#uses=1] + store i32 %call, i32* %retval, !dbg !15 + %0 = load i32* %retval, !dbg !16 ; <i32> [#uses=1] + ret i32 %0, !dbg !16 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define linkonce_odr i32 @_ZN1B2fnEv(%class.A* %this) ssp align 2 { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %this.addr = alloca %class.A*, align 8 ; <%class.A**> [#uses=2] + %a = alloca %class.A, align 1 ; <%class.A*> [#uses=1] + %i = alloca i32, align 4 ; <i32*> [#uses=2] + store %class.A* %this, %class.A** %this.addr + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !17), !dbg !18 + %this1 = load %class.A** %this.addr ; <%class.A*> [#uses=0] + call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !19), !dbg !27 + call void @llvm.dbg.declare(metadata !{i32* %i}, metadata !28), !dbg !29 + %call = call i32 @_ZZN1B2fnEvEN1A3fooEv(%class.A* %a), !dbg !30 ; <i32> [#uses=1] + store i32 %call, i32* %i, !dbg !30 + %tmp = load i32* %i, !dbg !31 ; <i32> [#uses=1] + store i32 %tmp, i32* %retval, !dbg !31 + %0 = load i32* %retval, !dbg !32 ; <i32> [#uses=1] + ret i32 %0, !dbg !32 +} + +define internal i32 @_ZZN1B2fnEvEN1A3fooEv(%class.A* %this) ssp align 2 { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %this.addr = alloca %class.A*, align 8 ; <%class.A**> [#uses=2] + store %class.A* %this, %class.A** %this.addr + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !33), !dbg !34 + %this1 = load %class.A** %this.addr ; <%class.A*> [#uses=0] + store i32 42, i32* %retval, !dbg !35 + %0 = load i32* %retval, !dbg !35 ; <i32> [#uses=1] + ret i32 %0, !dbg !35 +} + +!0 = metadata !{i32 524544, metadata !1, metadata !"b", metadata !3, i32 16, metadata !8} ; [ DW_TAG_auto_variable ] +!1 = metadata !{i32 524299, metadata !2, i32 15, i32 12} ; [ DW_TAG_lexical_block ] +!2 = metadata !{i32 524334, i32 0, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 15, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!3 = metadata !{i32 524329, metadata !"one.cc", metadata !"/tmp", metadata !4} ; [ DW_TAG_file_type ] +!4 = metadata !{i32 524305, i32 0, i32 4, metadata !"one.cc", metadata !"/tmp", metadata !"clang 1.5", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ] +!6 = metadata !{metadata !7} +!7 = metadata !{i32 524324, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 524290, metadata !3, metadata !"B", metadata !3, i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_class_type ] +!9 = metadata !{metadata !10} +!10 = metadata !{i32 524334, i32 0, metadata !8, metadata !"fn", metadata !"fn", metadata !"_ZN1B2fnEv", metadata !3, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !7, metadata !13} +!13 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 16, i32 5, metadata !1, null} +!15 = metadata !{i32 17, i32 3, metadata !1, null} +!16 = metadata !{i32 18, i32 1, metadata !2, null} +!17 = metadata !{i32 524545, metadata !10, metadata !"this", metadata !3, i32 4, metadata !13} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 4, i32 7, metadata !10, null} +!19 = metadata !{i32 524544, metadata !20, metadata !"a", metadata !3, i32 9, metadata !21} ; [ DW_TAG_auto_variable ] +!20 = metadata !{i32 524299, metadata !10, i32 4, i32 12} ; [ DW_TAG_lexical_block ] +!21 = metadata !{i32 524290, metadata !10, metadata !"A", metadata !3, i32 5, i64 8, i64 8, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_class_type ] +!22 = metadata !{metadata !23} +!23 = metadata !{i32 524334, i32 0, metadata !21, metadata !"foo", metadata !"foo", metadata !"_ZZN1B2fnEvEN1A3fooEv", metadata !3, i32 7, metadata !24, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!24 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, null} ; [ DW_TAG_subroutine_type ] +!25 = metadata !{metadata !7, metadata !26} +!26 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !21} ; [ DW_TAG_pointer_type ] +!27 = metadata !{i32 9, i32 7, metadata !20, null} +!28 = metadata !{i32 524544, metadata !20, metadata !"i", metadata !3, i32 10, metadata !7} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 10, i32 9, metadata !20, null} +!30 = metadata !{i32 10, i32 5, metadata !20, null} +!31 = metadata !{i32 11, i32 5, metadata !20, null} +!32 = metadata !{i32 12, i32 3, metadata !10, null} +!33 = metadata !{i32 524545, metadata !23, metadata !"this", metadata !3, i32 7, metadata !26} ; [ DW_TAG_arg_variable ] +!34 = metadata !{i32 7, i32 11, metadata !23, null} +!35 = metadata !{i32 7, i32 19, metadata !36, null} +!36 = metadata !{i32 524299, metadata !23, i32 7, i32 17} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-04-13-PubType.ll b/test/DebugInfo/2010-04-13-PubType.ll new file mode 100644 index 0000000..371169f --- /dev/null +++ b/test/DebugInfo/2010-04-13-PubType.ll @@ -0,0 +1,47 @@ +; RUN: llc -O0 -asm-verbose < %s > %t +; RUN: grep "External Name" %t | grep -v X +; RUN: grep "External Name" %t | grep Y | count 1 +; Test to check type with no defintion is listed in pubtypes section. +%struct.X = type opaque +%struct.Y = type { i32 } + +define i32 @foo(%struct.X* %x, %struct.Y* %y) nounwind ssp { +entry: + %x_addr = alloca %struct.X* ; <%struct.X**> [#uses=1] + %y_addr = alloca %struct.Y* ; <%struct.Y**> [#uses=1] + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.X** %x_addr}, metadata !0), !dbg !13 + store %struct.X* %x, %struct.X** %x_addr + call void @llvm.dbg.declare(metadata !{%struct.Y** %y_addr}, metadata !14), !dbg !13 + store %struct.Y* %y, %struct.Y** %y_addr + store i32 0, i32* %0, align 4, !dbg !13 + %1 = load i32* %0, align 4, !dbg !13 ; <i32> [#uses=1] + store i32 %1, i32* %retval, align 4, !dbg !13 + br label %return, !dbg !13 + +return: ; preds = %entry + %retval1 = load i32* %retval, !dbg !13 ; <i32> [#uses=1] + ret i32 %retval1, !dbg !15 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"x", metadata !2, i32 7, metadata !7} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"a.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"a.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !7, metadata !9} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 524307, metadata !2, metadata !"X", metadata !2, i32 3, i64 0, i64 0, i64 0, i32 4, null, null, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 524307, metadata !2, metadata !"Y", metadata !2, i32 4, i64 32, i64 32, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!11 = metadata !{metadata !12} +!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 5, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 7, i32 0, metadata !1, null} +!14 = metadata !{i32 524545, metadata !1, metadata !"y", metadata !2, i32 7, metadata !9} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 7, i32 0, metadata !16, null} +!16 = metadata !{i32 524299, metadata !1, i32 7, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-04-19-FramePtr.ll b/test/DebugInfo/2010-04-19-FramePtr.ll new file mode 100644 index 0000000..3003121 --- /dev/null +++ b/test/DebugInfo/2010-04-19-FramePtr.ll @@ -0,0 +1,30 @@ +; RUN: llc -asm-verbose -O0 -o %t < %s +; RUN: grep DW_AT_APPLE_omit_frame_ptr %t +; RUN: llc -disable-fp-elim -asm-verbose -O0 -o %t < %s +; RUN: grep -v DW_AT_APPLE_omit_frame_ptr %t + + +define i32 @foo() nounwind ssp { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 42, i32* %0, align 4, !dbg !0 + %1 = load i32* %0, align 4, !dbg !0 ; <i32> [#uses=1] + store i32 %1, i32* %retval, align 4, !dbg !0 + br label %return, !dbg !0 + +return: ; preds = %entry + %retval1 = load i32* %retval, !dbg !0 ; <i32> [#uses=1] + ret i32 %retval1, !dbg !7 +} + +!0 = metadata !{i32 2, i32 0, metadata !1, null} +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"a.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"a.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 2, i32 0, metadata !8, null} +!8 = metadata !{i32 524299, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-04-25-CU-entry_pc.ll b/test/DebugInfo/2010-04-25-CU-entry_pc.ll new file mode 100644 index 0000000..de099b6 --- /dev/null +++ b/test/DebugInfo/2010-04-25-CU-entry_pc.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s | grep entry_pc | count 2 +@i = global i32 1 ; <i32*> [#uses=0] + +!llvm.dbg.gv = !{!0} + +!0 = metadata !{i32 524340, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"", metadata !1, i32 1, metadata !3, i1 false, i1 true, i32* @i} ; [ DW_TAG_variable ] +!1 = metadata !{i32 524329, metadata !"b.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"b.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/Feature/unions.ll b/test/Feature/unions.ll index 9d6c36b..3cf8c3c 100644 --- a/test/Feature/unions.ll +++ b/test/Feature/unions.ll @@ -6,7 +6,9 @@ @union1 = constant union { i32, i8 } { i32 4 } @union2 = constant union { i32, i8 } insertvalue(union { i32, i8 } undef, i32 4, 0) +@union3 = common global %union.anon zeroinitializer, align 8 define void @"Unions" () { ret void } + diff --git a/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp b/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp index 4c8e0e5..2a9f1f1 100644 --- a/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp +++ b/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp @@ -1,4 +1,4 @@ -// RUN: %llvmgcc -g -S %s -o - | grep DW_TAG_pointer_type | grep "i32 458767, metadata .., metadata ..., metadata .., i32 ., i64 .., i64 .., i64 0, i32 64, metadata ..." +// RUN: %llvmgcc -g -S %s -o - | grep DW_TAG_pointer_type | grep "i32 524303, metadata .., metadata ..., metadata .., i32 ., i64 .., i64 .., i64 0, i32 64, metadata ..." // Here, second to last argument "i32 64" indicates that artificial type is set. // Test to artificial attribute attahed to "this" pointer type. // Radar 7655792 and 7655002 diff --git a/test/FrontendC++/2010-03-22-empty-baseclass.cpp b/test/FrontendC++/2010-03-22-empty-baseclass.cpp new file mode 100644 index 0000000..b6bdea4 --- /dev/null +++ b/test/FrontendC++/2010-03-22-empty-baseclass.cpp @@ -0,0 +1,134 @@ +// RUN: %llvmgxx -S -emit-llvm %s -o - -O2 | FileCheck %s +namespace boost { + namespace detail { + template <typename T> struct cv_traits_imp {}; + template <typename T> struct cv_traits_imp<T*> {typedef T unqualified_type;}; + } +} +namespace mpl_ {} +namespace boost { + namespace mpl {using namespace mpl_;} + template< typename T > struct remove_cv {typedef typename boost::detail::cv_traits_imp<T*>::unqualified_type type;}; + namespace type_traits { + typedef char yes_type; + struct no_type {char padding[8];}; + } +} +namespace mpl_ { + template< bool C_ > struct bool_; + typedef bool_<true> true_; + typedef bool_<false> false_; + template< bool C_ > struct bool_ {static const bool value = C_;}; + template< typename T, T N > struct integral_c; +} +namespace boost{ + template <class T, T val> struct integral_constant : + public mpl::integral_c<T, val> {}; + template<> struct integral_constant<bool,true> : public mpl::true_ {}; + template<> struct integral_constant<bool,false> : public mpl::false_ {}; + namespace type_traits { + template <bool b1, bool b2, bool b3 = false, bool b4 = false, + bool b5 = false, bool b6 = false, bool b7 = false> struct ice_or; + template <bool b1, bool b2, bool b3, bool b4, bool b5, bool b6, bool b7> + struct ice_or {static const bool value = true; }; + template <> struct ice_or<false, false, false, false, false, false, false> + {static const bool value = false;}; + template <bool b1, bool b2, bool b3 = true, bool b4 = true, bool b5 = true, + bool b6 = true, bool b7 = true> struct ice_and; + template <bool b1, bool b2, bool b3, bool b4, bool b5, bool b6, bool b7> + struct ice_and {static const bool value = false;}; + template <> struct ice_and<true, true, true, true, true, true, true> + {static const bool value = true;}; + template <bool b> struct ice_not {static const bool value = true;}; + }; + namespace detail { + template <typename T> struct is_union_impl {static const bool value = false;}; + } + template< typename T > struct is_union : + ::boost::integral_constant<bool, ::boost::detail::is_union_impl<T>::value> {}; + namespace detail { + template <class U> ::boost::type_traits::yes_type is_class_tester(void(U::*)(void)); + template <class U> ::boost::type_traits::no_type is_class_tester(...); + template <typename T> struct is_class_impl { + static const bool value = (::boost::type_traits::ice_and< sizeof(is_class_tester<T>(0)) + == sizeof(::boost::type_traits::yes_type), + ::boost::type_traits::ice_not< ::boost::is_union<T>::value >::value >::value);}; +} + template<typename T> struct is_class: + ::boost::integral_constant<bool,::boost::detail::is_class_impl<T>::value> { }; +namespace detail { + template <typename T> struct empty_helper_t1: public T {int i[256];}; + struct empty_helper_t2 {int i[256];}; + template <typename T, bool is_a_class = false> struct empty_helper + {static const bool value = false;}; + template <typename T> struct empty_helper<T, true> + {static const bool value = (sizeof(empty_helper_t1<T>) == sizeof(empty_helper_t2));}; + template <typename T> struct is_empty_impl { + typedef typename remove_cv<T>::type cvt; + static const bool value = (::boost::type_traits::ice_or< ::boost::detail::empty_helper + <cvt,::boost::is_class<T>::value>::value, false>::value); + }; +} +template<typename T> struct is_empty: +::boost::integral_constant<bool,::boost::detail::is_empty_impl<T>::value> {}; +template<typename T, typename U > struct is_same: +::boost::integral_constant<bool,false> {}; +template<typename T> struct call_traits {typedef T& reference;}; +namespace details { + template <class T1, class T2, bool IsSame, bool FirstEmpty, bool SecondEmpty> + struct compressed_pair_switch; + template <class T1, class T2> + struct compressed_pair_switch<T1, T2, false, true, false> + {static const int value = 1;}; + template <class T1, class T2, int Version> class compressed_pair_imp; + template <class T1, class T2> class compressed_pair_imp<T1, T2, 1>: + protected ::boost::remove_cv<T1>::type { + public: + typedef T1 first_type; + typedef T2 second_type; + typedef typename call_traits<first_type>::reference first_reference; + typedef typename call_traits<second_type>::reference second_reference; + first_reference first() {return *this;} + second_reference second() {return second_;} + second_type second_; + }; +} +template <class T1, class T2> class compressed_pair: + private ::boost::details::compressed_pair_imp<T1, T2, ::boost::details::compressed_pair_switch< + T1, T2, ::boost::is_same<typename remove_cv<T1>::type, + typename remove_cv<T2>::type>::value, + ::boost::is_empty<T1>::value, ::boost::is_empty<T2>::value>::value> + { + private: + typedef details::compressed_pair_imp<T1, T2, ::boost::details::compressed_pair_switch< + T1, T2, ::boost::is_same<typename remove_cv<T1>::type, + typename remove_cv<T2>::type>::value, + ::boost::is_empty<T1>::value, ::boost::is_empty<T2>::value>::value> base; + public: + typedef T1 first_type; + typedef T2 second_type; + typedef typename call_traits<first_type>::reference first_reference; + typedef typename call_traits<second_type>::reference second_reference; + first_reference first() {return base::first();} + second_reference second() {return base::second();} + }; +} +struct empty_base_t {}; +struct empty_t : empty_base_t {}; +typedef boost::compressed_pair<empty_t, int> data_t; +extern "C" {int printf(const char * , ...);} +extern "C" {void abort(void);} +int main (int argc, char * const argv[]) { + data_t x; + x.second() = -3; + // This store should be elided: + x.first() = empty_t(); + // If x.second() has been clobbered by the elided store, fail. + if (x.second() != -3) { + printf("x.second() was clobbered\n"); + // CHECK-NOT: x.second() was clobbered + abort(); + } + return 0; +} +// CHECK: ret i32 diff --git a/test/FrontendC/2007-05-16-EmptyStruct.c b/test/FrontendC/2007-05-16-EmptyStruct.c index 748aa98..23c0b1d 100644 --- a/test/FrontendC/2007-05-16-EmptyStruct.c +++ b/test/FrontendC/2007-05-16-EmptyStruct.c @@ -1,5 +1,5 @@ // PR 1417 -// RUN: %llvmgcc -xc %s -c -o - | llvm-dis | grep "struct.anon = type \{ \}" +// RUN: %llvmgcc -xc %s -c -o - | llvm-dis | grep "struct.anon = type \{\}" struct { } *X; diff --git a/test/FrontendC/2008-11-02-WeakAlias.c b/test/FrontendC/2008-11-02-WeakAlias.c index 4bdc5c7..befafe4 100644 --- a/test/FrontendC/2008-11-02-WeakAlias.c +++ b/test/FrontendC/2008-11-02-WeakAlias.c @@ -2,4 +2,4 @@ // PR2691 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ"))); -void native_init_IRQ(void) {}
\ No newline at end of file +void native_init_IRQ(void) {} diff --git a/test/FrontendC/2009-12-07-BitFieldAlignment.c b/test/FrontendC/2009-12-07-BitFieldAlignment.c index a8312a5..02ff8bc 100644 --- a/test/FrontendC/2009-12-07-BitFieldAlignment.c +++ b/test/FrontendC/2009-12-07-BitFieldAlignment.c @@ -9,7 +9,7 @@ struct S { }; void f0(struct S *a) { -// CHECK: %3 = load i32* %2, align 4 -// CHECK: store i32 %4, i32* %2, align 4 +// CHECK: load {{.*}}, align 4 +// CHECK: store {{.*}}, align 4 a->e = 0; } diff --git a/test/FrontendC/2010-03-10-arm-asmreg.c b/test/FrontendC/2010-03-10-arm-asmreg.c new file mode 100644 index 0000000..70d3681 --- /dev/null +++ b/test/FrontendC/2010-03-10-arm-asmreg.c @@ -0,0 +1,15 @@ +// RUN: %llvmgcc %s -S -O0 -o - | FileCheck %s +// pr6552 + +// XFAIL: * +// XTARGET: arm + +extern void bar(unsigned int ip); + +// CHECK: mov r0, r12 +void foo(void) +{ + register unsigned int ip __asm ("ip"); + bar(ip); +} + diff --git a/test/FrontendC/crash-invalid-array.c b/test/FrontendC/crash-invalid-array.c new file mode 100644 index 0000000..d602f785 --- /dev/null +++ b/test/FrontendC/crash-invalid-array.c @@ -0,0 +1,17 @@ +// RUN: not %llvmgcc -O1 %s -S |& grep {error: invalid use of array with unspecified bounds} +// PR6913 + +#include <stdio.h> + +int main() +{ + int x[10][10]; + int (*p)[] = x; // <-- this line is what triggered it + + int i; + + for(i = 0; i < 10; ++i) + { + p[i][i] = i; + } +} diff --git a/test/FrontendObjC/2010-03-17-StructRef.m b/test/FrontendObjC/2010-03-17-StructRef.m new file mode 100644 index 0000000..3594684 --- /dev/null +++ b/test/FrontendObjC/2010-03-17-StructRef.m @@ -0,0 +1,43 @@ +// RUN: %llvmgcc %s -m64 -S -o - | FileCheck %s +// Bitfield references must not touch memory outside of the enclosing +// struct. Radar 7639995 +typedef signed char BOOL; +@protocol NSObject +- (id)init; +@end +@interface NSObject <NSObject> {} +@end +@interface IMAVChatParticipant : NSObject { + int _ardRole; + int _state; + int _avRelayStatus; + int _chatEndedReason; + int _chatError; + unsigned _sendingAudio:1; + unsigned _sendingVideo:1; + unsigned _sendingAuxVideo:1; + unsigned _audioMuted:1; + unsigned _videoPaused:1; + unsigned _networkStalled:1; + unsigned _isInitiator:1; + unsigned _isAOLInterop:1; + unsigned _isRecording:1; + unsigned _isUsingICE:1; +} +@end +@implementation IMAVChatParticipant +- (id) init { + self = [super init]; + if ( self ) { + BOOL blah = (BOOL)1; + // We're expecting these three bitfield assignments will generate i8 stores. + _sendingAudio = (BOOL)1; + _isUsingICE = (BOOL)1; + _isUsingICE = blah; + // CHECK: store i8 + // CHECK: store i8 + // CHECK: store i8 + } + return self; +} +@end diff --git a/test/LLVMC/AppendCmdHook.td b/test/LLVMC/AppendCmdHook.td index 539a93f..254d5ea 100644 --- a/test/LLVMC/AppendCmdHook.td +++ b/test/LLVMC/AppendCmdHook.td @@ -2,6 +2,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/C++/dash-x.cpp b/test/LLVMC/C++/dash-x.cpp index b32400e..7d4cf19 100644 --- a/test/LLVMC/C++/dash-x.cpp +++ b/test/LLVMC/C++/dash-x.cpp @@ -1,6 +1,7 @@ // Test that we can compile .c files as C++ and vice versa // RUN: llvmc %s -x c++ %p/../test_data/false.c -x c %p/../test_data/false.cpp -x lisp -x whatnot -x none %p/../test_data/false2.cpp -o %t // RUN: %abs_tmp | grep hello +// XFAIL: vg extern int test_main(); diff --git a/test/LLVMC/C++/hello.cpp b/test/LLVMC/C++/hello.cpp index b9c6399..8f38306 100644 --- a/test/LLVMC/C++/hello.cpp +++ b/test/LLVMC/C++/hello.cpp @@ -1,6 +1,7 @@ // Test that we can compile C++ code. // RUN: llvmc %s -o %t // RUN: %abs_tmp | grep hello +// XFAIL: vg #include <iostream> int main() { diff --git a/test/LLVMC/C++/together.cpp b/test/LLVMC/C++/together.cpp index e02f69a..925215a 100644 --- a/test/LLVMC/C++/together.cpp +++ b/test/LLVMC/C++/together.cpp @@ -1,6 +1,7 @@ // Check that we can compile files of different types together. // RUN: llvmc %s %p/../test_data/together.c -o %t // RUN: %abs_tmp | grep hello +// XFAIL: vg extern "C" void test(); diff --git a/test/LLVMC/C/emit-llvm.c b/test/LLVMC/C/emit-llvm.c index 38bbba6..9844bc7 100644 --- a/test/LLVMC/C/emit-llvm.c +++ b/test/LLVMC/C/emit-llvm.c @@ -1,4 +1,5 @@ // RUN: llvmc -c -emit-llvm -o - %s | llvm-dis | grep "@f0()" | count 1 +// XFAIL: vg_leak int f0(void) { } diff --git a/test/LLVMC/C/hello.c b/test/LLVMC/C/hello.c index b2d903f..29ad39f 100644 --- a/test/LLVMC/C/hello.c +++ b/test/LLVMC/C/hello.c @@ -2,6 +2,7 @@ * Check that we can compile helloworld * RUN: llvmc %s -o %t * RUN: %abs_tmp | grep hello + * XFAIL: vg_leak */ #include <stdio.h> diff --git a/test/LLVMC/C/include.c b/test/LLVMC/C/include.c index 07ae761..9c9530b 100644 --- a/test/LLVMC/C/include.c +++ b/test/LLVMC/C/include.c @@ -2,6 +2,7 @@ * Check that the 'include' options work. * RUN: echo "int x;\n" > %t1.inc * RUN: llvmc -include %t1.inc -fsyntax-only %s + * XFAIL: vg_leak */ int f0(void) { diff --git a/test/LLVMC/C/opt-test.c b/test/LLVMC/C/opt-test.c index d69dc9b..7924def 100644 --- a/test/LLVMC/C/opt-test.c +++ b/test/LLVMC/C/opt-test.c @@ -2,6 +2,7 @@ * Check that the -opt switch works. * RUN: llvmc %s -opt -o %t * RUN: %abs_tmp | grep hello + * XFAIL: vg_leak */ #include <stdio.h> diff --git a/test/LLVMC/C/sink.c b/test/LLVMC/C/sink.c index bdff340..c4f9beb 100644 --- a/test/LLVMC/C/sink.c +++ b/test/LLVMC/C/sink.c @@ -2,6 +2,7 @@ * Check that the 'sink' options work. * RUN: llvmc -v -Wall %s -o %t |& grep "Wall" * RUN: %abs_tmp | grep hello + * XFAIL: vg_leak */ #include <stdio.h> diff --git a/test/LLVMC/C/wall.c b/test/LLVMC/C/wall.c index f676099..36813ba 100644 --- a/test/LLVMC/C/wall.c +++ b/test/LLVMC/C/wall.c @@ -2,6 +2,7 @@ * Check that -Wall works as intended * RUN: llvmc -Wall %s -o %t * RUN: %abs_tmp | grep hello + * XFAIL: vg_leak */ #include <stdio.h> diff --git a/test/LLVMC/EmptyCompilationGraph.td b/test/LLVMC/EmptyCompilationGraph.td index 934905b..e5d5e9a 100644 --- a/test/LLVMC/EmptyCompilationGraph.td +++ b/test/LLVMC/EmptyCompilationGraph.td @@ -1,6 +1,7 @@ // Check that the compilation graph can be empty. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/EnvParentheses.td b/test/LLVMC/EnvParentheses.td index c563171..86091db 100644 --- a/test/LLVMC/EnvParentheses.td +++ b/test/LLVMC/EnvParentheses.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: not grep {FOO")));} %t // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/ExternOptions.td b/test/LLVMC/ExternOptions.td index 77cb4bf..d84ea84 100644 --- a/test/LLVMC/ExternOptions.td +++ b/test/LLVMC/ExternOptions.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/ForwardAs.td b/test/LLVMC/ForwardAs.td index 7c3bd17..536b96a 100644 --- a/test/LLVMC/ForwardAs.td +++ b/test/LLVMC/ForwardAs.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/ForwardTransformedValue.td b/test/LLVMC/ForwardTransformedValue.td index 2caef6c..5e0bf29 100644 --- a/test/LLVMC/ForwardTransformedValue.td +++ b/test/LLVMC/ForwardTransformedValue.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/ForwardValue.td b/test/LLVMC/ForwardValue.td index 463235c..4c7a0ee 100644 --- a/test/LLVMC/ForwardValue.td +++ b/test/LLVMC/ForwardValue.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/HookWithArguments.td b/test/LLVMC/HookWithArguments.td index 312fa9c..5ff96cd 100644 --- a/test/LLVMC/HookWithArguments.td +++ b/test/LLVMC/HookWithArguments.td @@ -2,6 +2,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/HookWithInFile.td b/test/LLVMC/HookWithInFile.td index f58e3f4..9855dbc 100644 --- a/test/LLVMC/HookWithInFile.td +++ b/test/LLVMC/HookWithInFile.td @@ -2,6 +2,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/Init.td b/test/LLVMC/Init.td index ff9a0d8..05209bf 100644 --- a/test/LLVMC/Init.td +++ b/test/LLVMC/Init.td @@ -2,6 +2,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/MultiValuedOption.td b/test/LLVMC/MultiValuedOption.td index b52af57..73ccb63 100644 --- a/test/LLVMC/MultiValuedOption.td +++ b/test/LLVMC/MultiValuedOption.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/MultipleCompilationGraphs.td b/test/LLVMC/MultipleCompilationGraphs.td index 9702248..86cd613 100644 --- a/test/LLVMC/MultipleCompilationGraphs.td +++ b/test/LLVMC/MultipleCompilationGraphs.td @@ -1,6 +1,7 @@ // Check that multiple compilation graphs are allowed. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/NoActions.td b/test/LLVMC/NoActions.td index 015bfdd..a80bcfe 100644 --- a/test/LLVMC/NoActions.td +++ b/test/LLVMC/NoActions.td @@ -2,6 +2,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/NoCompilationGraph.td b/test/LLVMC/NoCompilationGraph.td index 96c1f17..69df701 100644 --- a/test/LLVMC/NoCompilationGraph.td +++ b/test/LLVMC/NoCompilationGraph.td @@ -1,5 +1,6 @@ // Check that the compilation graph is not required. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/OneOrMore.td b/test/LLVMC/OneOrMore.td index 42ec693..37fbc87 100644 --- a/test/LLVMC/OneOrMore.td +++ b/test/LLVMC/OneOrMore.td @@ -3,6 +3,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/OptionPreprocessor.td b/test/LLVMC/OptionPreprocessor.td index 8a31481..c2641be 100644 --- a/test/LLVMC/OptionPreprocessor.td +++ b/test/LLVMC/OptionPreprocessor.td @@ -2,6 +2,7 @@ // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s // RUN: %compile_cxx -fexceptions -x c++ %t +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/LLVMC/TestWarnings.td b/test/LLVMC/TestWarnings.td index 9523e24..0388cb0 100644 --- a/test/LLVMC/TestWarnings.td +++ b/test/LLVMC/TestWarnings.td @@ -1,6 +1,7 @@ // Check that warnings about unused options are really emitted. // This should fail because the output is printed on stderr. -// RUN: ignore tblgen -I %p/../../include --gen-llvmc %s |& grep "option '-Wall' has no effect!" +// RUN: tblgen -I %p/../../include --gen-llvmc %s |& grep "option '-Wall' has no effect!" +// XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" diff --git a/test/MC/AsmParser/X86/x86_32-bit.s b/test/MC/AsmParser/X86/x86_32-bit.s index 90e97be..ca0b26b 100644 --- a/test/MC/AsmParser/X86/x86_32-bit.s +++ b/test/MC/AsmParser/X86/x86_32-bit.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +// XFAIL: * // CHECK: movb $127, 3735928559(%ebx,%ecx,8) movb $0x7f,0xdeadbeef(%ebx,%ecx,8) diff --git a/test/MC/AsmParser/X86/x86_32-bit_cat.s b/test/MC/AsmParser/X86/x86_32-bit_cat.s index f0c7804..ec2bfa4 100644 --- a/test/MC/AsmParser/X86/x86_32-bit_cat.s +++ b/test/MC/AsmParser/X86/x86_32-bit_cat.s @@ -4,6 +4,8 @@ // the file x86_32-encoding.s (and other tests that encode are in x86_32-bit.s). // RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +// XFAIL: * + // CHECK: movb $127, 3735928559(%ebx,%ecx,8) movb $0x7f,0xdeadbeef(%ebx,%ecx,8) @@ -7754,41 +7756,38 @@ // CHECK: ptest %xmm5, %xmm5 ptest %xmm5,%xmm5 -// CHECK: crc32 3735928559(%ebx,%ecx,8), %ecx - crc32 0xdeadbeef(%ebx,%ecx,8),%ecx - -// CHECK: crc32 69, %ecx - crc32 0x45,%ecx +// CHECK: crc32b %bl, %eax + crc32b %bl, %eax -// CHECK: crc32 32493, %ecx - crc32 0x7eed,%ecx +// CHECK: crc32b 4(%ebx), %eax + crc32b 4(%ebx), %eax -// CHECK: crc32 3133065982, %ecx - crc32 0xbabecafe,%ecx +// CHECK: crc32w %bx, %eax + crc32w %bx, %eax -// CHECK: crc32 305419896, %ecx - crc32 0x12345678,%ecx +// CHECK: crc32w 4(%ebx), %eax + crc32w 4(%ebx), %eax -// CHECK: crc32 %ecx, %ecx - crc32 %ecx,%ecx +// CHECK: crc32l %ebx, %eax + crc32l %ebx, %eax -// CHECK: crc32 %ecx, %ecx - crc32 %ecx,%ecx +// CHECK: crc32l 4(%ebx), %eax + crc32l 4(%ebx), %eax -// CHECK: crc32 3735928559(%ebx,%ecx,8), %ecx - crc32 0xdeadbeef(%ebx,%ecx,8),%ecx +// CHECK: crc32l 3735928559(%ebx,%ecx,8), %ecx + crc32l 0xdeadbeef(%ebx,%ecx,8),%ecx -// CHECK: crc32 69, %ecx - crc32 0x45,%ecx +// CHECK: crc32l 69, %ecx + crc32l 0x45,%ecx -// CHECK: crc32 32493, %ecx - crc32 0x7eed,%ecx +// CHECK: crc32l 32493, %ecx + crc32l 0x7eed,%ecx -// CHECK: crc32 3133065982, %ecx - crc32 0xbabecafe,%ecx +// CHECK: crc32l 3133065982, %ecx + crc32l 0xbabecafe,%ecx -// CHECK: crc32 305419896, %ecx - crc32 0x12345678,%ecx +// CHECK: crc32l %ecx, %ecx + crc32l %ecx,%ecx // CHECK: pcmpgtq 3735928559(%ebx,%ecx,8), %xmm5 pcmpgtq 0xdeadbeef(%ebx,%ecx,8),%xmm5 @@ -7807,3 +7806,39 @@ // CHECK: pcmpgtq %xmm5, %xmm5 pcmpgtq %xmm5,%xmm5 + +// CHECK: aesimc %xmm0, %xmm1 + aesimc %xmm0,%xmm1 + +// CHECK: aesimc (%eax), %xmm1 + aesimc (%eax),%xmm1 + +// CHECK: aesenc %xmm1, %xmm2 + aesenc %xmm1,%xmm2 + +// CHECK: aesenc 4(%ebx), %xmm2 + aesenc 4(%ebx),%xmm2 + +// CHECK: aesenclast %xmm3, %xmm4 + aesenclast %xmm3,%xmm4 + +// CHECK: aesenclast 4(%edx,%edi), %xmm4 + aesenclast 4(%edx,%edi),%xmm4 + +// CHECK: aesdec %xmm5, %xmm6 + aesdec %xmm5,%xmm6 + +// CHECK: aesdec 4(%ecx,%eax,8), %xmm6 + aesdec 4(%ecx,%eax,8),%xmm6 + +// CHECK: aesdeclast %xmm7, %xmm0 + aesdeclast %xmm7,%xmm0 + +// CHECK: aesdeclast 3405691582, %xmm0 + aesdeclast 0xcafebabe,%xmm0 + +// CHECK: aeskeygenassist $125, %xmm1, %xmm2 + aeskeygenassist $125, %xmm1, %xmm2 + +// CHECK: aeskeygenassist $125, (%edx,%eax,4), %xmm2 + aeskeygenassist $125, (%edx,%eax,4), %xmm2 diff --git a/test/MC/AsmParser/X86/x86_32-encoding.s b/test/MC/AsmParser/X86/x86_32-encoding.s index e325bdd..bf573e8 100644 --- a/test/MC/AsmParser/X86/x86_32-encoding.s +++ b/test/MC/AsmParser/X86/x86_32-encoding.s @@ -1,4 +1,6 @@ // RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s +// XFAIL: * + // CHECK: movb $127, 3735928559(%ebx,%ecx,8) // CHECK: encoding: [0xc6,0x84,0xcb,0xef,0xbe,0xad,0xde,0x7f] @@ -9859,3 +9861,110 @@ // CHECK: pcmpgtq %xmm5, %xmm5 // CHECK: encoding: [0x66,0x0f,0x38,0x37,0xed] pcmpgtq %xmm5,%xmm5 + +// CHECK: crc32b %bl, %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0xc3] + crc32b %bl, %eax + +// CHECK: crc32b 4(%ebx), %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0x43,0x04] + crc32b 4(%ebx), %eax + +// CHECK: crc32w %bx, %eax +// CHECK: encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc3] + crc32w %bx, %eax + +// CHECK: crc32w 4(%ebx), %eax +// CHECK: encoding: [0x66,0xf2,0x0f,0x38,0xf1,0x43,0x04] + crc32w 4(%ebx), %eax + +// CHECK: crc32l %ebx, %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0xc3] + crc32l %ebx, %eax + +// CHECK: crc32l 4(%ebx), %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x43,0x04] + crc32l 4(%ebx), %eax + +// CHECK: crc32l 3735928559(%ebx,%ecx,8), %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x8c,0xcb,0xef,0xbe,0xad,0xde] + crc32l 0xdeadbeef(%ebx,%ecx,8),%ecx + +// CHECK: crc32l 69, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0d,0x45,0x00,0x00,0x00] + crc32l 0x45,%ecx + +// CHECK: crc32l 32493, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0d,0xed,0x7e,0x00,0x00] + crc32l 0x7eed,%ecx + +// CHECK: crc32l 3133065982, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0d,0xfe,0xca,0xbe,0xba] + crc32l 0xbabecafe,%ecx + +// CHECK: crc32l %ecx, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0xc9] + crc32l %ecx,%ecx + +// CHECK: pcmpistrm $125, %xmm1, %xmm2 +// CHECK: encoding: [0x66,0x0f,0x3a,0x62,0xd1,0x7d] + pcmpistrm $125, %xmm1, %xmm2 + +// CHECK: pcmpistrm $125, (%edx,%eax,4), %xmm2 +// CHECK: encoding: [0x66,0x0f,0x3a,0x62,0x14,0x82,0x7d] + pcmpistrm $125, (%edx,%eax,4), %xmm2 + +// CHECK: aesimc %xmm0, %xmm1 +// CHECK: encoding: [0x66,0x0f,0x38,0xdb,0xc8] + aesimc %xmm0,%xmm1 + +// CHECK: aesimc (%eax), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x38,0xdb,0x08] + aesimc (%eax),%xmm1 + +// CHECK: aesenc %xmm1, %xmm2 +// CHECK: encoding: [0x66,0x0f,0x38,0xdc,0xd1] + aesenc %xmm1,%xmm2 + +// CHECK: aesenc 4(%ebx), %xmm2 +// CHECK: encoding: [0x66,0x0f,0x38,0xdc,0x53,0x04] + aesenc 4(%ebx),%xmm2 + +// CHECK: aesenclast %xmm3, %xmm4 +// CHECK: encoding: [0x66,0x0f,0x38,0xdd,0xe3] + aesenclast %xmm3,%xmm4 + +// CHECK: aesenclast 4(%edx,%edi), %xmm4 +// CHECK: encoding: [0x66,0x0f,0x38,0xdd,0x64,0x3a,0x04] + aesenclast 4(%edx,%edi),%xmm4 + +// CHECK: aesdec %xmm5, %xmm6 +// CHECK: encoding: [0x66,0x0f,0x38,0xde,0xf5] + aesdec %xmm5,%xmm6 + +// CHECK: aesdec 4(%ecx,%eax,8), %xmm6 +// CHECK: encoding: [0x66,0x0f,0x38,0xde,0x74,0xc1,0x04] + aesdec 4(%ecx,%eax,8),%xmm6 + +// CHECK: aesdeclast %xmm7, %xmm0 +// CHECK: encoding: [0x66,0x0f,0x38,0xdf,0xc7] + aesdeclast %xmm7,%xmm0 + +// CHECK: aesdeclast 3405691582, %xmm0 +// CHECK: encoding: [0x66,0x0f,0x38,0xdf,0x05,0xbe,0xba,0xfe,0xca] + aesdeclast 0xcafebabe,%xmm0 + +// CHECK: aeskeygenassist $125, %xmm1, %xmm2 +// CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0xd1,0x7d] + aeskeygenassist $125, %xmm1, %xmm2 + +// CHECK: aeskeygenassist $125, (%edx,%eax,4), %xmm2 +// CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d] + aeskeygenassist $125, (%edx,%eax,4), %xmm2 + +// rdar://7840289 +// CHECK: pshufb CPI1_0(%rip), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A] +// CHECK: fixup A - offset: 5, value: CPI1_0-4 +pshufb CPI1_0(%rip), %xmm1 + diff --git a/test/MC/AsmParser/X86/x86_32-mismatched-add.s b/test/MC/AsmParser/X86/x86_32-mismatched-add.s new file mode 100644 index 0000000..0840c65 --- /dev/null +++ b/test/MC/AsmParser/X86/x86_32-mismatched-add.s @@ -0,0 +1,8 @@ +// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s +// XFAIL: * + +// CHECK: addl $4294967295, %eax # encoding: [0x83,0xc0,0xff] + addl $0xFFFFFFFF, %eax + +// CHECK: addl $65535, %eax # encoding: [0x66,0x83,0xc0,0xff] + addw $0xFFFF, %ax diff --git a/test/MC/AsmParser/X86/x86_32-new-encoder.s b/test/MC/AsmParser/X86/x86_32-new-encoder.s index 6fd0cbb..c00007f 100644 --- a/test/MC/AsmParser/X86/x86_32-new-encoder.s +++ b/test/MC/AsmParser/X86/x86_32-new-encoder.s @@ -38,4 +38,15 @@ rdtscp movl %eax, 16(%ebp) // CHECK: movl %eax, -16(%ebp) # encoding: [0x89,0x45,0xf0] movl %eax, -16(%ebp) - + +// CHECK: testb %bl, %cl # encoding: [0x84,0xcb] + testb %bl, %cl + +// CHECK: cmpl %eax, %ebx # encoding: [0x39,0xc3] + cmpl %eax, %ebx + +// CHECK: addw %ax, %ax # encoding: [0x66,0x01,0xc0] + addw %ax, %ax + +// CHECK: shrl %eax # encoding: [0xd1,0xe8] + shrl $1, %eax diff --git a/test/MC/AsmParser/X86/x86_64-encoding.s b/test/MC/AsmParser/X86/x86_64-encoding.s new file mode 100644 index 0000000..3920c5b --- /dev/null +++ b/test/MC/AsmParser/X86/x86_64-encoding.s @@ -0,0 +1,73 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +// CHECK: crc32b %bl, %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0xc3] + crc32b %bl, %eax + +// CHECK: crc32b 4(%rbx), %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0x43,0x04] + crc32b 4(%rbx), %eax + +// CHECK: crc32w %bx, %eax +// CHECK: encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc3] + crc32w %bx, %eax + +// CHECK: crc32w 4(%rbx), %eax +// CHECK: encoding: [0x66,0xf2,0x0f,0x38,0xf1,0x43,0x04] + crc32w 4(%rbx), %eax + +// CHECK: crc32l %ebx, %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0xc3] + crc32l %ebx, %eax + +// CHECK: crc32l 4(%rbx), %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x43,0x04] + crc32l 4(%rbx), %eax + +// CHECK: crc32l 3735928559(%rbx,%rcx,8), %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x8c,0xcb,0xef,0xbe,0xad,0xde] + crc32l 0xdeadbeef(%rbx,%rcx,8),%ecx + +// CHECK: crc32l 69, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0c,0x25,0x45,0x00,0x00,0x00] + crc32l 0x45,%ecx + +// CHECK: crc32l 32493, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xed,0x7e,0x00,0x00] + crc32l 0x7eed,%ecx + +// CHECK: crc32l 3133065982, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xfe,0xca,0xbe,0xba] + crc32l 0xbabecafe,%ecx + +// CHECK: crc32l %ecx, %ecx +// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0xc9] + crc32l %ecx,%ecx + +// CHECK: crc32b %r11b, %eax +// CHECK: encoding: [0xf2,0x41,0x0f,0x38,0xf0,0xc3] + crc32b %r11b, %eax + +// CHECK: crc32b 4(%rbx), %eax +// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0x43,0x04] + crc32b 4(%rbx), %eax + +// CHECK: crc32b %dil, %rax +// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf0,0xc7] + crc32b %dil,%rax + +// CHECK: crc32b %r11b, %rax +// CHECK: encoding: [0xf2,0x49,0x0f,0x38,0xf0,0xc3] + crc32b %r11b,%rax + +// CHECK: crc32b 4(%rbx), %rax +// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf0,0x43,0x04] + crc32b 4(%rbx), %rax + +// CHECK: crc32q %rbx, %rax +// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xc3] + crc32q %rbx, %rax + +// CHECK: crc32q 4(%rbx), %rax +// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf1,0x43,0x04] + crc32q 4(%rbx), %rax diff --git a/test/MC/AsmParser/X86/x86_64-incl_decl.s b/test/MC/AsmParser/X86/x86_64-incl_decl.s new file mode 100644 index 0000000..51315f8 --- /dev/null +++ b/test/MC/AsmParser/X86/x86_64-incl_decl.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck --check-prefix=CHECK-X86_32 %s +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck --check-prefix=CHECK-X86_64 %s + +# CHECK-X86_32: incb %al # encoding: [0xfe,0xc0] +# CHECK-X86_64: incb %al # encoding: [0xfe,0xc0] + incb %al + +# CHECK-X86_32: incw %ax # encoding: [0x66,0x40] +# CHECK-X86_64: incw %ax # encoding: [0x66,0xff,0xc0] + incw %ax + +# CHECK-X86_32: incl %eax # encoding: [0x40] +# CHECK-X86_64: incl %eax # encoding: [0xff,0xc0] + incl %eax + +# CHECK-X86_32: decb %al # encoding: [0xfe,0xc8] +# CHECK-X86_64: decb %al # encoding: [0xfe,0xc8] + decb %al + +# CHECK-X86_32: decw %ax # encoding: [0x66,0x48] +# CHECK-X86_64: decw %ax # encoding: [0x66,0xff,0xc8] + decw %ax + +# CHECK-X86_32: decl %eax # encoding: [0x48] +# CHECK-X86_64: decl %eax # encoding: [0xff,0xc8] + decl %eax diff --git a/test/MC/AsmParser/X86/x86_64-new-encoder.s b/test/MC/AsmParser/X86/x86_64-new-encoder.s index 56ec0b3..4028bee 100644 --- a/test/MC/AsmParser/X86/x86_64-new-encoder.s +++ b/test/MC/AsmParser/X86/x86_64-new-encoder.s @@ -24,3 +24,31 @@ movq $12, foo(%rip) // CHECK: movq $12, foo(%rip) // CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00] // CHECK: fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte + +// CHECK: addq $-424, %rax +// CHECK: encoding: [0x48,0x05,0x58,0xfe,0xff,0xff] +addq $-424, %rax + + +// CHECK: movq _foo@GOTPCREL(%rip), %rax +// CHECK: encoding: [0x48,0x8b,0x05,A,A,A,A] +// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load +movq _foo@GOTPCREL(%rip), %rax + +// CHECK: movq _foo@GOTPCREL(%rip), %r14 +// CHECK: encoding: [0x4c,0x8b,0x35,A,A,A,A] +// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load +movq _foo@GOTPCREL(%rip), %r14 + + +// CHECK: movq (%r13,%rax,8), %r13 +// CHECK: encoding: [0x4d,0x8b,0x6c,0xc5,0x00] +movq 0x00(%r13,%rax,8),%r13 + +// CHECK: testq %rax, %rbx +// CHECK: encoding: [0x48,0x85,0xd8] +testq %rax, %rbx + +// CHECK: cmpq %rbx, %r14 +// CHECK: encoding: [0x49,0x39,0xde] + cmpq %rbx, %r14 diff --git a/test/MC/AsmParser/X86/x86_64-operands.s b/test/MC/AsmParser/X86/x86_64-operands.s new file mode 100644 index 0000000..9e15779 --- /dev/null +++ b/test/MC/AsmParser/X86/x86_64-operands.s @@ -0,0 +1,9 @@ +// FIXME: Actually test that we get the expected results. + +// RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s + +# CHECK: callq a + callq a + +# CHECK: leaq -40(%rbp), %r15 + leaq -40(%rbp), %r15 diff --git a/test/MC/AsmParser/X86/x86_operands.s b/test/MC/AsmParser/X86/x86_operands.s index edddd1f..bf958d8 100644 --- a/test/MC/AsmParser/X86/x86_operands.s +++ b/test/MC/AsmParser/X86/x86_operands.s @@ -55,4 +55,6 @@ # CHECK: call *4(%eax) call *4(%eax) - +# CHECK: movl %gs:8, %eax +movl %gs:8, %eax + diff --git a/test/MC/AsmParser/exprs.s b/test/MC/AsmParser/exprs.s index 62b11c2..d9a248c 100644 --- a/test/MC/AsmParser/exprs.s +++ b/test/MC/AsmParser/exprs.s @@ -61,3 +61,14 @@ n: movw $8, (42)+66(%eax) + +// "." support: +_f0: +L0: + jmp L1 + .long . - L0 +L1: + jmp A + .long . - L1 + + .zerofill __DATA,_bss,A,0 diff --git a/test/MC/Disassembler/arm-tests.txt b/test/MC/Disassembler/arm-tests.txt new file mode 100644 index 0000000..a1e229c --- /dev/null +++ b/test/MC/Disassembler/arm-tests.txt @@ -0,0 +1,77 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s + +# CHECK: b #0 +0xfe 0xff 0xff 0xea + +# CHECK: bfc r8, #0, #16 +0x1f 0x80 0xcf 0xe7 + +# CHECK: bfi r8, r0, #16, #1 +0x10 0x88 0xd0 0xe7 + +# CHECK: cmn r0, #1 +0x01 0x00 0x70 0xe3 + +# CHECK: dmb nshst +0x56 0xf0 0x7f 0xf5 + +# CHECK: ldclvc p5, cr15, [r8], #-0 +0x00 0xf5 0x78 0x7c + +# CHECK: ldr r0, [r2], #15 +0x0f 0x00 0x92 0xe4 + +# CHECK: ldrh r0, [r2], #0 +0xb0 0x00 0xd2 0xe0 + +# CHECK: ldrht r0, [r2], #15 +0xbf 0x00 0xf2 0xe0 + +# CHECK: ldrsbtvs lr, [r2], -r9 +0xd9 0xe9 0x32 0x60 + +# CHECK: lsls r0, r2, #31 +0x82 0x0f 0xb0 0xe1 + +# CHECK: mcr2 p0, #0, r2, cr1, cr0, #7 +0xf0 0x20 0x01 0xfe + +# CHECK: movt r8, #65535 +0xff 0x8f 0x4f 0xe3 + +# CHECK: mvnpls r7, #245, 2 +0xf5 0x71 0xf0 0x53 + +# CHECK: pkhbt r8, r9, r10, lsl #4 +0x1a 0x82 0x89 0xe6 + +# CHECK: pop {r0, r2, r4, r6, r8, r10} +0x55 0x05 0xbd 0xe8 + +# CHECK: push {r0, r2, r4, r6, r8, r10} +0x55 0x05 0x2d 0xe9 + +# CHECK: qsax r8, r9, r10 +0x5a 0x8f 0x29 0xe6 + +# CHECK: rfedb r0! +0x00 0x0a 0x30 0xf9 + +# CHECK: sbcs r0, pc, #1 +0x01 0x00 0xdf 0xe2 + +# CHECK: sbfx r0, r1, #0, #8 +0x51 0x00 0xa7 0xe7 + +# CHECK: ssat r8, #1, r10, lsl #8 +0x1a 0x84 0xa0 0xe6 + +# CHECK: stmdb r10!, {r4, r5, r6, r7, lr} +0xf0 0x40 0x2a 0xe9 + +# CHECK: teq r0, #31 +0x1f 0x00 0x30 0xe3 + +# CHECK: ubfx r0, r0, #16, #1 +0x50 0x08 0xe0 0xe7 + diff --git a/test/MC/Disassembler/dg.exp b/test/MC/Disassembler/dg.exp index 68d5f1d..fc2f17a 100644 --- a/test/MC/Disassembler/dg.exp +++ b/test/MC/Disassembler/dg.exp @@ -1,4 +1,6 @@ load_lib llvm.exp -RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] +if { [llvm_supports_target ARM] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] +} diff --git a/test/MC/Disassembler/neon-tests.txt b/test/MC/Disassembler/neon-tests.txt new file mode 100644 index 0000000..51b31e7 --- /dev/null +++ b/test/MC/Disassembler/neon-tests.txt @@ -0,0 +1,48 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s + +# CHECK: vbif q15, q7, q0 +0x50 0xe1 0x7e 0xf3 + +# CHECK: vcvt.f32.s32 q15, q0, #1 +0x50 0xee 0xff 0xf2 + +# CHECK: vdup.32 q3, d1[0] +0x41 0x6c 0xb4 0xf3 + +# VLD1q8_UPD (with ${dst:dregpair} operand) +# CHECK: vld1.8 {d17, d18}, [r6], r5 +0x05 0x1a 0x66 0xf4 + +# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 +0x07 0x00 0x22 0xf4 + +# CHECK: vld4.8 {d4, d6, d8, d10}, [r2] +0x0f 0x41 0x22 0xf4 + +# CHECK: vmov d0, d15 +0x1f 0x01 0x2f 0xf2 + +# CHECK: vmov.i64 q6, #0xFF00FF00FF +0x75 0xce 0x81 0xf2 + +# CHECK: vmul.f32 d0, d0, d6 +0x16 0x0d 0x00 0xf3 + +# CHECK: vneg.f32 q0, q0 +0xc0 0x07 0xb9 0xf3 + +# CHECK: vqrdmulh.s32 d0, d0, d3[1] +0x63 0x0d 0xa0 0xf2 + +# CHECK: vrshr.s32 d0, d0, #16 +0x10 0x02 0xb0 0xf2 + +# CHECK: vshll.i16 q3, d1, #16 +0x01 0x63 0xb6 0xf3 + +# CHECK: vsri.32 q15, q0, #1 +0x50 0xe4 0xff 0xf3 + +# CHECK: vtbx.8 d18, {d4, d5, d6}, d7 +0x47 0x2a 0xf4 0xf3 + diff --git a/test/MC/Disassembler/simple-tests.txt b/test/MC/Disassembler/simple-tests.txt index 11c077d..4155261 100644 --- a/test/MC/Disassembler/simple-tests.txt +++ b/test/MC/Disassembler/simple-tests.txt @@ -41,4 +41,16 @@ 0x0f 0x01 0xf8 # CHECK: rdtscp -0x0f 0x01 0xf9
\ No newline at end of file +0x0f 0x01 0xf9 + +# CHECK: vmxon +0xf3 0x0f 0xc7 0x30 + +# CHECK: vmptrld +0x0f 0xc7 0x30 + +# CHECK: vmptrst +0x0f 0xc7 0x38 + +# CHECK: movl $0, -4(%rbp) +0xc7 0x45 0xfc 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/thumb-tests.txt b/test/MC/Disassembler/thumb-tests.txt new file mode 100644 index 0000000..14e9129 --- /dev/null +++ b/test/MC/Disassembler/thumb-tests.txt @@ -0,0 +1,93 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s + +# CHECK: add r5, sp, #68 +0x11 0xad + +# CHECK: adcs r0, r0, #1 +0x50 0xf1 0x01 0x00 + +# CHECK: b #34 +0x0f 0xe0 + +# CHECK: b.w #-12 +0xff 0xf7 0xf8 0xaf + +# CHECK: bfi r2, r10, #0, #1 +0x6a 0xf3 0x00 0x02 + +# CHECK: cbnz r7, #20 +0x57 0xb9 + +# CHECK: cmp r3, r4 +0xa3 0x42 + +# CHECK: cmn.w r0, #31 +0x10 0xf1 0x1f 0x0f + +# CHECK: ldmia r0!, {r1} +0x02 0xc8 + +# CHECK: ldrb.w r8, #-24 +0x1f 0xf8 0x18 0x80 + +# CHECK: ldrd r0, r1, [r7, #64]! +0xf7 0xe9 0x10 0x01 + +# CHECK: lsls.w r0, pc, #1 +0x5f 0xea 0x4f 0x00 + +# CHECK: mov r11, r7 +0xbb 0x46 + +# CHECK: pkhtb r2, r4, r6, asr #16 +0xc4 0xea 0x26 0x42 + +# CHECK: pop {r2, r4, r6, r8, r10, r12} +0xbd 0xe8 0x54 0x15 + +# CHECK: push {r2, r4, r6, r8, r10, r12} +0x2d 0xe9 0x54 0x15 + +# CHECK: rsbs r0, r0, #0 +0x40 0x42 + +# CHECK: strd r0, [r7, #64] +0xc7 0xe9 0x10 0x01 + +# CHECK: sub sp, #60 +0x8f 0xb0 + +# CHECK: subw r0, pc, #1 +0xaf 0xf2 0x01 0x00 + +# CHECK: subw r0, sp, #835 +0xad 0xf2 0x43 0x30 + +# CHECK: uqadd16 r3, r4, r5 +0x94 0xfa 0x55 0xf3 + +# CHECK: usada8 r5, r4, r3, r2 +0x74 0xfb 0x03 0x25 + +# CHECK: uxtab16 r1, r2, r3, ror #8 +0x32 0xfa 0x93 0xf1 + +# IT block begin +# CHECK: ittte eq +0x03 0xbf + +# CHECK: moveq r3, #3 +0x03 0x23 + +# CHECK: asreq r1, r0, #5 +0x41 0x11 + +# CHECK: lsleq r1, r0, #28 +0x01 0x07 + +# CHECK: stmiane r0!, {r1, r2, r3} +0x0e 0xc0 + +# IT block end +# CHECK: rsbs r1, r2, #0 +0x51 0x42 diff --git a/test/MC/MachO/Darwin/dg.exp b/test/MC/MachO/Darwin/dg.exp deleted file mode 100644 index 0f34b63..0000000 --- a/test/MC/MachO/Darwin/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_darwin_and_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{s}]] -} diff --git a/test/MC/MachO/Darwin/x86_32_diff_as.s b/test/MC/MachO/Darwin/x86_32_diff_as.s deleted file mode 100644 index dd5fb55..0000000 --- a/test/MC/MachO/Darwin/x86_32_diff_as.s +++ /dev/null @@ -1,550 +0,0 @@ -// Validate that we can assemble this file exactly like the platform -// assembler. -// -// RUN: llvm-mc -filetype=obj -triple i386-unknown-unknown -o %t.mc.o %s -// RUN: as -arch i386 -o %t.as.o %s -// RUN: diff %t.mc.o %t.as.o - - movb $0x7f,0xdeadbeef(%ebx,%ecx,8) - movw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - movl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - movl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - movsbl 0xdeadbeef(%ebx,%ecx,8),%ecx - movswl 0xdeadbeef(%ebx,%ecx,8),%ecx - movzbl 0xdeadbeef(%ebx,%ecx,8),%ecx - movzwl 0xdeadbeef(%ebx,%ecx,8),%ecx - pushl 0xdeadbeef(%ebx,%ecx,8) - popl 0xdeadbeef(%ebx,%ecx,8) - lahf - sahf - addb $0xfe,0xdeadbeef(%ebx,%ecx,8) - addb $0x7f,0xdeadbeef(%ebx,%ecx,8) - addw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - addl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - addl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - incl 0xdeadbeef(%ebx,%ecx,8) - subb $0xfe,0xdeadbeef(%ebx,%ecx,8) - subb $0x7f,0xdeadbeef(%ebx,%ecx,8) - subw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - subl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - subl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - decl 0xdeadbeef(%ebx,%ecx,8) - sbbw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - sbbl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - sbbl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - cmpb $0xfe,0xdeadbeef(%ebx,%ecx,8) - cmpb $0x7f,0xdeadbeef(%ebx,%ecx,8) - cmpw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - cmpl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - cmpl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - testb $0x7f,0xdeadbeef(%ebx,%ecx,8) - testw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - testl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - testl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - andb $0xfe,0xdeadbeef(%ebx,%ecx,8) - andb $0x7f,0xdeadbeef(%ebx,%ecx,8) - andw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - andl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - andl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - orb $0xfe,0xdeadbeef(%ebx,%ecx,8) - orb $0x7f,0xdeadbeef(%ebx,%ecx,8) - orw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - orl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - orl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - xorb $0xfe,0xdeadbeef(%ebx,%ecx,8) - xorb $0x7f,0xdeadbeef(%ebx,%ecx,8) - xorw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - xorl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - xorl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - adcb $0xfe,0xdeadbeef(%ebx,%ecx,8) - adcb $0x7f,0xdeadbeef(%ebx,%ecx,8) - adcw $0x7ace,0xdeadbeef(%ebx,%ecx,8) - adcl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8) - adcl $0x13572468,0xdeadbeef(%ebx,%ecx,8) - negl 0xdeadbeef(%ebx,%ecx,8) - notl 0xdeadbeef(%ebx,%ecx,8) - cbtw - cwtl - cwtd - cltd - mull 0xdeadbeef(%ebx,%ecx,8) - imull 0xdeadbeef(%ebx,%ecx,8) - divl 0xdeadbeef(%ebx,%ecx,8) - idivl 0xdeadbeef(%ebx,%ecx,8) - roll $0,0xdeadbeef(%ebx,%ecx,8) - rolb $0x7f,0xdeadbeef(%ebx,%ecx,8) - roll 0xdeadbeef(%ebx,%ecx,8) - rorl $0,0xdeadbeef(%ebx,%ecx,8) - rorb $0x7f,0xdeadbeef(%ebx,%ecx,8) - rorl 0xdeadbeef(%ebx,%ecx,8) - shll $0,0xdeadbeef(%ebx,%ecx,8) - shlb $0x7f,0xdeadbeef(%ebx,%ecx,8) - shll 0xdeadbeef(%ebx,%ecx,8) - shrl $0,0xdeadbeef(%ebx,%ecx,8) - shrb $0x7f,0xdeadbeef(%ebx,%ecx,8) - shrl 0xdeadbeef(%ebx,%ecx,8) - sarl $0,0xdeadbeef(%ebx,%ecx,8) - sarb $0x7f,0xdeadbeef(%ebx,%ecx,8) - sarl 0xdeadbeef(%ebx,%ecx,8) - call *%ecx - call *0xdeadbeef(%ebx,%ecx,8) - call *0xdeadbeef(%ebx,%ecx,8) - jmp *0xdeadbeef(%ebx,%ecx,8) - jmp *0xdeadbeef(%ebx,%ecx,8) - ljmpl *0xdeadbeef(%ebx,%ecx,8) - lret - leave - seto %bl - seto 0xdeadbeef(%ebx,%ecx,8) - setno %bl - setno 0xdeadbeef(%ebx,%ecx,8) - setb %bl - setb 0xdeadbeef(%ebx,%ecx,8) - setae %bl - setae 0xdeadbeef(%ebx,%ecx,8) - sete %bl - sete 0xdeadbeef(%ebx,%ecx,8) - setne %bl - setne 0xdeadbeef(%ebx,%ecx,8) - setbe %bl - setbe 0xdeadbeef(%ebx,%ecx,8) - seta %bl - seta 0xdeadbeef(%ebx,%ecx,8) - sets %bl - sets 0xdeadbeef(%ebx,%ecx,8) - setns %bl - setns 0xdeadbeef(%ebx,%ecx,8) - setp %bl - setp 0xdeadbeef(%ebx,%ecx,8) - setnp %bl - setnp 0xdeadbeef(%ebx,%ecx,8) - setl %bl - setl 0xdeadbeef(%ebx,%ecx,8) - setge %bl - setge 0xdeadbeef(%ebx,%ecx,8) - setle %bl - setle 0xdeadbeef(%ebx,%ecx,8) - setg %bl - setg 0xdeadbeef(%ebx,%ecx,8) - nopl 0xdeadbeef(%ebx,%ecx,8) - nop - fldl 0xdeadbeef(%ebx,%ecx,8) - fildl 0xdeadbeef(%ebx,%ecx,8) - fildll 0xdeadbeef(%ebx,%ecx,8) - fldt 0xdeadbeef(%ebx,%ecx,8) - fbld 0xdeadbeef(%ebx,%ecx,8) - fstl 0xdeadbeef(%ebx,%ecx,8) - fistl 0xdeadbeef(%ebx,%ecx,8) - fstpl 0xdeadbeef(%ebx,%ecx,8) - fistpl 0xdeadbeef(%ebx,%ecx,8) - fistpll 0xdeadbeef(%ebx,%ecx,8) - fstpt 0xdeadbeef(%ebx,%ecx,8) - fbstp 0xdeadbeef(%ebx,%ecx,8) - ficoml 0xdeadbeef(%ebx,%ecx,8) - ficompl 0xdeadbeef(%ebx,%ecx,8) - fucompp - ftst - fld1 - fldz - faddl 0xdeadbeef(%ebx,%ecx,8) - fiaddl 0xdeadbeef(%ebx,%ecx,8) - fsubl 0xdeadbeef(%ebx,%ecx,8) - fisubl 0xdeadbeef(%ebx,%ecx,8) - fsubrl 0xdeadbeef(%ebx,%ecx,8) - fisubrl 0xdeadbeef(%ebx,%ecx,8) - fmull 0xdeadbeef(%ebx,%ecx,8) - fimull 0xdeadbeef(%ebx,%ecx,8) - fdivl 0xdeadbeef(%ebx,%ecx,8) - fidivl 0xdeadbeef(%ebx,%ecx,8) - fdivrl 0xdeadbeef(%ebx,%ecx,8) - fidivrl 0xdeadbeef(%ebx,%ecx,8) - fsqrt - fsin - fcos - fchs - fabs - fldcw 0xdeadbeef(%ebx,%ecx,8) - fnstcw 0xdeadbeef(%ebx,%ecx,8) - rdtsc - sysenter - sysexit - ud2 - movnti %ecx,0xdeadbeef(%ebx,%ecx,8) - clflush 0xdeadbeef(%ebx,%ecx,8) - emms - movd %ecx,%mm3 - movd 0xdeadbeef(%ebx,%ecx,8),%mm3 - movd %ecx,%xmm5 - movd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movd %xmm5,%ecx - movd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movq 0xdeadbeef(%ebx,%ecx,8),%mm3 - movq %mm3,%mm3 - movq %mm3,%mm3 - movq %xmm5,%xmm5 - movq %xmm5,%xmm5 - packssdw %mm3,%mm3 - packssdw %xmm5,%xmm5 - packsswb %mm3,%mm3 - packsswb %xmm5,%xmm5 - packuswb %mm3,%mm3 - packuswb %xmm5,%xmm5 - paddb %mm3,%mm3 - paddb %xmm5,%xmm5 - paddw %mm3,%mm3 - paddw %xmm5,%xmm5 - paddd %mm3,%mm3 - paddd %xmm5,%xmm5 - paddq %mm3,%mm3 - paddq %xmm5,%xmm5 - paddsb %mm3,%mm3 - paddsb %xmm5,%xmm5 - paddsw %mm3,%mm3 - paddsw %xmm5,%xmm5 - paddusb %mm3,%mm3 - paddusb %xmm5,%xmm5 - paddusw %mm3,%mm3 - paddusw %xmm5,%xmm5 - pand %mm3,%mm3 - pand %xmm5,%xmm5 - pandn %mm3,%mm3 - pandn %xmm5,%xmm5 - pcmpeqb %mm3,%mm3 - pcmpeqb %xmm5,%xmm5 - pcmpeqw %mm3,%mm3 - pcmpeqw %xmm5,%xmm5 - pcmpeqd %mm3,%mm3 - pcmpeqd %xmm5,%xmm5 - pcmpgtb %mm3,%mm3 - pcmpgtb %xmm5,%xmm5 - pcmpgtw %mm3,%mm3 - pcmpgtw %xmm5,%xmm5 - pcmpgtd %mm3,%mm3 - pcmpgtd %xmm5,%xmm5 - pmaddwd %mm3,%mm3 - pmaddwd %xmm5,%xmm5 - pmulhw %mm3,%mm3 - pmulhw %xmm5,%xmm5 - pmullw %mm3,%mm3 - pmullw %xmm5,%xmm5 - por %mm3,%mm3 - por %xmm5,%xmm5 - psllw %mm3,%mm3 - psllw %xmm5,%xmm5 - psllw $0x7f,%mm3 - psllw $0x7f,%xmm5 - pslld %mm3,%mm3 - pslld %xmm5,%xmm5 - pslld $0x7f,%mm3 - pslld $0x7f,%xmm5 - psllq %mm3,%mm3 - psllq %xmm5,%xmm5 - psllq $0x7f,%mm3 - psllq $0x7f,%xmm5 - psraw %mm3,%mm3 - psraw %xmm5,%xmm5 - psraw $0x7f,%mm3 - psraw $0x7f,%xmm5 - psrad %mm3,%mm3 - psrad %xmm5,%xmm5 - psrad $0x7f,%mm3 - psrad $0x7f,%xmm5 - psrlw %mm3,%mm3 - psrlw %xmm5,%xmm5 - psrlw $0x7f,%mm3 - psrlw $0x7f,%xmm5 - psrld %mm3,%mm3 - psrld %xmm5,%xmm5 - psrld $0x7f,%mm3 - psrld $0x7f,%xmm5 - psrlq %mm3,%mm3 - psrlq %xmm5,%xmm5 - psrlq $0x7f,%mm3 - psrlq $0x7f,%xmm5 - psubb %mm3,%mm3 - psubb %xmm5,%xmm5 - psubw %mm3,%mm3 - psubw %xmm5,%xmm5 - psubd %mm3,%mm3 - psubd %xmm5,%xmm5 - psubq %mm3,%mm3 - psubq %xmm5,%xmm5 - psubsb %mm3,%mm3 - psubsb %xmm5,%xmm5 - psubsw %mm3,%mm3 - psubsw %xmm5,%xmm5 - psubusb %mm3,%mm3 - psubusb %xmm5,%xmm5 - psubusw %mm3,%mm3 - psubusw %xmm5,%xmm5 - punpckhbw %mm3,%mm3 - punpckhbw %xmm5,%xmm5 - punpckhwd %mm3,%mm3 - punpckhwd %xmm5,%xmm5 - punpckhdq %mm3,%mm3 - punpckhdq %xmm5,%xmm5 - punpcklbw %mm3,%mm3 - punpcklbw %xmm5,%xmm5 - punpcklwd %mm3,%mm3 - punpcklwd %xmm5,%xmm5 - punpckldq %mm3,%mm3 - punpckldq %xmm5,%xmm5 - pxor %mm3,%mm3 - pxor %xmm5,%xmm5 - addps %xmm5,%xmm5 - addss %xmm5,%xmm5 - andnps %xmm5,%xmm5 - andps %xmm5,%xmm5 - cvtpi2ps 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtpi2ps %mm3,%xmm5 - cvtps2pi 0xdeadbeef(%ebx,%ecx,8),%mm3 - cvtps2pi %xmm5,%mm3 - cvtsi2ss %ecx,%xmm5 - cvtsi2ss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvttps2pi 0xdeadbeef(%ebx,%ecx,8),%mm3 - cvttps2pi %xmm5,%mm3 - cvttss2si 0xdeadbeef(%ebx,%ecx,8),%ecx - cvttss2si %xmm5,%ecx - divps %xmm5,%xmm5 - divss %xmm5,%xmm5 - ldmxcsr 0xdeadbeef(%ebx,%ecx,8) - maskmovq %mm3,%mm3 - maxps %xmm5,%xmm5 - maxss %xmm5,%xmm5 - minps %xmm5,%xmm5 - minss %xmm5,%xmm5 - movaps 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movaps %xmm5,%xmm5 - movaps %xmm5,0xdeadbeef(%ebx,%ecx,8) - movaps %xmm5,%xmm5 - movhlps %xmm5,%xmm5 - movhps %xmm5,0xdeadbeef(%ebx,%ecx,8) - movlhps %xmm5,%xmm5 - movlps %xmm5,0xdeadbeef(%ebx,%ecx,8) - movmskps %xmm5,%ecx - movntps %xmm5,0xdeadbeef(%ebx,%ecx,8) - movntq %mm3,0xdeadbeef(%ebx,%ecx,8) - movntdq %xmm5,0xdeadbeef(%ebx,%ecx,8) - movss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movss %xmm5,%xmm5 - movss %xmm5,0xdeadbeef(%ebx,%ecx,8) - movss %xmm5,%xmm5 - movups 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movups %xmm5,%xmm5 - movups %xmm5,0xdeadbeef(%ebx,%ecx,8) - movups %xmm5,%xmm5 - mulps %xmm5,%xmm5 - mulss %xmm5,%xmm5 - orps %xmm5,%xmm5 - pavgb %mm3,%mm3 - pavgb %xmm5,%xmm5 - pavgw %mm3,%mm3 - pavgw %xmm5,%xmm5 - pmaxsw %mm3,%mm3 - pmaxsw %xmm5,%xmm5 - pmaxub %mm3,%mm3 - pmaxub %xmm5,%xmm5 - pminsw %mm3,%mm3 - pminsw %xmm5,%xmm5 - pminub %mm3,%mm3 - pminub %xmm5,%xmm5 - pmovmskb %mm3,%ecx - pmovmskb %xmm5,%ecx - pmulhuw %mm3,%mm3 - pmulhuw %xmm5,%xmm5 - prefetchnta 0xdeadbeef(%ebx,%ecx,8) - prefetcht0 0xdeadbeef(%ebx,%ecx,8) - prefetcht1 0xdeadbeef(%ebx,%ecx,8) - prefetcht2 0xdeadbeef(%ebx,%ecx,8) - psadbw %mm3,%mm3 - psadbw %xmm5,%xmm5 - rcpps 0xdeadbeef(%ebx,%ecx,8),%xmm5 - rcpps %xmm5,%xmm5 - rcpss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - rcpss %xmm5,%xmm5 - rsqrtps 0xdeadbeef(%ebx,%ecx,8),%xmm5 - rsqrtps %xmm5,%xmm5 - rsqrtss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - rsqrtss %xmm5,%xmm5 - sqrtps 0xdeadbeef(%ebx,%ecx,8),%xmm5 - sqrtps %xmm5,%xmm5 - sqrtss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - sqrtss %xmm5,%xmm5 - stmxcsr 0xdeadbeef(%ebx,%ecx,8) - subps %xmm5,%xmm5 - subss %xmm5,%xmm5 - ucomiss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - ucomiss %xmm5,%xmm5 - unpckhps %xmm5,%xmm5 - unpcklps %xmm5,%xmm5 - xorps %xmm5,%xmm5 - addpd %xmm5,%xmm5 - addsd %xmm5,%xmm5 - andnpd %xmm5,%xmm5 - andpd %xmm5,%xmm5 - comisd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - comisd %xmm5,%xmm5 - cvtpi2pd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtpi2pd %mm3,%xmm5 - cvtsi2sd %ecx,%xmm5 - cvtsi2sd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - divpd %xmm5,%xmm5 - divsd %xmm5,%xmm5 - maxpd %xmm5,%xmm5 - maxsd %xmm5,%xmm5 - minpd %xmm5,%xmm5 - minsd %xmm5,%xmm5 - movapd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movapd %xmm5,%xmm5 - movapd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movapd %xmm5,%xmm5 - movhpd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movlpd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movmskpd %xmm5,%ecx - movntpd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movsd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movsd %xmm5,%xmm5 - movsd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movsd %xmm5,%xmm5 - movupd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movupd %xmm5,%xmm5 - movupd %xmm5,0xdeadbeef(%ebx,%ecx,8) - movupd %xmm5,%xmm5 - mulpd %xmm5,%xmm5 - mulsd %xmm5,%xmm5 - orpd %xmm5,%xmm5 - sqrtpd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - sqrtpd %xmm5,%xmm5 - sqrtsd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - sqrtsd %xmm5,%xmm5 - subpd %xmm5,%xmm5 - subsd %xmm5,%xmm5 - ucomisd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - ucomisd %xmm5,%xmm5 - unpckhpd %xmm5,%xmm5 - unpcklpd %xmm5,%xmm5 - xorpd %xmm5,%xmm5 - cvtdq2pd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtdq2pd %xmm5,%xmm5 - cvtpd2dq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtpd2dq %xmm5,%xmm5 - cvtdq2ps 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtdq2ps %xmm5,%xmm5 - cvtpd2pi 0xdeadbeef(%ebx,%ecx,8),%mm3 - cvtpd2pi %xmm5,%mm3 - cvtps2dq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtps2dq %xmm5,%xmm5 - cvtsd2ss 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtsd2ss %xmm5,%xmm5 - cvtss2sd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - cvtss2sd %xmm5,%xmm5 - cvttpd2pi 0xdeadbeef(%ebx,%ecx,8),%mm3 - cvttpd2pi %xmm5,%mm3 - cvttsd2si 0xdeadbeef(%ebx,%ecx,8),%ecx - cvttsd2si %xmm5,%ecx - maskmovdqu %xmm5,%xmm5 - movdqa 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movdqa %xmm5,%xmm5 - movdqa %xmm5,0xdeadbeef(%ebx,%ecx,8) - movdqa %xmm5,%xmm5 - movdqu 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movdqu %xmm5,0xdeadbeef(%ebx,%ecx,8) - movdq2q %xmm5,%mm3 - movq2dq %mm3,%xmm5 - pmuludq %mm3,%mm3 - pmuludq %xmm5,%xmm5 - pslldq $0x7f,%xmm5 - psrldq $0x7f,%xmm5 - punpckhqdq %xmm5,%xmm5 - punpcklqdq %xmm5,%xmm5 - addsubpd %xmm5,%xmm5 - addsubps %xmm5,%xmm5 - haddpd %xmm5,%xmm5 - haddps %xmm5,%xmm5 - hsubpd %xmm5,%xmm5 - hsubps %xmm5,%xmm5 - lddqu 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movddup 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movddup %xmm5,%xmm5 - movshdup 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movshdup %xmm5,%xmm5 - movsldup 0xdeadbeef(%ebx,%ecx,8),%xmm5 - movsldup %xmm5,%xmm5 - phaddw %mm3,%mm3 - phaddw %xmm5,%xmm5 - phaddd %mm3,%mm3 - phaddd %xmm5,%xmm5 - phaddsw %mm3,%mm3 - phaddsw %xmm5,%xmm5 - phsubw %mm3,%mm3 - phsubw %xmm5,%xmm5 - phsubd %mm3,%mm3 - phsubd %xmm5,%xmm5 - phsubsw %mm3,%mm3 - phsubsw %xmm5,%xmm5 - pmaddubsw %mm3,%mm3 - pmaddubsw %xmm5,%xmm5 - pmulhrsw %mm3,%mm3 - pmulhrsw %xmm5,%xmm5 - pshufb %mm3,%mm3 - pshufb %xmm5,%xmm5 - psignb %mm3,%mm3 - psignb %xmm5,%xmm5 - psignw %mm3,%mm3 - psignw %xmm5,%xmm5 - psignd %mm3,%mm3 - psignd %xmm5,%xmm5 - pabsb 0xdeadbeef(%ebx,%ecx,8),%mm3 - pabsb %mm3,%mm3 - pabsb 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pabsb %xmm5,%xmm5 - pabsw 0xdeadbeef(%ebx,%ecx,8),%mm3 - pabsw %mm3,%mm3 - pabsw 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pabsw %xmm5,%xmm5 - pabsd 0xdeadbeef(%ebx,%ecx,8),%mm3 - pabsd %mm3,%mm3 - pabsd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pabsd %xmm5,%xmm5 - femms - packusdw %xmm5,%xmm5 - pcmpeqq %xmm5,%xmm5 - phminposuw 0xdeadbeef(%ebx,%ecx,8),%xmm5 - phminposuw %xmm5,%xmm5 - pmaxsb %xmm5,%xmm5 - pmaxsd %xmm5,%xmm5 - pmaxud %xmm5,%xmm5 - pmaxuw %xmm5,%xmm5 - pminsb %xmm5,%xmm5 - pminsd %xmm5,%xmm5 - pminud %xmm5,%xmm5 - pminuw %xmm5,%xmm5 - pmovsxbw 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovsxbw %xmm5,%xmm5 - pmovsxbd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovsxbd %xmm5,%xmm5 - pmovsxbq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovsxbq %xmm5,%xmm5 - pmovsxwd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovsxwd %xmm5,%xmm5 - pmovsxwq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovsxwq %xmm5,%xmm5 - pmovsxdq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovsxdq %xmm5,%xmm5 - pmovzxbw 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovzxbw %xmm5,%xmm5 - pmovzxbd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovzxbd %xmm5,%xmm5 - pmovzxbq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovzxbq %xmm5,%xmm5 - pmovzxwd 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovzxwd %xmm5,%xmm5 - pmovzxwq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovzxwq %xmm5,%xmm5 - pmovzxdq 0xdeadbeef(%ebx,%ecx,8),%xmm5 - pmovzxdq %xmm5,%xmm5 - pmuldq %xmm5,%xmm5 - pmulld %xmm5,%xmm5 - ptest 0xdeadbeef(%ebx,%ecx,8),%xmm5 - ptest %xmm5,%xmm5 - pcmpgtq %xmm5,%xmm5 diff --git a/test/MC/MachO/absolutize.s b/test/MC/MachO/absolutize.s new file mode 100644 index 0000000..76acd5b --- /dev/null +++ b/test/MC/MachO/absolutize.s @@ -0,0 +1,213 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +_text_a: + xorl %eax,%eax +_text_b: + xorl %eax,%eax +Ltext_c: + xorl %eax,%eax +Ltext_d: + xorl %eax,%eax + + movl $(_text_a - _text_b), %eax +Ltext_expr_0 = _text_a - _text_b + movl $(Ltext_expr_0), %eax + + movl $(Ltext_c - _text_b), %eax +Ltext_expr_1 = Ltext_c - _text_b + movl $(Ltext_expr_1), %eax + + movl $(Ltext_d - Ltext_c), %eax +Ltext_expr_2 = Ltext_d - Ltext_c + movl $(Ltext_expr_2), %eax + + movl $(_text_a + Ltext_expr_0), %eax + + .data +_data_a: + .long 0 +_data_b: + .long 0 +Ldata_c: + .long 0 +Ldata_d: + .long 0 + + .long _data_a - _data_b +Ldata_expr_0 = _data_a - _data_b + .long Ldata_expr_0 + + .long Ldata_c - _data_b +Ldata_expr_1 = Ldata_c - _data_b + .long Ldata_expr_1 + + .long Ldata_d - Ldata_c +Ldata_expr_2 = Ldata_d - Ldata_c + .long Ldata_expr_2 + + .long _data_a + Ldata_expr_0 + +// CHECK: ('cputype', 7) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 296) +// CHECK: ('flag', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 1) +// CHECK: ('size', 192) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 87) +// CHECK: ('file_offset', 324) +// CHECK: ('file_size', 87) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 2) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 43) +// CHECK: ('offset', 324) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 412) +// CHECK: ('num_reloc', 7) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0xa0000027), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0xa400001d), +// CHECK: ('word-1', 0x6)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x4)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0xa4000013), +// CHECK: ('word-1', 0x4)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x2)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0xa4000009), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x2)), +// CHECK: ]) +// CHECK: ('_section_data', '1\xc01\xc01\xc01\xc0\xb8\xfe\xff\xff\xff\xb8\xfe\xff\xff\xff\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\xfe\xff\xff\xff') +// CHECK: # Section 1 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 43) +// CHECK: ('size', 44) +// CHECK: ('offset', 367) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 468) +// CHECK: ('num_reloc', 7) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0xa0000028), +// CHECK: ('word-1', 0x2b)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0xa4000020), +// CHECK: ('word-1', 0x37)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x33)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0xa4000018), +// CHECK: ('word-1', 0x33)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x2f)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0xa4000010), +// CHECK: ('word-1', 0x2b)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x2f)), +// CHECK: ]) +// CHECK: ('_section_data', "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xfc\xff\xff\xff\xfc\xff\xff\xff\x04\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00'\x00\x00\x00") +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 524) +// CHECK: ('nsyms', 4) +// CHECK: ('stroff', 572) +// CHECK: ('strsize', 36) +// CHECK: ('_string_data', '\x00_text_a\x00_text_b\x00_data_a\x00_data_b\x00\x00\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_text_a') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 9) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 2) +// CHECK: ('_string', '_text_b') +// CHECK: ), +// CHECK: # Symbol 2 +// CHECK: (('n_strx', 17) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 43) +// CHECK: ('_string', '_data_a') +// CHECK: ), +// CHECK: # Symbol 3 +// CHECK: (('n_strx', 25) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 47) +// CHECK: ('_string', '_data_b') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 4) +// CHECK: ('iextdefsym', 4) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 4) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/darwin-x86_64-diff-relocs.s b/test/MC/MachO/darwin-x86_64-diff-relocs.s new file mode 100644 index 0000000..38fa074 --- /dev/null +++ b/test/MC/MachO/darwin-x86_64-diff-relocs.s @@ -0,0 +1,329 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + .text + +// FIXME: llvm-mc doesn't handle this in a way we can make compatible with 'as', +// currently, because of how we handle assembler variables. +// +// See <rdar://problem/7763719> improve handling of absolute symbols + +// _baz = 4 + +_foo: + xorl %eax,%eax +_g0: + xorl %eax,%eax +L0: + jmp 4 +// jmp _baz + +// FIXME: Darwin 'as' for historical reasons widens this jump, but doesn't emit +// a relocation. It seems like 'as' widens any jump that is not to a temporary, +// which is inherited from the x86_32 behavior, even though x86_64 could do +// better. +// jmp _g0 + + jmp L0 + jmp _g1 + +// FIXME: Darwin 'as' gets this wrong as well, even though it could get it right +// given the other things we do on x86_64. It is using a short jump here. This +// is probably fallout of the hack that exists for x86_32. +// jmp L1 + +// FIXME: We don't support this, and would currently get it wrong, it should be a jump to an absolute address. +// jmp L0 - _g0 + +// jmp _g1 - _g0 +// FIXME: Darwin 'as' comes up with 'SIGNED' here instead of 'BRANCH'. +// jmp _g1 - L1 +// FIXME: Darwin 'as' gets this completely wrong. It ends up with a single +// branch relocation. Fallout from the other delta hack? +// jmp L1 - _g0 + + jmp _g2 + jmp L2 + jmp _g3 + jmp L3 +// FIXME: Darwin 'as' gets this completely wrong. It ends up with a single +// branch relocation. Fallout from the other delta hack? +// jmp L2 - _g3 +// jmp _g3 - _g2 +// FIXME: Darwin 'as' comes up with 'SIGNED' here instead of 'BRANCH'. +// jmp _g3 - L3 +// FIXME: Darwin 'as' gets this completely wrong. It ends up with a single +// branch relocation. Fallout from the other delta hack? +// jmp L3 - _g2 + + movl %eax,4(%rip) +// movl %eax,_baz(%rip) + movl %eax,_g0(%rip) + movl %eax,L0(%rip) + movl %eax,_g1(%rip) + movl %eax,L1(%rip) + +// FIXME: Darwin 'as' gets most of these wrong, and there is an ambiguity in ATT +// syntax in what they should mean in the first place (absolute or +// rip-relative address). +// movl %eax,L0 - _g0(%rip) +// movl %eax,_g1 - _g0(%rip) +// movl %eax,_g1 - L1(%rip) +// movl %eax,L1 - _g0(%rip) + + movl %eax,_g2(%rip) + movl %eax,L2(%rip) + movl %eax,_g3(%rip) + movl %eax,L3(%rip) + +// FIXME: Darwin 'as' gets most of these wrong, and there is an ambiguity in ATT +// syntax in what they should mean in the first place (absolute or +// rip-relative address). +// movl %eax,L2 - _g2(%rip) +// movl %eax,_g3 - _g2(%rip) +// movl %eax,_g3 - L3(%rip) +// movl %eax,L3 - _g2(%rip) + +_g1: + xorl %eax,%eax +L1: + xorl %eax,%eax + + .data +_g2: + xorl %eax,%eax +L2: + .quad 4 +// .quad _baz + .quad _g2 + .quad L2 + .quad _g3 + .quad L3 + .quad L2 - _g2 + .quad _g3 - _g2 + .quad L3 - _g2 + .quad L3 - _g3 + + .quad _g0 + .quad L0 + .quad _g1 + .quad L1 + .quad L0 - _g0 + .quad _g1 - _g0 + .quad L1 - _g0 + .quad L1 - _g1 + +_g3: + xorl %eax,%eax +L3: + xorl %eax,%eax + +// CHECK: ('cputype', 16777223) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 336) +// CHECK: ('flag', 0) +// CHECK: ('reserved', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 25) +// CHECK: ('size', 232) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 236) +// CHECK: ('file_offset', 368) +// CHECK: ('file_size', 236) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 2) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 94) +// CHECK: ('offset', 368) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 604) +// CHECK: ('num_reloc', 12) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ + +// FIXME: Unfortunately, we do not get these relocations in exactly the same +// order as Darwin 'as'. It turns out that 'as' *usually* ends up emitting +// them in reverse address order, but sometimes it allocates some +// additional relocations late so these end up preceed the other entries. I +// haven't figured out the exact criteria for this yet. + +// CHECK: (('word-0', 0x56), +// CHECK: ('word-1', 0x1d000004)), +// CHECK: (('word-0', 0x50), +// CHECK: ('word-1', 0x1d000004)), +// CHECK: (('word-0', 0x4a), +// CHECK: ('word-1', 0x1d000003)), +// CHECK: (('word-0', 0x44), +// CHECK: ('word-1', 0x1d000003)), +// CHECK: (('word-0', 0x3e), +// CHECK: ('word-1', 0x1d000002)), +// CHECK: (('word-0', 0x38), +// CHECK: ('word-1', 0x1d000002)), +// CHECK: (('word-0', 0x20), +// CHECK: ('word-1', 0x2d000004)), +// CHECK: (('word-0', 0x1b), +// CHECK: ('word-1', 0x2d000004)), +// CHECK: (('word-0', 0x16), +// CHECK: ('word-1', 0x2d000003)), +// CHECK: (('word-0', 0x11), +// CHECK: ('word-1', 0x2d000003)), +// CHECK: (('word-0', 0xc), +// CHECK: ('word-1', 0x2d000002)), +// CHECK: (('word-0', 0x5), +// CHECK: ('word-1', 0x2d000000)), +// CHECK: ]) +// CHECK: # Section 1 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 94) +// CHECK: ('size', 142) +// CHECK: ('offset', 462) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 700) +// CHECK: ('num_reloc', 16) +// CHECK: ('flags', 0x400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x7a), +// CHECK: ('word-1', 0x5e000001)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0x7a), +// CHECK: ('word-1', 0xe000002)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0x72), +// CHECK: ('word-1', 0x5e000001)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0x72), +// CHECK: ('word-1', 0xe000002)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0x62), +// CHECK: ('word-1', 0xe000002)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0x5a), +// CHECK: ('word-1', 0xe000002)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0x52), +// CHECK: ('word-1', 0xe000001)), +// CHECK: # Relocation 7 +// CHECK: (('word-0', 0x4a), +// CHECK: ('word-1', 0xe000001)), +// CHECK: # Relocation 8 +// CHECK: (('word-0', 0x3a), +// CHECK: ('word-1', 0x5e000003)), +// CHECK: # Relocation 9 +// CHECK: (('word-0', 0x3a), +// CHECK: ('word-1', 0xe000004)), +// CHECK: # Relocation 10 +// CHECK: (('word-0', 0x32), +// CHECK: ('word-1', 0x5e000003)), +// CHECK: # Relocation 11 +// CHECK: (('word-0', 0x32), +// CHECK: ('word-1', 0xe000004)), +// CHECK: # Relocation 12 +// CHECK: (('word-0', 0x22), +// CHECK: ('word-1', 0xe000004)), +// CHECK: # Relocation 13 +// CHECK: (('word-0', 0x1a), +// CHECK: ('word-1', 0xe000004)), +// CHECK: # Relocation 14 +// CHECK: (('word-0', 0x12), +// CHECK: ('word-1', 0xe000003)), +// CHECK: # Relocation 15 +// CHECK: (('word-0', 0xa), +// CHECK: ('word-1', 0xe000003)), +// CHECK: ]) +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 828) +// CHECK: ('nsyms', 5) +// CHECK: ('stroff', 908) +// CHECK: ('strsize', 24) +// CHECK: ('_string_data', '\x00_foo\x00_g0\x00_g1\x00_g2\x00_g3\x00\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_foo') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 6) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 2) +// CHECK: ('_string', '_g0') +// CHECK: ), +// CHECK: # Symbol 2 +// CHECK: (('n_strx', 10) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 90) +// CHECK: ('_string', '_g1') +// CHECK: ), +// CHECK: # Symbol 3 +// CHECK: (('n_strx', 14) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 94) +// CHECK: ('_string', '_g2') +// CHECK: ), +// CHECK: # Symbol 4 +// CHECK: (('n_strx', 18) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 232) +// CHECK: ('_string', '_g3') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 5) +// CHECK: ('iextdefsym', 5) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 5) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/darwin-x86_64-reloc-offsets.s b/test/MC/MachO/darwin-x86_64-reloc-offsets.s new file mode 100644 index 0000000..ab6820e --- /dev/null +++ b/test/MC/MachO/darwin-x86_64-reloc-offsets.s @@ -0,0 +1,343 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + .data + + .org 0x10 +L0: + .long 0 + .long 0 + .long 0 + .long 0 + +_d: + .long 0 +L1: + .long 0 + + .text + +// These generate normal x86_64 (external) relocations. They could all use +// SIGNED, but don't for pedantic compatibility with Darwin 'as'. + + // SIGNED1 + movb $0x12, _d(%rip) + + // SIGNED + movb $0x12, _d + 1(%rip) + + // SIGNED4 + movl $0x12345678, _d(%rip) + + // SIGNED + movl $0x12345678, _d + 1(%rip) + + // SIGNED2 + movl $0x12345678, _d + 2(%rip) + + // SIGNED1 + movl $0x12345678, _d + 3(%rip) + + // SIGNED + movl $0x12345678, _d + 4(%rip) + + movb %al, _d(%rip) + movb %al, _d + 1(%rip) + movl %eax, _d(%rip) + movl %eax, _d + 1(%rip) + movl %eax, _d + 2(%rip) + movl %eax, _d + 3(%rip) + movl %eax, _d + 4(%rip) + +// These have to use local relocations. Since that uses an offset into the +// section in x86_64 (as opposed to a scattered relocation), and since the +// linker can only decode this to an atom + offset by scanning the section, +// it is not possible to correctly encode these without SIGNED<N>. This is +// ultimately due to a design flaw in the x86_64 relocation format, it is +// not possible to encode an address (L<foo> + <constant>) which is outside the +// atom containing L<foo>. + + // SIGNED1 + movb $0x12, L0(%rip) + + // SIGNED + movb $0x12, L0 + 1(%rip) + + // SIGNED4 + movl $0x12345678, L0(%rip) + + // SIGNED + movl $0x12345678, L0 + 1(%rip) + + // SIGNED2 + movl $0x12345678, L0 + 2(%rip) + + // SIGNED1 + movl $0x12345678, L0 + 3(%rip) + + // SIGNED + movl $0x12345678, L0 + 4(%rip) + + movb %al, L0(%rip) + movb %al, L0 + 1(%rip) + movl %eax, L0(%rip) + movl %eax, L0 + 1(%rip) + movl %eax, L0 + 2(%rip) + movl %eax, L0 + 3(%rip) + movl %eax, L0 + 4(%rip) + + // SIGNED1 + movb $0x12, L1(%rip) + + // SIGNED + movb $0x12, L1 + 1(%rip) + + // SIGNED4 + movl $0x12345678, L1(%rip) + + // SIGNED + movl $0x12345678, L1 + 1(%rip) + + // SIGNED2 + movl $0x12345678, L1 + 2(%rip) + + // SIGNED1 + movl $0x12345678, L1 + 3(%rip) + + // SIGNED + movl $0x12345678, L1 + 4(%rip) + + movb %al, L1(%rip) + movb %al, L1 + 1(%rip) + movl %eax, L1(%rip) + movl %eax, L1 + 1(%rip) + movl %eax, L1 + 2(%rip) + movl %eax, L1 + 3(%rip) + movl %eax, L1 + 4(%rip) + +// CHECK: ('cputype', 16777223) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 336) +// CHECK: ('flag', 0) +// CHECK: ('reserved', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 25) +// CHECK: ('size', 232) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 358) +// CHECK: ('file_offset', 368) +// CHECK: ('file_size', 358) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 2) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 318) +// CHECK: ('offset', 368) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 728) +// CHECK: ('num_reloc', 42) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x13a), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0x134), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0x12e), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0x128), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0x122), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0x11c), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0x116), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 7 +// CHECK: (('word-0', 0x10c), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 8 +// CHECK: (('word-0', 0x102), +// CHECK: ('word-1', 0x6d000000)), +// CHECK: # Relocation 9 +// CHECK: (('word-0', 0xf8), +// CHECK: ('word-1', 0x7d000000)), +// CHECK: # Relocation 10 +// CHECK: (('word-0', 0xee), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 11 +// CHECK: (('word-0', 0xe4), +// CHECK: ('word-1', 0x8d000000)), +// CHECK: # Relocation 12 +// CHECK: (('word-0', 0xdd), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 13 +// CHECK: (('word-0', 0xd6), +// CHECK: ('word-1', 0x6d000000)), +// CHECK: # Relocation 14 +// CHECK: (('word-0', 0xd0), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 15 +// CHECK: (('word-0', 0xca), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 16 +// CHECK: (('word-0', 0xc4), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 17 +// CHECK: (('word-0', 0xbe), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 18 +// CHECK: (('word-0', 0xb8), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 19 +// CHECK: (('word-0', 0xb2), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 20 +// CHECK: (('word-0', 0xac), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 21 +// CHECK: (('word-0', 0xa2), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 22 +// CHECK: (('word-0', 0x98), +// CHECK: ('word-1', 0x65000002)), +// CHECK: # Relocation 23 +// CHECK: (('word-0', 0x8e), +// CHECK: ('word-1', 0x75000002)), +// CHECK: # Relocation 24 +// CHECK: (('word-0', 0x84), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 25 +// CHECK: (('word-0', 0x7a), +// CHECK: ('word-1', 0x85000002)), +// CHECK: # Relocation 26 +// CHECK: (('word-0', 0x73), +// CHECK: ('word-1', 0x15000002)), +// CHECK: # Relocation 27 +// CHECK: (('word-0', 0x6c), +// CHECK: ('word-1', 0x65000002)), +// CHECK: # Relocation 28 +// CHECK: (('word-0', 0x66), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 29 +// CHECK: (('word-0', 0x60), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 30 +// CHECK: (('word-0', 0x5a), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 31 +// CHECK: (('word-0', 0x54), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 32 +// CHECK: (('word-0', 0x4e), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 33 +// CHECK: (('word-0', 0x48), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 34 +// CHECK: (('word-0', 0x42), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 35 +// CHECK: (('word-0', 0x38), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 36 +// CHECK: (('word-0', 0x2e), +// CHECK: ('word-1', 0x6d000000)), +// CHECK: # Relocation 37 +// CHECK: (('word-0', 0x24), +// CHECK: ('word-1', 0x7d000000)), +// CHECK: # Relocation 38 +// CHECK: (('word-0', 0x1a), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 39 +// CHECK: (('word-0', 0x10), +// CHECK: ('word-1', 0x8d000000)), +// CHECK: # Relocation 40 +// CHECK: (('word-0', 0x9), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 41 +// CHECK: (('word-0', 0x2), +// CHECK: ('word-1', 0x6d000000)), +// CHECK: ]) +// CHECK: ('_section_data', '\xc6\x05\xff\xff\xff\xff\x12\xc6\x05\x00\x00\x00\x00\x12\xc7\x05\xfc\xff\xff\xffxV4\x12\xc7\x05\xfd\xff\xff\xffxV4\x12\xc7\x05\xfe\xff\xff\xffxV4\x12\xc7\x05\xff\xff\xff\xffxV4\x12\xc7\x05\x00\x00\x00\x00xV4\x12\x88\x05\x00\x00\x00\x00\x88\x05\x01\x00\x00\x00\x89\x05\x00\x00\x00\x00\x89\x05\x01\x00\x00\x00\x89\x05\x02\x00\x00\x00\x89\x05\x03\x00\x00\x00\x89\x05\x04\x00\x00\x00\xc6\x05\xdd\x00\x00\x00\x12\xc6\x05\xd7\x00\x00\x00\x12\xc7\x05\xcc\x00\x00\x00xV4\x12\xc7\x05\xc3\x00\x00\x00xV4\x12\xc7\x05\xba\x00\x00\x00xV4\x12\xc7\x05\xb1\x00\x00\x00xV4\x12\xc7\x05\xa8\x00\x00\x00xV4\x12\x88\x05\x9e\x00\x00\x00\x88\x05\x99\x00\x00\x00\x89\x05\x92\x00\x00\x00\x89\x05\x8d\x00\x00\x00\x89\x05\x88\x00\x00\x00\x89\x05\x83\x00\x00\x00\x89\x05~\x00\x00\x00\xc6\x05\x03\x00\x00\x00\x12\xc6\x05\x04\x00\x00\x00\x12\xc7\x05\x00\x00\x00\x00xV4\x12\xc7\x05\x01\x00\x00\x00xV4\x12\xc7\x05\x02\x00\x00\x00xV4\x12\xc7\x05\x03\x00\x00\x00xV4\x12\xc7\x05\x04\x00\x00\x00xV4\x12\x88\x05\x04\x00\x00\x00\x88\x05\x05\x00\x00\x00\x89\x05\x04\x00\x00\x00\x89\x05\x05\x00\x00\x00\x89\x05\x06\x00\x00\x00\x89\x05\x07\x00\x00\x00\x89\x05\x08\x00\x00\x00') +// CHECK: # Section 1 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 318) +// CHECK: ('size', 40) +// CHECK: ('offset', 686) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 1064) +// CHECK: ('nsyms', 1) +// CHECK: ('stroff', 1080) +// CHECK: ('strsize', 4) +// CHECK: ('_string_data', '\x00_d\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 350) +// CHECK: ('_string', '_d') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 1) +// CHECK: ('iextdefsym', 1) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 1) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/darwin-x86_64-reloc.s b/test/MC/MachO/darwin-x86_64-reloc.s new file mode 100644 index 0000000..d5e75d1 --- /dev/null +++ b/test/MC/MachO/darwin-x86_64-reloc.s @@ -0,0 +1,264 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +// These examples are taken from <mach-o/x86_64/reloc.h>. + + .text +_foo: + ret + +_baz: + call _foo + call _foo+4 + movq _foo@GOTPCREL(%rip), %rax + pushq _foo@GOTPCREL(%rip) + movl _foo(%rip), %eax + movl _foo+4(%rip), %eax + movb $0x12, _foo(%rip) + movl $0x12345678, _foo(%rip) + .quad _foo +_bar: + .quad _foo+4 + .quad _foo - _bar + .quad _foo - _bar + 4 + .long _foo - _bar + leaq L1(%rip), %rax + leaq L0(%rip), %rax + addl $6,L0(%rip) + addw $500,L0(%rip) + addl $500,L0(%rip) + +_prev: + .space 12,0x90 + .quad L1 +L0: + .quad L0 +L_pc: + .quad _foo - L_pc + .quad _foo - L1 +L1: + .quad L1 - _prev + + .data +.long _foobar@GOTPCREL+4 +.long _foo@GOTPCREL+4 + +// CHECK: ('cputype', 16777223) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 336) +// CHECK: ('flag', 0) +// CHECK: ('reserved', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 25) +// CHECK: ('size', 232) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 189) +// CHECK: ('file_offset', 368) +// CHECK: ('file_size', 189) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 2) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 181) +// CHECK: ('offset', 368) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 560) +// CHECK: ('num_reloc', 27) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0xa5), +// CHECK: ('word-1', 0x5e000003)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0xa5), +// CHECK: ('word-1', 0xe000000)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0x9d), +// CHECK: ('word-1', 0x5e000003)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0x9d), +// CHECK: ('word-1', 0xe000000)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0x95), +// CHECK: ('word-1', 0xe000003)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0x8d), +// CHECK: ('word-1', 0xe000003)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0x79), +// CHECK: ('word-1', 0x8d000003)), +// CHECK: # Relocation 7 +// CHECK: (('word-0', 0x71), +// CHECK: ('word-1', 0x7d000003)), +// CHECK: # Relocation 8 +// CHECK: (('word-0', 0x69), +// CHECK: ('word-1', 0x6d000003)), +// CHECK: # Relocation 9 +// CHECK: (('word-0', 0x63), +// CHECK: ('word-1', 0x1d000003)), +// CHECK: # Relocation 10 +// CHECK: (('word-0', 0x5c), +// CHECK: ('word-1', 0x1d000003)), +// CHECK: # Relocation 11 +// CHECK: (('word-0', 0x55), +// CHECK: ('word-1', 0x5c000002)), +// CHECK: # Relocation 12 +// CHECK: (('word-0', 0x55), +// CHECK: ('word-1', 0xc000000)), +// CHECK: # Relocation 13 +// CHECK: (('word-0', 0x4d), +// CHECK: ('word-1', 0x5e000002)), +// CHECK: # Relocation 14 +// CHECK: (('word-0', 0x4d), +// CHECK: ('word-1', 0xe000000)), +// CHECK: # Relocation 15 +// CHECK: (('word-0', 0x45), +// CHECK: ('word-1', 0x5e000002)), +// CHECK: # Relocation 16 +// CHECK: (('word-0', 0x45), +// CHECK: ('word-1', 0xe000000)), +// CHECK: # Relocation 17 +// CHECK: (('word-0', 0x3d), +// CHECK: ('word-1', 0xe000000)), +// CHECK: # Relocation 18 +// CHECK: (('word-0', 0x35), +// CHECK: ('word-1', 0xe000000)), +// CHECK: # Relocation 19 +// CHECK: (('word-0', 0x2d), +// CHECK: ('word-1', 0x8d000000)), +// CHECK: # Relocation 20 +// CHECK: (('word-0', 0x26), +// CHECK: ('word-1', 0x6d000000)), +// CHECK: # Relocation 21 +// CHECK: (('word-0', 0x20), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 22 +// CHECK: (('word-0', 0x1a), +// CHECK: ('word-1', 0x1d000000)), +// CHECK: # Relocation 23 +// CHECK: (('word-0', 0x14), +// CHECK: ('word-1', 0x4d000000)), +// CHECK: # Relocation 24 +// CHECK: (('word-0', 0xe), +// CHECK: ('word-1', 0x3d000000)), +// CHECK: # Relocation 25 +// CHECK: (('word-0', 0x7), +// CHECK: ('word-1', 0x2d000000)), +// CHECK: # Relocation 26 +// CHECK: (('word-0', 0x2), +// CHECK: ('word-1', 0x2d000000)), +// CHECK: ]) +// CHECK: ('_section_data', '\xc3\xe8\x00\x00\x00\x00\xe8\x04\x00\x00\x00H\x8b\x05\x00\x00\x00\x00\xff5\x00\x00\x00\x00\x8b\x05\x00\x00\x00\x00\x8b\x05\x04\x00\x00\x00\xc6\x05\xff\xff\xff\xff\x12\xc7\x05\xfc\xff\xff\xffxV4\x12\x00\x00\x00\x00\x00\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00H\x8d\x05,\x00\x00\x00H\x8d\x05\x14\x00\x00\x00\x83\x05\x13\x00\x00\x00\x06f\x81\x05\x12\x00\x00\x00\xf4\x01\x81\x05\x10\x00\x00\x00\xf4\x01\x00\x00\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90,\x00\x00\x00\x00\x00\x00\x00\x14\x00\x00\x00\x00\x00\x00\x00\xe4\xff\xff\xff\xff\xff\xff\xff\xd4\xff\xff\xff\xff\xff\xff\xff,\x00\x00\x00\x00\x00\x00\x00') +// CHECK: # Section 1 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 181) +// CHECK: ('size', 8) +// CHECK: ('offset', 549) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 776) +// CHECK: ('num_reloc', 2) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x4), +// CHECK: ('word-1', 0x4d000000)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0x0), +// CHECK: ('word-1', 0x4d000004)), +// CHECK: ]) +// CHECK: ('_section_data', '\x04\x00\x00\x00\x04\x00\x00\x00') +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 792) +// CHECK: ('nsyms', 5) +// CHECK: ('stroff', 872) +// CHECK: ('strsize', 32) +// CHECK: ('_string_data', '\x00_foobar\x00_foo\x00_baz\x00_bar\x00_prev\x00\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 9) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_foo') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 14) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 1) +// CHECK: ('_string', '_baz') +// CHECK: ), +// CHECK: # Symbol 2 +// CHECK: (('n_strx', 19) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 61) +// CHECK: ('_string', '_bar') +// CHECK: ), +// CHECK: # Symbol 3 +// CHECK: (('n_strx', 24) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 129) +// CHECK: ('_string', '_prev') +// CHECK: ), +// CHECK: # Symbol 4 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_foobar') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 4) +// CHECK: ('iextdefsym', 4) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 4) +// CHECK: ('nundefsym', 1) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/relax-jumps.s b/test/MC/MachO/relax-jumps.s new file mode 100644 index 0000000..9c58aa76 --- /dev/null +++ b/test/MC/MachO/relax-jumps.s @@ -0,0 +1,31 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +// FIXME: This is a horrible way of checking the output, we need an llvm-mc +// based 'otool'. Use: +// (f=relax-jumps; +// llvm-mc -filetype=obj -o $f.mc.o $f.s && +// as -arch i386 -o $f.as.o $f.s && +// otool -tvr $f.mc.o | tail +2 > $f.mc.dump && +// otool -tvr $f.as.o | tail +2 > $f.as.dump && +// diff $f.{as,mc}.dump) +// to examine the results in a more sensible fashion. + +// CHECK: ('_section_data', '\x90 +// CHECK: \x0f\x842\xff\xff\xff\x0f\x82\xe6\x00\x00\x00\x0f\x87&\xff\xff\xff\x0f\x8f\xda\x00\x00\x00\x0f\x88\x1a\xff\xff\xff\x0f\x83\xce\x00\x00\x00\x0f\x89\x0e\xff\xff\xff\x90 +// CHECK: \x901\xc0') + +L1: + .space 200, 0x90 + + je L1 + jb L2 + ja L1 + jg L2 + js L1 + jae L2 + jns L1 + + .space 200, 0x90 +L2: + + xorl %eax, %eax diff --git a/test/MC/MachO/relax-recompute-align.s b/test/MC/MachO/relax-recompute-align.s new file mode 100644 index 0000000..2494025 --- /dev/null +++ b/test/MC/MachO/relax-recompute-align.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +// FIXME: This is a horrible way of checking the output, we need an llvm-mc +// based 'otool'. + +// This is a case where llvm-mc computes a better layout than Darwin 'as'. This +// issue is that after the first jmp slides, the .align size must be +// recomputed -- otherwise the second jump will appear to be out-of-range for a +// 1-byte jump. + +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 306) +// CHECK: ('offset', 324) +// CHECK: ('alignment', 4) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), + +L0: + .space 0x8a, 0x90 + jmp L0 + .space (0xb3 - 0x8f), 0x90 + jle L2 + .space (0xcd - 0xb5), 0x90 + .align 4, 0x90 +L1: + .space (0x130 - 0xd0),0x90 + jl L1 +L2: + +.zerofill __DATA,__bss,_sym,4,2 diff --git a/test/MC/MachO/reloc-diff.s b/test/MC/MachO/reloc-diff.s new file mode 100644 index 0000000..601edba --- /dev/null +++ b/test/MC/MachO/reloc-diff.s @@ -0,0 +1,55 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s + +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0xa2000014), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0xa4000010), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0xa400000c), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0xa4000008), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 7 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 8 +// CHECK: (('word-0', 0xa4000004), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 9 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 10 +// CHECK: (('word-0', 0xa2000000), +// CHECK: ('word-1', 0x0)), +// CHECK: # Relocation 11 +// CHECK: (('word-0', 0xa1000000), +// CHECK: ('word-1', 0x0)), +// CHECK-NEXT: ]) + +_local_def: + .globl _external_def +_external_def: +Ltemp: + ret + + .data + .long _external_def - _local_def + .long Ltemp - _local_def + + .long _local_def - _external_def + .long Ltemp - _external_def + + .long _local_def - Ltemp + .long _external_def - Ltemp diff --git a/test/MC/MachO/reloc-pcrel-offset.s b/test/MC/MachO/reloc-pcrel-offset.s new file mode 100644 index 0000000..46dc3a9 --- /dev/null +++ b/test/MC/MachO/reloc-pcrel-offset.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -n -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x1), +// CHECK: ('word-1', 0x5000002)), +// CHECK-NEXT: ]) +// CHECK: ('_section_data', '\xe8\xfb\xff\xff\xff') + + .data + .long 0 + + .text +_a: + call _a diff --git a/test/MC/MachO/reloc-pcrel.s b/test/MC/MachO/reloc-pcrel.s new file mode 100644 index 0000000..fff7cc0 --- /dev/null +++ b/test/MC/MachO/reloc-pcrel.s @@ -0,0 +1,62 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s + +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0xe4000045), +// CHECK: ('word-1', 0x4)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0xe1000000), +// CHECK: ('word-1', 0x6)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0x40), +// CHECK: ('word-1', 0xd000002)), +// CHECK: # Relocation 3 +// CHECK: (('word-0', 0x3b), +// CHECK: ('word-1', 0xd000002)), +// CHECK: # Relocation 4 +// CHECK: (('word-0', 0x36), +// CHECK: ('word-1', 0xd000002)), +// CHECK: # Relocation 5 +// CHECK: (('word-0', 0xe0000031), +// CHECK: ('word-1', 0x4)), +// CHECK: # Relocation 6 +// CHECK: (('word-0', 0xe000002c), +// CHECK: ('word-1', 0x4)), +// CHECK: # Relocation 7 +// CHECK: (('word-0', 0x27), +// CHECK: ('word-1', 0x5000001)), +// CHECK: # Relocation 8 +// CHECK: (('word-0', 0xe0000022), +// CHECK: ('word-1', 0x2)), +// CHECK: # Relocation 9 +// CHECK: (('word-0', 0xe000001d), +// CHECK: ('word-1', 0x2)), +// CHECK: # Relocation 10 +// CHECK: (('word-0', 0x18), +// CHECK: ('word-1', 0x5000001)), +// CHECK-NEXT: ]) + + xorl %eax,%eax + + .globl _a +_a: + xorl %eax,%eax +_b: + xorl %eax,%eax +L0: + xorl %eax,%eax +L1: + + call L0 + call L0 - 1 + call L0 + 1 + call _a + call _a - 1 + call _a + 1 + call _b + call _b - 1 + call _b + 1 + call _c + call _c - 1 + call _c + 1 +// call _a - L0 + call _b - L0 diff --git a/test/MC/MachO/reloc.s b/test/MC/MachO/reloc.s index e86ed8c..c305eeb 100644 --- a/test/MC/MachO/reloc.s +++ b/test/MC/MachO/reloc.s @@ -10,7 +10,7 @@ local_a_ext: local_a: .long 0 -local_a_elt: +local_a_elt: .long 0 local_b: .long local_b - local_c + 245 @@ -27,9 +27,20 @@ local_c: .const .long -bar: +bar: .long local_a_elt - bar + 33 +L0: + .long L0 + .long L1 + + .text +_f0: +L1: + jmp L0 + jmp L1 + ret + // CHECK: ('cputype', 7) // CHECK: ('cpusubtype', 3) // CHECK: ('filetype', 1) @@ -42,9 +53,9 @@ bar: // CHECK: ('size', 260) // CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('vm_addr', 0) -// CHECK: ('vm_size', 47) +// CHECK: ('vm_size', 63) // CHECK: ('file_offset', 392) -// CHECK: ('file_size', 47) +// CHECK: ('file_size', 63) // CHECK: ('maxprot', 7) // CHECK: ('initprot', 7) // CHECK: ('num_sections', 3) @@ -54,26 +65,29 @@ bar: // CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('address', 0) -// CHECK: ('size', 0) +// CHECK: ('size', 8) // CHECK: ('offset', 392) // CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 0) -// CHECK: ('num_reloc', 0) -// CHECK: ('flags', 0x80000000) +// CHECK: ('reloc_offset', 456) +// CHECK: ('num_reloc', 1) +// CHECK: ('flags', 0x80000400) // CHECK: ('reserved1', 0) // CHECK: ('reserved2', 0) // CHECK: ), // CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x1), +// CHECK: ('word-1', 0x5000003)), // CHECK: ]) -// CHECK: ('_section_data', '') +// CHECK: ('_section_data', '\xe92\x00\x00\x00\xeb\xf9\xc3') // CHECK: # Section 1 // CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('address', 0) +// CHECK: ('address', 8) // CHECK: ('size', 43) -// CHECK: ('offset', 392) +// CHECK: ('offset', 400) // CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 440) +// CHECK: ('reloc_offset', 464) // CHECK: ('num_reloc', 9) // CHECK: ('flags', 0x0) // CHECK: ('reserved1', 0) @@ -82,72 +96,78 @@ bar: // CHECK: ('_relocations', [ // CHECK: # Relocation 0 // CHECK: (('word-0', 0x8000002a), -// CHECK: ('word-1', 0x10)), +// CHECK: ('word-1', 0x18)), // CHECK: # Relocation 1 // CHECK: (('word-0', 0x90000028), -// CHECK: ('word-1', 0x10)), +// CHECK: ('word-1', 0x18)), // CHECK: # Relocation 2 // CHECK: (('word-0', 0xa0000024), -// CHECK: ('word-1', 0x10)), +// CHECK: ('word-1', 0x18)), // CHECK: # Relocation 3 // CHECK: (('word-0', 0xa0000020), -// CHECK: ('word-1', 0x10)), +// CHECK: ('word-1', 0x18)), // CHECK: # Relocation 4 // CHECK: (('word-0', 0xa4000014), -// CHECK: ('word-1', 0x14)), +// CHECK: ('word-1', 0x1c)), // CHECK: # Relocation 5 // CHECK: (('word-0', 0xa1000000), -// CHECK: ('word-1', 0x1c)), +// CHECK: ('word-1', 0x24)), // CHECK: # Relocation 6 // CHECK: (('word-0', 0x8), // CHECK: ('word-1', 0x4000002)), // CHECK: # Relocation 7 // CHECK: (('word-0', 0x4), -// CHECK: ('word-1', 0xc000006)), +// CHECK: ('word-1', 0xc000007)), // CHECK: # Relocation 8 // CHECK: (('word-0', 0x0), -// CHECK: ('word-1', 0xc000006)), +// CHECK: ('word-1', 0xc000007)), // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x04\x00\x00\x00\x08\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xed\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x11\x00\x00\x00\x1a\x00\x00\x00$\x00i') +// CHECK: ('_section_data', '\x00\x00\x00\x00\x04\x00\x00\x00\x10\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xed\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x19\x00\x00\x00"\x00\x00\x00,\x00q') // CHECK: # Section 2 // CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('address', 43) -// CHECK: ('size', 4) -// CHECK: ('offset', 435) +// CHECK: ('address', 51) +// CHECK: ('size', 12) +// CHECK: ('offset', 443) // CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 512) -// CHECK: ('num_reloc', 2) +// CHECK: ('reloc_offset', 536) +// CHECK: ('num_reloc', 4) // CHECK: ('flags', 0x0) // CHECK: ('reserved1', 0) // CHECK: ('reserved2', 0) // CHECK: ), // CHECK: ('_relocations', [ // CHECK: # Relocation 0 -// CHECK: (('word-0', 0xa4000000), -// CHECK: ('word-1', 0x10)), +// CHECK: (('word-0', 0x8), +// CHECK: ('word-1', 0x4000001)), // CHECK: # Relocation 1 +// CHECK: (('word-0', 0x4), +// CHECK: ('word-1', 0x4000003)), +// CHECK: # Relocation 2 +// CHECK: (('word-0', 0xa4000000), +// CHECK: ('word-1', 0x18)), +// CHECK: # Relocation 3 // CHECK: (('word-0', 0xa1000000), -// CHECK: ('word-1', 0x2b)), +// CHECK: ('word-1', 0x33)), // CHECK: ]) -// CHECK: ('_section_data', '\x06\x00\x00\x00') +// CHECK: ('_section_data', '\x06\x00\x00\x007\x00\x00\x00\x00\x00\x00\x00') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 // CHECK: (('command', 2) // CHECK: ('size', 24) -// CHECK: ('symoff', 528) -// CHECK: ('nsyms', 7) -// CHECK: ('stroff', 612) -// CHECK: ('strsize', 60) -// CHECK: ('_string_data', '\x00undef\x00local_a_ext\x00local_a\x00local_a_elt\x00local_b\x00local_c\x00bar\x00\x00') +// CHECK: ('symoff', 568) +// CHECK: ('nsyms', 8) +// CHECK: ('stroff', 664) +// CHECK: ('strsize', 64) +// CHECK: ('_string_data', '\x00undef\x00local_a_ext\x00local_a\x00local_a_elt\x00local_b\x00local_c\x00bar\x00_f0\x00\x00') // CHECK: ('_symbols', [ // CHECK: # Symbol 0 // CHECK: (('n_strx', 19) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 12) +// CHECK: ('n_value', 20) // CHECK: ('_string', 'local_a') // CHECK: ), // CHECK: # Symbol 1 @@ -155,7 +175,7 @@ bar: // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 16) +// CHECK: ('n_value', 24) // CHECK: ('_string', 'local_a_elt') // CHECK: ), // CHECK: # Symbol 2 @@ -163,7 +183,7 @@ bar: // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 20) +// CHECK: ('n_value', 28) // CHECK: ('_string', 'local_b') // CHECK: ), // CHECK: # Symbol 3 @@ -171,7 +191,7 @@ bar: // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 28) +// CHECK: ('n_value', 36) // CHECK: ('_string', 'local_c') // CHECK: ), // CHECK: # Symbol 4 @@ -179,18 +199,26 @@ bar: // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 3) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 43) +// CHECK: ('n_value', 51) // CHECK: ('_string', 'bar') // CHECK: ), // CHECK: # Symbol 5 +// CHECK: (('n_strx', 59) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_f0') +// CHECK: ), +// CHECK: # Symbol 6 // CHECK: (('n_strx', 7) // CHECK: ('n_type', 0xf) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 8) +// CHECK: ('n_value', 16) // CHECK: ('_string', 'local_a_ext') // CHECK: ), -// CHECK: # Symbol 6 +// CHECK: # Symbol 7 // CHECK: (('n_strx', 1) // CHECK: ('n_type', 0x1) // CHECK: ('n_sect', 0) @@ -204,10 +232,10 @@ bar: // CHECK: (('command', 11) // CHECK: ('size', 80) // CHECK: ('ilocalsym', 0) -// CHECK: ('nlocalsym', 5) -// CHECK: ('iextdefsym', 5) +// CHECK: ('nlocalsym', 6) +// CHECK: ('iextdefsym', 6) // CHECK: ('nextdefsym', 1) -// CHECK: ('iundefsym', 6) +// CHECK: ('iundefsym', 7) // CHECK: ('nundefsym', 1) // CHECK: ('tocoff', 0) // CHECK: ('ntoc', 0) diff --git a/test/MC/MachO/symbols-1.s b/test/MC/MachO/symbols-1.s index 4c72fb3..623e528 100644 --- a/test/MC/MachO/symbols-1.s +++ b/test/MC/MachO/symbols-1.s @@ -1,4 +1,5 @@ -// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck -check-prefix CHECK-X86_32 %s +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o - | macho-dump | FileCheck -check-prefix CHECK-X86_64 %s sym_local_B: .globl sym_globl_def_B @@ -16,146 +17,294 @@ sym_globl_def_C: Lsym_asm_temp: .long 0 -// CHECK: ('cputype', 7) -// CHECK: ('cpusubtype', 3) -// CHECK: ('filetype', 1) -// CHECK: ('num_load_commands', 1) -// CHECK: ('load_commands_size', 228) -// CHECK: ('flag', 0) -// CHECK: ('load_commands', [ -// CHECK: # Load Command 0 -// CHECK: (('command', 1) -// CHECK: ('size', 124) -// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('vm_addr', 0) -// CHECK: ('vm_size', 4) -// CHECK: ('file_offset', 256) -// CHECK: ('file_size', 4) -// CHECK: ('maxprot', 7) -// CHECK: ('initprot', 7) -// CHECK: ('num_sections', 1) -// CHECK: ('flags', 0) -// CHECK: ('sections', [ -// CHECK: # Section 0 -// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('address', 0) -// CHECK: ('size', 4) -// CHECK: ('offset', 256) -// CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 0) -// CHECK: ('num_reloc', 0) -// CHECK: ('flags', 0x80000000) -// CHECK: ('reserved1', 0) -// CHECK: ('reserved2', 0) -// CHECK: ), -// CHECK: ]) -// CHECK: ), -// CHECK: # Load Command 1 -// CHECK: (('command', 2) -// CHECK: ('size', 24) -// CHECK: ('symoff', 260) -// CHECK: ('nsyms', 9) -// CHECK: ('stroff', 368) -// CHECK: ('strsize', 140) -// CHECK: ('_string_data', '\x00sym_globl_def_B\x00sym_globl_undef_B\x00sym_globl_def_A\x00sym_globl_undef_A\x00sym_globl_def_C\x00sym_globl_undef_C\x00sym_local_B\x00sym_local_A\x00sym_local_C\x00\x00') -// CHECK: ('_symbols', [ -// CHECK: # Symbol 0 -// CHECK: (('n_strx', 103) -// CHECK: ('n_type', 0xe) -// CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_local_B') -// CHECK: ), -// CHECK: # Symbol 1 -// CHECK: (('n_strx', 115) -// CHECK: ('n_type', 0xe) -// CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_local_A') -// CHECK: ), -// CHECK: # Symbol 2 -// CHECK: (('n_strx', 127) -// CHECK: ('n_type', 0xe) -// CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_local_C') -// CHECK: ), -// CHECK: # Symbol 3 -// CHECK: (('n_strx', 35) -// CHECK: ('n_type', 0xf) -// CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_globl_def_A') -// CHECK: ), -// CHECK: # Symbol 4 -// CHECK: (('n_strx', 1) -// CHECK: ('n_type', 0xf) -// CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_globl_def_B') -// CHECK: ), -// CHECK: # Symbol 5 -// CHECK: (('n_strx', 69) -// CHECK: ('n_type', 0xf) -// CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_globl_def_C') -// CHECK: ), -// CHECK: # Symbol 6 -// CHECK: (('n_strx', 51) -// CHECK: ('n_type', 0x1) -// CHECK: ('n_sect', 0) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_globl_undef_A') -// CHECK: ), -// CHECK: # Symbol 7 -// CHECK: (('n_strx', 17) -// CHECK: ('n_type', 0x1) -// CHECK: ('n_sect', 0) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_globl_undef_B') -// CHECK: ), -// CHECK: # Symbol 8 -// CHECK: (('n_strx', 85) -// CHECK: ('n_type', 0x1) -// CHECK: ('n_sect', 0) -// CHECK: ('n_desc', 0) -// CHECK: ('n_value', 0) -// CHECK: ('_string', 'sym_globl_undef_C') -// CHECK: ), -// CHECK: ]) -// CHECK: ), -// CHECK: # Load Command 2 -// CHECK: (('command', 11) -// CHECK: ('size', 80) -// CHECK: ('ilocalsym', 0) -// CHECK: ('nlocalsym', 3) -// CHECK: ('iextdefsym', 3) -// CHECK: ('nextdefsym', 3) -// CHECK: ('iundefsym', 6) -// CHECK: ('nundefsym', 3) -// CHECK: ('tocoff', 0) -// CHECK: ('ntoc', 0) -// CHECK: ('modtaboff', 0) -// CHECK: ('nmodtab', 0) -// CHECK: ('extrefsymoff', 0) -// CHECK: ('nextrefsyms', 0) -// CHECK: ('indirectsymoff', 0) -// CHECK: ('nindirectsyms', 0) -// CHECK: ('extreloff', 0) -// CHECK: ('nextrel', 0) -// CHECK: ('locreloff', 0) -// CHECK: ('nlocrel', 0) -// CHECK: ('_indirect_symbols', [ -// CHECK: ]) -// CHECK: ), -// CHECK: ]) +// CHECK-X86_32: ('cputype', 7) +// CHECK-X86_32: ('cpusubtype', 3) +// CHECK-X86_32: ('filetype', 1) +// CHECK-X86_32: ('num_load_commands', 1) +// CHECK-X86_32: ('load_commands_size', 228) +// CHECK-X86_32: ('flag', 0) +// CHECK-X86_32: ('load_commands', [ +// CHECK-X86_32: # Load Command 0 +// CHECK-X86_32: (('command', 1) +// CHECK-X86_32: ('size', 124) +// CHECK-X86_32: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_32: ('vm_addr', 0) +// CHECK-X86_32: ('vm_size', 4) +// CHECK-X86_32: ('file_offset', 256) +// CHECK-X86_32: ('file_size', 4) +// CHECK-X86_32: ('maxprot', 7) +// CHECK-X86_32: ('initprot', 7) +// CHECK-X86_32: ('num_sections', 1) +// CHECK-X86_32: ('flags', 0) +// CHECK-X86_32: ('sections', [ +// CHECK-X86_32: # Section 0 +// CHECK-X86_32: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_32: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_32: ('address', 0) +// CHECK-X86_32: ('size', 4) +// CHECK-X86_32: ('offset', 256) +// CHECK-X86_32: ('alignment', 0) +// CHECK-X86_32: ('reloc_offset', 0) +// CHECK-X86_32: ('num_reloc', 0) +// CHECK-X86_32: ('flags', 0x80000000) +// CHECK-X86_32: ('reserved1', 0) +// CHECK-X86_32: ('reserved2', 0) +// CHECK-X86_32: ), +// CHECK-X86_32: ]) +// CHECK-X86_32: ), +// CHECK-X86_32: # Load Command 1 +// CHECK-X86_32: (('command', 2) +// CHECK-X86_32: ('size', 24) +// CHECK-X86_32: ('symoff', 260) +// CHECK-X86_32: ('nsyms', 9) +// CHECK-X86_32: ('stroff', 368) +// CHECK-X86_32: ('strsize', 140) +// CHECK-X86_32: ('_string_data', '\x00sym_globl_def_B\x00sym_globl_undef_B\x00sym_globl_def_A\x00sym_globl_undef_A\x00sym_globl_def_C\x00sym_globl_undef_C\x00sym_local_B\x00sym_local_A\x00sym_local_C\x00\x00') +// CHECK-X86_32: ('_symbols', [ +// CHECK-X86_32: # Symbol 0 +// CHECK-X86_32: (('n_strx', 103) +// CHECK-X86_32: ('n_type', 0xe) +// CHECK-X86_32: ('n_sect', 1) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_local_B') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 1 +// CHECK-X86_32: (('n_strx', 115) +// CHECK-X86_32: ('n_type', 0xe) +// CHECK-X86_32: ('n_sect', 1) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_local_A') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 2 +// CHECK-X86_32: (('n_strx', 127) +// CHECK-X86_32: ('n_type', 0xe) +// CHECK-X86_32: ('n_sect', 1) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_local_C') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 3 +// CHECK-X86_32: (('n_strx', 35) +// CHECK-X86_32: ('n_type', 0xf) +// CHECK-X86_32: ('n_sect', 1) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_globl_def_A') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 4 +// CHECK-X86_32: (('n_strx', 1) +// CHECK-X86_32: ('n_type', 0xf) +// CHECK-X86_32: ('n_sect', 1) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_globl_def_B') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 5 +// CHECK-X86_32: (('n_strx', 69) +// CHECK-X86_32: ('n_type', 0xf) +// CHECK-X86_32: ('n_sect', 1) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_globl_def_C') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 6 +// CHECK-X86_32: (('n_strx', 51) +// CHECK-X86_32: ('n_type', 0x1) +// CHECK-X86_32: ('n_sect', 0) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_globl_undef_A') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 7 +// CHECK-X86_32: (('n_strx', 17) +// CHECK-X86_32: ('n_type', 0x1) +// CHECK-X86_32: ('n_sect', 0) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_globl_undef_B') +// CHECK-X86_32: ), +// CHECK-X86_32: # Symbol 8 +// CHECK-X86_32: (('n_strx', 85) +// CHECK-X86_32: ('n_type', 0x1) +// CHECK-X86_32: ('n_sect', 0) +// CHECK-X86_32: ('n_desc', 0) +// CHECK-X86_32: ('n_value', 0) +// CHECK-X86_32: ('_string', 'sym_globl_undef_C') +// CHECK-X86_32: ), +// CHECK-X86_32: ]) +// CHECK-X86_32: ), +// CHECK-X86_32: # Load Command 2 +// CHECK-X86_32: (('command', 11) +// CHECK-X86_32: ('size', 80) +// CHECK-X86_32: ('ilocalsym', 0) +// CHECK-X86_32: ('nlocalsym', 3) +// CHECK-X86_32: ('iextdefsym', 3) +// CHECK-X86_32: ('nextdefsym', 3) +// CHECK-X86_32: ('iundefsym', 6) +// CHECK-X86_32: ('nundefsym', 3) +// CHECK-X86_32: ('tocoff', 0) +// CHECK-X86_32: ('ntoc', 0) +// CHECK-X86_32: ('modtaboff', 0) +// CHECK-X86_32: ('nmodtab', 0) +// CHECK-X86_32: ('extrefsymoff', 0) +// CHECK-X86_32: ('nextrefsyms', 0) +// CHECK-X86_32: ('indirectsymoff', 0) +// CHECK-X86_32: ('nindirectsyms', 0) +// CHECK-X86_32: ('extreloff', 0) +// CHECK-X86_32: ('nextrel', 0) +// CHECK-X86_32: ('locreloff', 0) +// CHECK-X86_32: ('nlocrel', 0) +// CHECK-X86_32: ('_indirect_symbols', [ +// CHECK-X86_32: ]) +// CHECK-X86_32: ), +// CHECK-X86_32: ]) + +// CHECK-X86_64: ('cputype', 16777223) +// CHECK-X86_64: ('cpusubtype', 3) +// CHECK-X86_64: ('filetype', 1) +// CHECK-X86_64: ('num_load_commands', 1) +// CHECK-X86_64: ('load_commands_size', 256) +// CHECK-X86_64: ('flag', 0) +// CHECK-X86_64: ('reserved', 0) +// CHECK-X86_64: ('load_commands', [ +// CHECK-X86_64: # Load Command 0 +// CHECK-X86_64: (('command', 25) +// CHECK-X86_64: ('size', 152) +// CHECK-X86_64: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('vm_addr', 0) +// CHECK-X86_64: ('vm_size', 4) +// CHECK-X86_64: ('file_offset', 288) +// CHECK-X86_64: ('file_size', 4) +// CHECK-X86_64: ('maxprot', 7) +// CHECK-X86_64: ('initprot', 7) +// CHECK-X86_64: ('num_sections', 1) +// CHECK-X86_64: ('flags', 0) +// CHECK-X86_64: ('sections', [ +// CHECK-X86_64: # Section 0 +// CHECK-X86_64: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('address', 0) +// CHECK-X86_64: ('size', 4) +// CHECK-X86_64: ('offset', 288) +// CHECK-X86_64: ('alignment', 0) +// CHECK-X86_64: ('reloc_offset', 0) +// CHECK-X86_64: ('num_reloc', 0) +// CHECK-X86_64: ('flags', 0x80000000) +// CHECK-X86_64: ('reserved1', 0) +// CHECK-X86_64: ('reserved2', 0) +// CHECK-X86_64: ('reserved3', 0) +// CHECK-X86_64: ), +// CHECK-X86_64: ('_relocations', [ +// CHECK-X86_64: ]) +// CHECK-X86_64: ]) +// CHECK-X86_64: ), +// CHECK-X86_64: # Load Command 1 +// CHECK-X86_64: (('command', 2) +// CHECK-X86_64: ('size', 24) +// CHECK-X86_64: ('symoff', 292) +// CHECK-X86_64: ('nsyms', 9) +// CHECK-X86_64: ('stroff', 436) +// CHECK-X86_64: ('strsize', 140) +// CHECK-X86_64: ('_string_data', '\x00sym_globl_def_B\x00sym_globl_undef_B\x00sym_globl_def_A\x00sym_globl_undef_A\x00sym_globl_def_C\x00sym_globl_undef_C\x00sym_local_B\x00sym_local_A\x00sym_local_C\x00\x00') +// CHECK-X86_64: ('_symbols', [ +// CHECK-X86_64: # Symbol 0 +// CHECK-X86_64: (('n_strx', 103) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_local_B') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 1 +// CHECK-X86_64: (('n_strx', 115) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_local_A') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 2 +// CHECK-X86_64: (('n_strx', 127) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_local_C') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 3 +// CHECK-X86_64: (('n_strx', 35) +// CHECK-X86_64: ('n_type', 0xf) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_globl_def_A') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 4 +// CHECK-X86_64: (('n_strx', 1) +// CHECK-X86_64: ('n_type', 0xf) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_globl_def_B') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 5 +// CHECK-X86_64: (('n_strx', 69) +// CHECK-X86_64: ('n_type', 0xf) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_globl_def_C') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 6 +// CHECK-X86_64: (('n_strx', 51) +// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_sect', 0) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_globl_undef_A') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 7 +// CHECK-X86_64: (('n_strx', 17) +// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_sect', 0) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_globl_undef_B') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 8 +// CHECK-X86_64: (('n_strx', 85) +// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_sect', 0) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'sym_globl_undef_C') +// CHECK-X86_64: ), +// CHECK-X86_64: ]) +// CHECK-X86_64: ), +// CHECK-X86_64: # Load Command 2 +// CHECK-X86_64: (('command', 11) +// CHECK-X86_64: ('size', 80) +// CHECK-X86_64: ('ilocalsym', 0) +// CHECK-X86_64: ('nlocalsym', 3) +// CHECK-X86_64: ('iextdefsym', 3) +// CHECK-X86_64: ('nextdefsym', 3) +// CHECK-X86_64: ('iundefsym', 6) +// CHECK-X86_64: ('nundefsym', 3) +// CHECK-X86_64: ('tocoff', 0) +// CHECK-X86_64: ('ntoc', 0) +// CHECK-X86_64: ('modtaboff', 0) +// CHECK-X86_64: ('nmodtab', 0) +// CHECK-X86_64: ('extrefsymoff', 0) +// CHECK-X86_64: ('nextrefsyms', 0) +// CHECK-X86_64: ('indirectsymoff', 0) +// CHECK-X86_64: ('nindirectsyms', 0) +// CHECK-X86_64: ('extreloff', 0) +// CHECK-X86_64: ('nextrel', 0) +// CHECK-X86_64: ('locreloff', 0) +// CHECK-X86_64: ('nlocrel', 0) +// CHECK-X86_64: ('_indirect_symbols', [ +// CHECK-X86_64: ]) +// CHECK-X86_64: ), +// CHECK-X86_64: ]) diff --git a/test/MC/MachO/Darwin/optimal_nop.s b/test/MC/MachO/x86_32-optimal_nop.s index 29cb073..d21d143 100644 --- a/test/MC/MachO/Darwin/optimal_nop.s +++ b/test/MC/MachO/x86_32-optimal_nop.s @@ -1,9 +1,4 @@ -// Validate that we can assemble this file exactly like the platform -// assembler. -// -// RUN: llvm-mc -filetype=obj -triple i386-apple-darwin10 -o %t.mc.o %s -// RUN: as -arch i386 -o %t.as.o %s -// RUN: diff %t.mc.o %t.as.o +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s # 1 byte nop test .align 4, 0 # start with 16 byte alignment filled with zeros @@ -154,3 +149,43 @@ # 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 .align 4, 0x90 ret + +// CHECK: ('cputype', 7) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 124) +// CHECK: ('flag', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 1) +// CHECK: ('size', 124) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 337) +// CHECK: ('file_offset', 152) +// CHECK: ('file_size', 337) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 1) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 337) +// CHECK: ('offset', 152) +// CHECK: ('alignment', 4) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ('_section_data', '\xc3\x90\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3f\x90\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\x0f\x1f@\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3\xc3\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3f\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3f\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\x0f\x1fD\x00\x00f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3f\x0f\x1fD\x00\x00f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3f\x0f\x1fD\x00\x00\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\x0f\x1f\x80\x00\x00\x00\x00\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x80\x00\x00\x00\x00\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3') +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/sections.s b/test/MC/MachO/x86_32-sections.s index a7bcd21..66ada28 100644 --- a/test/MC/MachO/sections.s +++ b/test/MC/MachO/x86_32-sections.s @@ -36,13 +36,9 @@ .objc_class_vars .objc_instance_vars .objc_module_info - -// FIXME: These are aliases for __TEXT, __cstring which we don't properly unique -// yet. -// .objc_class_names -// .objc_meth_var_types -// .objc_meth_var_names - + .objc_class_names + .objc_meth_var_types + .objc_meth_var_names .objc_selector_strs .section __TEXT,__picsymbolstub4,symbol_stubs,none,16 diff --git a/test/MC/MachO/x86_32-symbols.s b/test/MC/MachO/x86_32-symbols.s new file mode 100644 index 0000000..629ba7d --- /dev/null +++ b/test/MC/MachO/x86_32-symbols.s @@ -0,0 +1,1041 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s + + .text +L0: +D0: + .section __TEXT,__text,regular,pure_instructions +L1: +D1: + .const +L2: +D2: + .static_const +L3: +D3: + .cstring +L4: +D4: + .literal4 +L5: +D5: + .literal8 +L6: +D6: + .literal16 +L7: +D7: + .constructor +L8: +D8: + .destructor +L9: +D9: + .symbol_stub +L10: +D10: + .picsymbol_stub +L11: +D11: + .data +L12: +D12: + .static_data +L13: +D13: + .non_lazy_symbol_pointer +L14: +D14: + .lazy_symbol_pointer +L15: +D15: + .dyld +L16: +D16: + .mod_init_func +L17: +D17: + .mod_term_func +L18: +D18: + .const_data +L19: +D19: + .objc_class +L20: +D20: + .objc_meta_class +L21: +D21: + .objc_cat_cls_meth +L22: +D22: + .objc_cat_inst_meth +L23: +D23: + .objc_protocol +L24: +D24: + .objc_string_object +L25: +D25: + .objc_cls_meth +L26: +D26: + .objc_inst_meth +L27: +D27: + .objc_cls_refs +L28: +D28: + .objc_message_refs +L29: +D29: + .objc_symbols +L30: +D30: + .objc_category +L31: +D31: + .objc_class_vars +L32: +D32: + .objc_instance_vars +L33: +D33: + .objc_module_info +L34: +D34: + .objc_class_names +L35: +D35: + .objc_meth_var_types +L36: +D36: + .objc_meth_var_names +L37: +D37: + .objc_selector_strs +L38: +D38: + .section __TEXT,__picsymbolstub4,symbol_stubs,none,16 +L39: +D39: + +// CHECK: ('cputype', 7) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 2608) +// CHECK: ('flag', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 1) +// CHECK: ('size', 2504) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 0) +// CHECK: ('file_offset', 2636) +// CHECK: ('file_size', 0) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 36) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 1 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 2 +// CHECK: (('section_name', '__static_const\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 3 +// CHECK: (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x2) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 4 +// CHECK: (('section_name', '__literal4\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x3) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 5 +// CHECK: (('section_name', '__literal8\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 3) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x4) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 6 +// CHECK: (('section_name', '__literal16\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 4) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0xe) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 7 +// CHECK: (('section_name', '__constructor\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 8 +// CHECK: (('section_name', '__destructor\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 9 +// CHECK: (('section_name', '__symbol_stub\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000008) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 16) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 10 +// CHECK: (('section_name', '__picsymbol_stub') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000008) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 26) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 11 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 12 +// CHECK: (('section_name', '__static_data\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 13 +// CHECK: (('section_name', '__nl_symbol_ptr\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x6) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 14 +// CHECK: (('section_name', '__la_symbol_ptr\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x7) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 15 +// CHECK: (('section_name', '__dyld\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 16 +// CHECK: (('section_name', '__mod_init_func\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x9) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 17 +// CHECK: (('section_name', '__mod_term_func\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0xa) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 18 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 19 +// CHECK: (('section_name', '__class\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 20 +// CHECK: (('section_name', '__meta_class\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 21 +// CHECK: (('section_name', '__cat_cls_meth\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 22 +// CHECK: (('section_name', '__cat_inst_meth\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 23 +// CHECK: (('section_name', '__protocol\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 24 +// CHECK: (('section_name', '__string_object\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 25 +// CHECK: (('section_name', '__cls_meth\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 26 +// CHECK: (('section_name', '__inst_meth\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 27 +// CHECK: (('section_name', '__cls_refs\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000005) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 28 +// CHECK: (('section_name', '__message_refs\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000005) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 29 +// CHECK: (('section_name', '__symbols\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 30 +// CHECK: (('section_name', '__category\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 31 +// CHECK: (('section_name', '__class_vars\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 32 +// CHECK: (('section_name', '__instance_vars\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 33 +// CHECK: (('section_name', '__module_info\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 34 +// CHECK: (('section_name', '__selector_strs\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x2) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 35 +// CHECK: (('section_name', '__picsymbolstub4') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2636) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x8) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 16) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 2636) +// CHECK: ('nsyms', 40) +// CHECK: ('stroff', 3116) +// CHECK: ('strsize', 152) +// CHECK: ('_string_data', '\x00D0\x00D1\x00D2\x00D3\x00D4\x00D5\x00D6\x00D7\x00D8\x00D9\x00D10\x00D11\x00D12\x00D13\x00D14\x00D15\x00D16\x00D17\x00D18\x00D19\x00D20\x00D21\x00D22\x00D23\x00D24\x00D25\x00D26\x00D27\x00D28\x00D29\x00D30\x00D31\x00D32\x00D33\x00D34\x00D35\x00D36\x00D37\x00D38\x00D39\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D0') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 4) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D1') +// CHECK: ), +// CHECK: # Symbol 2 +// CHECK: (('n_strx', 7) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D2') +// CHECK: ), +// CHECK: # Symbol 3 +// CHECK: (('n_strx', 10) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 3) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D3') +// CHECK: ), +// CHECK: # Symbol 4 +// CHECK: (('n_strx', 13) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D4') +// CHECK: ), +// CHECK: # Symbol 5 +// CHECK: (('n_strx', 16) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 5) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D5') +// CHECK: ), +// CHECK: # Symbol 6 +// CHECK: (('n_strx', 19) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 6) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D6') +// CHECK: ), +// CHECK: # Symbol 7 +// CHECK: (('n_strx', 22) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 7) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D7') +// CHECK: ), +// CHECK: # Symbol 8 +// CHECK: (('n_strx', 25) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 8) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D8') +// CHECK: ), +// CHECK: # Symbol 9 +// CHECK: (('n_strx', 28) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 9) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D9') +// CHECK: ), +// CHECK: # Symbol 10 +// CHECK: (('n_strx', 31) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 10) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D10') +// CHECK: ), +// CHECK: # Symbol 11 +// CHECK: (('n_strx', 35) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 11) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D11') +// CHECK: ), +// CHECK: # Symbol 12 +// CHECK: (('n_strx', 39) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 12) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D12') +// CHECK: ), +// CHECK: # Symbol 13 +// CHECK: (('n_strx', 43) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 13) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D13') +// CHECK: ), +// CHECK: # Symbol 14 +// CHECK: (('n_strx', 47) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 14) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D14') +// CHECK: ), +// CHECK: # Symbol 15 +// CHECK: (('n_strx', 51) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 15) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D15') +// CHECK: ), +// CHECK: # Symbol 16 +// CHECK: (('n_strx', 55) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 16) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D16') +// CHECK: ), +// CHECK: # Symbol 17 +// CHECK: (('n_strx', 59) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 17) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D17') +// CHECK: ), +// CHECK: # Symbol 18 +// CHECK: (('n_strx', 63) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 18) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D18') +// CHECK: ), +// CHECK: # Symbol 19 +// CHECK: (('n_strx', 67) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 19) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D19') +// CHECK: ), +// CHECK: # Symbol 20 +// CHECK: (('n_strx', 71) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 20) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D20') +// CHECK: ), +// CHECK: # Symbol 21 +// CHECK: (('n_strx', 75) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 21) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D21') +// CHECK: ), +// CHECK: # Symbol 22 +// CHECK: (('n_strx', 79) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 22) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D22') +// CHECK: ), +// CHECK: # Symbol 23 +// CHECK: (('n_strx', 83) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 23) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D23') +// CHECK: ), +// CHECK: # Symbol 24 +// CHECK: (('n_strx', 87) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 24) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D24') +// CHECK: ), +// CHECK: # Symbol 25 +// CHECK: (('n_strx', 91) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 25) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D25') +// CHECK: ), +// CHECK: # Symbol 26 +// CHECK: (('n_strx', 95) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 26) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D26') +// CHECK: ), +// CHECK: # Symbol 27 +// CHECK: (('n_strx', 99) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 27) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D27') +// CHECK: ), +// CHECK: # Symbol 28 +// CHECK: (('n_strx', 103) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 28) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D28') +// CHECK: ), +// CHECK: # Symbol 29 +// CHECK: (('n_strx', 107) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 29) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D29') +// CHECK: ), +// CHECK: # Symbol 30 +// CHECK: (('n_strx', 111) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 30) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D30') +// CHECK: ), +// CHECK: # Symbol 31 +// CHECK: (('n_strx', 115) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 31) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D31') +// CHECK: ), +// CHECK: # Symbol 32 +// CHECK: (('n_strx', 119) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 32) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D32') +// CHECK: ), +// CHECK: # Symbol 33 +// CHECK: (('n_strx', 123) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 33) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D33') +// CHECK: ), +// CHECK: # Symbol 34 +// CHECK: (('n_strx', 127) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 34) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D34') +// CHECK: ), +// CHECK: # Symbol 35 +// CHECK: (('n_strx', 131) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D35') +// CHECK: ), +// CHECK: # Symbol 36 +// CHECK: (('n_strx', 135) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D36') +// CHECK: ), +// CHECK: # Symbol 37 +// CHECK: (('n_strx', 139) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D37') +// CHECK: ), +// CHECK: # Symbol 38 +// CHECK: (('n_strx', 143) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 35) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D38') +// CHECK: ), +// CHECK: # Symbol 39 +// CHECK: (('n_strx', 147) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 36) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D39') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 40) +// CHECK: ('iextdefsym', 40) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 40) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/x86_64-sections.s b/test/MC/MachO/x86_64-sections.s new file mode 100644 index 0000000..8efd35e --- /dev/null +++ b/test/MC/MachO/x86_64-sections.s @@ -0,0 +1,561 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o - | macho-dump | FileCheck %s + + .text + .section __TEXT,__text,regular,pure_instructions + + .const + .static_const + .cstring + .literal4 + .literal8 + .literal16 + .constructor + .destructor + .data + .static_data + .dyld + .mod_init_func + .mod_term_func + .const_data + .objc_class + .objc_meta_class + .objc_cat_cls_meth + .objc_cat_inst_meth + .objc_protocol + .objc_string_object + .objc_cls_meth + .objc_inst_meth + .objc_cls_refs + .objc_message_refs + .objc_symbols + .objc_category + .objc_class_vars + .objc_instance_vars + .objc_module_info + .objc_class_names + .objc_meth_var_types + .objc_meth_var_names + .objc_selector_strs + + .subsections_via_symbols + +// CHECK: ('cputype', 16777223) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 2552) +// CHECK: ('flag', 8192) +// CHECK: ('reserved', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 25) +// CHECK: ('size', 2552) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 0) +// CHECK: ('file_offset', 2584) +// CHECK: ('file_size', 0) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 31) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 1 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 2 +// CHECK: (('section_name', '__static_const\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 3 +// CHECK: (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x2) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 4 +// CHECK: (('section_name', '__literal4\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x3) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 5 +// CHECK: (('section_name', '__literal8\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 3) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x4) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 6 +// CHECK: (('section_name', '__literal16\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 4) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0xe) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 7 +// CHECK: (('section_name', '__constructor\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 8 +// CHECK: (('section_name', '__destructor\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 9 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 10 +// CHECK: (('section_name', '__static_data\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 11 +// CHECK: (('section_name', '__dyld\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 12 +// CHECK: (('section_name', '__mod_init_func\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x9) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 13 +// CHECK: (('section_name', '__mod_term_func\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0xa) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 14 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 15 +// CHECK: (('section_name', '__class\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 16 +// CHECK: (('section_name', '__meta_class\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 17 +// CHECK: (('section_name', '__cat_cls_meth\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 18 +// CHECK: (('section_name', '__cat_inst_meth\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 19 +// CHECK: (('section_name', '__protocol\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 20 +// CHECK: (('section_name', '__string_object\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 21 +// CHECK: (('section_name', '__cls_meth\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 22 +// CHECK: (('section_name', '__inst_meth\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 23 +// CHECK: (('section_name', '__cls_refs\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000005) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 24 +// CHECK: (('section_name', '__message_refs\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000005) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 25 +// CHECK: (('section_name', '__symbols\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 26 +// CHECK: (('section_name', '__category\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 27 +// CHECK: (('section_name', '__class_vars\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 28 +// CHECK: (('section_name', '__instance_vars\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 29 +// CHECK: (('section_name', '__module_info\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 30 +// CHECK: (('section_name', '__selector_strs\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2584) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x2) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/x86_64-symbols.s b/test/MC/MachO/x86_64-symbols.s new file mode 100644 index 0000000..c5c39a6 --- /dev/null +++ b/test/MC/MachO/x86_64-symbols.s @@ -0,0 +1,998 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o - | macho-dump | FileCheck %s + + .text +L0: +D0: + .section __TEXT,__text,regular,pure_instructions +L1: +D1: + .const +L2: +D2: + .static_const +L3: +D3: + .cstring +L4: +D4: + .literal4 +L5: +D5: + .literal8 +L6: +D6: + .literal16 +L7: +D7: + .constructor +L8: +D8: + .destructor +L9: +D9: +// .symbol_stub +//L10: +//D10: +// .picsymbol_stub +//L11: +//D11: + .data +L12: +D12: + .static_data +L13: +D13: +// .non_lazy_symbol_pointer +//L14: +//D14: +// .lazy_symbol_pointer +//L15: +//D15: + .dyld +L16: +D16: + .mod_init_func +L17: +D17: + .mod_term_func +L18: +D18: + .const_data +L19: +D19: + .objc_class +L20: +D20: + .objc_meta_class +L21: +D21: + .objc_cat_cls_meth +L22: +D22: + .objc_cat_inst_meth +L23: +D23: + .objc_protocol +L24: +D24: + .objc_string_object +L25: +D25: + .objc_cls_meth +L26: +D26: + .objc_inst_meth +L27: +D27: + .objc_cls_refs +L28: +D28: + .objc_message_refs +L29: +D29: + .objc_symbols +L30: +D30: + .objc_category +L31: +D31: + .objc_class_vars +L32: +D32: + .objc_instance_vars +L33: +D33: + .objc_module_info +L34: +D34: + .objc_class_names +L35: +D35: + .objc_meth_var_types +L36: +D36: + .objc_meth_var_names +L37: +D37: + .objc_selector_strs +L38: +D38: +// .section __TEXT,__picsymbolstub4,symbol_stubs,none,16 +//L39: +//D39: + +// CHECK: ('cputype', 16777223) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 2656) +// CHECK: ('flag', 0) +// CHECK: ('reserved', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 25) +// CHECK: ('size', 2552) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 0) +// CHECK: ('file_offset', 2688) +// CHECK: ('file_size', 0) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 31) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 1 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 2 +// CHECK: (('section_name', '__static_const\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 3 +// CHECK: (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x2) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 4 +// CHECK: (('section_name', '__literal4\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x3) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 5 +// CHECK: (('section_name', '__literal8\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 3) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x4) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 6 +// CHECK: (('section_name', '__literal16\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 4) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0xe) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 7 +// CHECK: (('section_name', '__constructor\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 8 +// CHECK: (('section_name', '__destructor\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 9 +// CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 10 +// CHECK: (('section_name', '__static_data\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 11 +// CHECK: (('section_name', '__dyld\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 12 +// CHECK: (('section_name', '__mod_init_func\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x9) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 13 +// CHECK: (('section_name', '__mod_term_func\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0xa) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 14 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 15 +// CHECK: (('section_name', '__class\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 16 +// CHECK: (('section_name', '__meta_class\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 17 +// CHECK: (('section_name', '__cat_cls_meth\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 18 +// CHECK: (('section_name', '__cat_inst_meth\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 19 +// CHECK: (('section_name', '__protocol\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 20 +// CHECK: (('section_name', '__string_object\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 21 +// CHECK: (('section_name', '__cls_meth\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 22 +// CHECK: (('section_name', '__inst_meth\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 23 +// CHECK: (('section_name', '__cls_refs\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000005) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 24 +// CHECK: (('section_name', '__message_refs\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 2) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000005) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 25 +// CHECK: (('section_name', '__symbols\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 26 +// CHECK: (('section_name', '__category\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 27 +// CHECK: (('section_name', '__class_vars\x00\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 28 +// CHECK: (('section_name', '__instance_vars\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 29 +// CHECK: (('section_name', '__module_info\x00\x00\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x10000000) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: # Section 30 +// CHECK: (('section_name', '__selector_strs\x00') +// CHECK: ('segment_name', '__OBJC\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 0) +// CHECK: ('offset', 2688) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x2) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ('reserved3', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 2688) +// CHECK: ('nsyms', 40) +// CHECK: ('stroff', 3328) +// CHECK: ('strsize', 152) +// CHECK: ('_string_data', '\x00D0\x00D1\x00D2\x00D3\x00L4\x00D4\x00D5\x00D6\x00D7\x00D8\x00D9\x00D12\x00D13\x00D16\x00D17\x00D18\x00D19\x00D20\x00D21\x00D22\x00D23\x00D24\x00D25\x00D26\x00D27\x00D28\x00D29\x00D30\x00D31\x00D32\x00D33\x00D34\x00L35\x00D35\x00L36\x00D36\x00L37\x00D37\x00L38\x00D38\x00\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D0') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 4) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D1') +// CHECK: ), +// CHECK: # Symbol 2 +// CHECK: (('n_strx', 7) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D2') +// CHECK: ), +// CHECK: # Symbol 3 +// CHECK: (('n_strx', 10) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 3) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D3') +// CHECK: ), +// CHECK: # Symbol 4 +// CHECK: (('n_strx', 13) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'L4') +// CHECK: ), +// CHECK: # Symbol 5 +// CHECK: (('n_strx', 16) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D4') +// CHECK: ), +// CHECK: # Symbol 6 +// CHECK: (('n_strx', 19) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 5) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D5') +// CHECK: ), +// CHECK: # Symbol 7 +// CHECK: (('n_strx', 22) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 6) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D6') +// CHECK: ), +// CHECK: # Symbol 8 +// CHECK: (('n_strx', 25) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 7) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D7') +// CHECK: ), +// CHECK: # Symbol 9 +// CHECK: (('n_strx', 28) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 8) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D8') +// CHECK: ), +// CHECK: # Symbol 10 +// CHECK: (('n_strx', 31) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 9) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D9') +// CHECK: ), +// CHECK: # Symbol 11 +// CHECK: (('n_strx', 34) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 10) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D12') +// CHECK: ), +// CHECK: # Symbol 12 +// CHECK: (('n_strx', 38) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 11) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D13') +// CHECK: ), +// CHECK: # Symbol 13 +// CHECK: (('n_strx', 42) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 12) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D16') +// CHECK: ), +// CHECK: # Symbol 14 +// CHECK: (('n_strx', 46) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 13) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D17') +// CHECK: ), +// CHECK: # Symbol 15 +// CHECK: (('n_strx', 50) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 14) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D18') +// CHECK: ), +// CHECK: # Symbol 16 +// CHECK: (('n_strx', 54) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 15) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D19') +// CHECK: ), +// CHECK: # Symbol 17 +// CHECK: (('n_strx', 58) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 16) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D20') +// CHECK: ), +// CHECK: # Symbol 18 +// CHECK: (('n_strx', 62) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 17) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D21') +// CHECK: ), +// CHECK: # Symbol 19 +// CHECK: (('n_strx', 66) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 18) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D22') +// CHECK: ), +// CHECK: # Symbol 20 +// CHECK: (('n_strx', 70) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 19) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D23') +// CHECK: ), +// CHECK: # Symbol 21 +// CHECK: (('n_strx', 74) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 20) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D24') +// CHECK: ), +// CHECK: # Symbol 22 +// CHECK: (('n_strx', 78) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 21) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D25') +// CHECK: ), +// CHECK: # Symbol 23 +// CHECK: (('n_strx', 82) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 22) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D26') +// CHECK: ), +// CHECK: # Symbol 24 +// CHECK: (('n_strx', 86) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 23) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D27') +// CHECK: ), +// CHECK: # Symbol 25 +// CHECK: (('n_strx', 90) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 24) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D28') +// CHECK: ), +// CHECK: # Symbol 26 +// CHECK: (('n_strx', 94) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 25) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D29') +// CHECK: ), +// CHECK: # Symbol 27 +// CHECK: (('n_strx', 98) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 26) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D30') +// CHECK: ), +// CHECK: # Symbol 28 +// CHECK: (('n_strx', 102) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 27) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D31') +// CHECK: ), +// CHECK: # Symbol 29 +// CHECK: (('n_strx', 106) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 28) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D32') +// CHECK: ), +// CHECK: # Symbol 30 +// CHECK: (('n_strx', 110) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 29) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D33') +// CHECK: ), +// CHECK: # Symbol 31 +// CHECK: (('n_strx', 114) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 30) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D34') +// CHECK: ), +// CHECK: # Symbol 32 +// CHECK: (('n_strx', 118) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'L35') +// CHECK: ), +// CHECK: # Symbol 33 +// CHECK: (('n_strx', 122) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D35') +// CHECK: ), +// CHECK: # Symbol 34 +// CHECK: (('n_strx', 126) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'L36') +// CHECK: ), +// CHECK: # Symbol 35 +// CHECK: (('n_strx', 130) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D36') +// CHECK: ), +// CHECK: # Symbol 36 +// CHECK: (('n_strx', 134) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'L37') +// CHECK: ), +// CHECK: # Symbol 37 +// CHECK: (('n_strx', 138) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 4) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D37') +// CHECK: ), +// CHECK: # Symbol 38 +// CHECK: (('n_strx', 142) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 31) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'L38') +// CHECK: ), +// CHECK: # Symbol 39 +// CHECK: (('n_strx', 146) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 31) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'D38') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 40) +// CHECK: ('iextdefsym', 40) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 40) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/MC/MachO/zerofill-4.s b/test/MC/MachO/zerofill-4.s new file mode 100644 index 0000000..d9c987c --- /dev/null +++ b/test/MC/MachO/zerofill-4.s @@ -0,0 +1,35 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s + +.zerofill __DATA,__bss,_fill0,1,0 +.zerofill __DATA,__bss,_a,4,2 +.zerofill __DATA,__bss,_fill1,1,0 +.zerofill __DATA,__bss,_b,4,3 +.zerofill __DATA,__bss,_fill2,1,0 +.zerofill __DATA,__bss,_c,4,4 +.zerofill __DATA,__bss,_fill3,1,0 +.zerofill __DATA,__bss,_d,4,5 + +// CHECK: # Symbol 0 +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_fill0') +// CHECK: # Symbol 1 +// CHECK: ('n_value', 4) +// CHECK: ('_string', '_a') +// CHECK: # Symbol 2 +// CHECK: ('n_value', 8) +// CHECK: ('_string', '_fill1') +// CHECK: # Symbol 3 +// CHECK: ('n_value', 16) +// CHECK: ('_string', '_b') +// CHECK: # Symbol 4 +// CHECK: ('n_value', 20) +// CHECK: ('_string', '_fill2') +// CHECK: # Symbol 5 +// CHECK: ('n_value', 32) +// CHECK: ('_string', '_c') +// CHECK: # Symbol 6 +// CHECK: ('n_value', 36) +// CHECK: ('_string', '_fill3') +// CHECK: # Symbol 7 +// CHECK: ('n_value', 64) +// CHECK: ('_string', '_d') diff --git a/test/MC/MachO/zerofill-sect-align.s b/test/MC/MachO/zerofill-sect-align.s new file mode 100644 index 0000000..5d7730f --- /dev/null +++ b/test/MC/MachO/zerofill-sect-align.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s +// +// Check that the section itself is aligned. + + .byte 0 + +.zerofill __DATA,__bss,_a,1,0 +.zerofill __DATA,__bss,_b,4,4 + +// CHECK: # Symbol 0 +// CHECK: ('n_value', 16) +// CHECK: ('_string', '_a') +// CHECK: # Symbol 1 +// CHECK: ('n_value', 32) +// CHECK: ('_string', '_b') diff --git a/test/Other/constant-fold-gep.ll b/test/Other/constant-fold-gep.ll index 5358e1f..ecef9c4 100644 --- a/test/Other/constant-fold-gep.ll +++ b/test/Other/constant-fold-gep.ll @@ -21,10 +21,12 @@ ; PLAIN: %1 = type { double, float, double, double } ; PLAIN: %2 = type { i1, i1* } ; PLAIN: %3 = type { i64, i64 } +; PLAIN: %4 = type { i32, i32 } ; OPT: %0 = type { i1, double } ; OPT: %1 = type { double, float, double, double } ; OPT: %2 = type { i1, i1* } ; OPT: %3 = type { i64, i64 } +; OPT: %4 = type { i32, i32 } ; The automatic constant folder in opt does not have targetdata access, so ; it can't fold gep arithmetic, in general. However, the constant folder run @@ -118,9 +120,19 @@ ; TO: @N = constant i64* inttoptr (i64 8 to i64*) ; TO: @O = constant i64* inttoptr (i64 8 to i64*) -@M = constant i64* getelementptr (i64 *null, i32 1) -@N = constant i64* getelementptr ({ i64, i64 } *null, i32 0, i32 1) -@O = constant i64* getelementptr ([2 x i64] *null, i32 0, i32 1) +@M = constant i64* getelementptr (i64* null, i32 1) +@N = constant i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) +@O = constant i64* getelementptr ([2 x i64]* null, i32 0, i32 1) + +; Fold GEP of a GEP. Theoretically some of these cases could be folded +; without using targetdata, however that's not implemented yet. + +; PLAIN: @Z = global i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x %4]* @ext, i64 0, i64 1, i32 0), i64 1) +; OPT: @Z = global i32* getelementptr (i32* getelementptr inbounds ([3 x %4]* @ext, i64 0, i64 1, i32 0), i64 1) +; TO: @Z = global i32* getelementptr inbounds ([3 x %0]* @ext, i64 0, i64 1, i32 1) + +@ext = external global [3 x { i32, i32 }] +@Z = global i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) ; Duplicate all of the above as function return values rather than ; global initializers. @@ -457,14 +469,33 @@ define i64 @fk() nounwind { ; SCEV: --> sizeof(i64) define i64* @fM() nounwind { - %t = bitcast i64* getelementptr (i64 *null, i32 1) to i64* + %t = bitcast i64* getelementptr (i64* null, i32 1) to i64* ret i64* %t } define i64* @fN() nounwind { - %t = bitcast i64* getelementptr ({ i64, i64 } *null, i32 0, i32 1) to i64* + %t = bitcast i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) to i64* ret i64* %t } define i64* @fO() nounwind { - %t = bitcast i64* getelementptr ([2 x i64] *null, i32 0, i32 1) to i64* + %t = bitcast i64* getelementptr ([2 x i64]* null, i32 0, i32 1) to i64* ret i64* %t } + +; PLAIN: define i32* @fZ() nounwind { +; PLAIN: %t = bitcast i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x %4]* @ext, i64 0, i64 1, i32 0), i64 1) to i32* +; PLAIN: ret i32* %t +; PLAIN: } +; OPT: define i32* @fZ() nounwind { +; OPT: ret i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x %4]* @ext, i64 0, i64 1, i32 0), i64 1) +; OPT: } +; TO: define i32* @fZ() nounwind { +; TO: ret i32* getelementptr inbounds ([3 x %0]* @ext, i64 0, i64 1, i32 1) +; TO: } +; SCEV: Classifying expressions for: @fZ +; SCEV: %t = bitcast i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x %4]* @ext, i64 0, i64 1, i32 0), i64 1) to i32* +; SCEV: --> ((3 * sizeof(i32)) + @ext) + +define i32* @fZ() nounwind { + %t = bitcast i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32* + ret i32* %t +} diff --git a/test/Other/lint.ll b/test/Other/lint.ll new file mode 100644 index 0000000..8658495 --- /dev/null +++ b/test/Other/lint.ll @@ -0,0 +1,66 @@ +; RUN: opt -lint -disable-output < %s |& FileCheck %s +target datalayout = "e-p:64:64:64" + +declare fastcc void @bar() + +define i32 @foo() noreturn { +; CHECK: Caller and callee calling convention differ + call void @bar() +; CHECK: Null pointer dereference + store i32 0, i32* null +; CHECK: Null pointer dereference + %t = load i32* null +; CHECK: Undef pointer dereference + store i32 0, i32* undef +; CHECK: Undef pointer dereference + %u = load i32* undef +; CHECK: Memory reference address is misaligned + %x = inttoptr i32 1 to i32* + load i32* %x, align 4 +; CHECK: Division by zero + %sd = sdiv i32 2, 0 +; CHECK: Division by zero + %ud = udiv i32 2, 0 +; CHECK: Division by zero + %sr = srem i32 2, 0 +; CHECK: Division by zero + %ur = urem i32 2, 0 +; CHECK: extractelement index out of range + %ee = extractelement <4 x i32> zeroinitializer, i32 4 +; CHECK: insertelement index out of range + %ie = insertelement <4 x i32> zeroinitializer, i32 0, i32 4 +; CHECK: Shift count out of range + %r = lshr i32 0, 32 +; CHECK: Shift count out of range + %q = ashr i32 0, 32 +; CHECK: Shift count out of range + %l = shl i32 0, 32 +; CHECK: xor(undef, undef) + %xx = xor i32 undef, undef +; CHECK: sub(undef, undef) + %xs = sub i32 undef, undef + br label %next + +next: +; CHECK: Static alloca outside of entry block + %a = alloca i32 +; CHECK: Return statement in function with noreturn attribute + ret i32 0 + +foo: + %z = add i32 0, 0 +; CHECK: unreachable immediately preceded by instruction without side effects + unreachable +} + +; CHECK: Unnamed function with non-local linkage +define void @0() nounwind { + ret void +} + +; CHECK: va_start called in a non-varargs function +declare void @llvm.va_start(i8*) +define void @not_vararg(i8* %p) nounwind { + call void @llvm.va_start(i8* %p) + ret void +} diff --git a/test/Scripts/macho-dump b/test/Scripts/macho-dump index 5b9943a..72f8339 100755 --- a/test/Scripts/macho-dump +++ b/test/Scripts/macho-dump @@ -12,12 +12,10 @@ class Reader: else: self.file = open(path,'rb') self.isLSB = None + self.is64Bit = None self.string_table = None - def setLSB(self, isLSB): - self.isLSB = bool(isLSB) - def tell(self): return self.file.tell() @@ -42,6 +40,9 @@ class Reader: Value = struct.unpack('><'[self.isLSB] + 'I', self.read(4))[0] return int(Value) + def read64(self): + return struct.unpack('><'[self.isLSB] + 'Q', self.read(8))[0] + def registerStringTable(self, strings): if self.string_table is not None: raise ValueError,"%s: warning: multiple string tables" % sys.argv[0] @@ -60,9 +61,13 @@ def dumpmacho(path, opts): magic = f.read(4) if magic == '\xFE\xED\xFA\xCE': - f.setLSB(False) + f.isLSB, f.is64Bit = False, False elif magic == '\xCE\xFA\xED\xFE': - f.setLSB(True) + f.isLSB, f.is64Bit = True, False + elif magic == '\xFE\xED\xFA\xCF': + f.isLSB, f.is64Bit = False, True + elif magic == '\xCF\xFA\xED\xFE': + f.isLSB, f.is64Bit = True, True else: raise ValueError,"Not a Mach-O object file: %r (bad magic)" % path @@ -79,6 +84,9 @@ def dumpmacho(path, opts): print "('flag', %r)" % f.read32() + if f.is64Bit: + print "('reserved', %r)" % f.read32() + start = f.tell() print "('load_commands', [" @@ -87,7 +95,8 @@ def dumpmacho(path, opts): print "])" if f.tell() - start != loadCommandsSize: - raise ValueError,"%s: warning: invalid load commands size: %r" % (sys.argv[0], loadCommandsSize) + raise ValueError,"%s: warning: invalid load commands size: %r" % ( + sys.argv[0], loadCommandsSize) def dumpLoadCommand(f, i, opts): start = f.tell() @@ -99,28 +108,38 @@ def dumpLoadCommand(f, i, opts): print " ('size', %r)" % cmdSize if cmd == 1: - dumpSegmentLoadCommand32(f, opts) + dumpSegmentLoadCommand(f, opts, False) elif cmd == 2: dumpSymtabCommand(f, opts) elif cmd == 11: dumpDysymtabCommand(f, opts) + elif cmd == 25: + dumpSegmentLoadCommand(f, opts, True) elif cmd == 27: import uuid print " ('uuid', %s)" % uuid.UUID(bytes=f.read(16)) else: - print >>sys.stderr,"%s: warning: unknown load command: %r" % (sys.argv[0], cmd) + print >>sys.stderr,"%s: warning: unknown load command: %r" % ( + sys.argv[0], cmd) f.read(cmdSize - 8) print " )," if f.tell() - start != cmdSize: - raise ValueError,"%s: warning: invalid load command size: %r" % (sys.argv[0], cmdSize) + raise ValueError,"%s: warning: invalid load command size: %r" % ( + sys.argv[0], cmdSize) -def dumpSegmentLoadCommand32(f, opts): +def dumpSegmentLoadCommand(f, opts, is64Bit): print " ('segment_name', %r)" % f.read(16) - print " ('vm_addr', %r)" % f.read32() - print " ('vm_size', %r)" % f.read32() - print " ('file_offset', %r)" % f.read32() - print " ('file_size', %r)" % f.read32() + if is64Bit: + print " ('vm_addr', %r)" % f.read64() + print " ('vm_size', %r)" % f.read64() + print " ('file_offset', %r)" % f.read64() + print " ('file_size', %r)" % f.read64() + else: + print " ('vm_addr', %r)" % f.read32() + print " ('vm_size', %r)" % f.read32() + print " ('file_offset', %r)" % f.read32() + print " ('file_size', %r)" % f.read32() print " ('maxprot', %r)" % f.read32() print " ('initprot', %r)" % f.read32() numSections = f.read32() @@ -129,7 +148,7 @@ def dumpSegmentLoadCommand32(f, opts): print " ('sections', [" for i in range(numSections): - dumpSection32(f, i, opts) + dumpSection(f, i, opts, is64Bit) print " ])" def dumpSymtabCommand(f, opts): @@ -168,8 +187,12 @@ def dumpNlist32(f, i, opts): print " ('n_sect', %r)" % n_sect n_desc = f.read16() print " ('n_desc', %r)" % n_desc - n_value = f.read32() - print " ('n_value', %r)" % n_value + if f.is64Bit: + n_value = f.read64() + print " ('n_value', %r)" % n_value + else: + n_value = f.read32() + print " ('n_value', %r)" % n_value print " ('_string', %r)" % f.getString(n_strx) print " )," @@ -206,13 +229,18 @@ def dumpDysymtabCommand(f, opts): f.seek(prev_pos) -def dumpSection32(f, i, opts): +def dumpSection(f, i, opts, is64Bit): print " # Section %r" % i print " (('section_name', %r)" % f.read(16) print " ('segment_name', %r)" % f.read(16) - print " ('address', %r)" % f.read32() - size = f.read32() - print " ('size', %r)" % size + if is64Bit: + print " ('address', %r)" % f.read64() + size = f.read64() + print " ('size', %r)" % size + else: + print " ('address', %r)" % f.read32() + size = f.read32() + print " ('size', %r)" % size offset = f.read32() print " ('offset', %r)" % offset print " ('alignment', %r)" % f.read32() @@ -223,6 +251,8 @@ def dumpSection32(f, i, opts): print " ('flags', %#x)" % f.read32() print " ('reserved1', %r)" % f.read32() print " ('reserved2', %r)" % f.read32() + if is64Bit: + print " ('reserved3', %r)" % f.read32() print " )," prev_pos = f.tell() diff --git a/test/TableGen/2003-08-03-PassCode.td b/test/TableGen/2003-08-03-PassCode.td index 7142186..c02f499 100644 --- a/test/TableGen/2003-08-03-PassCode.td +++ b/test/TableGen/2003-08-03-PassCode.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak class test<code C> { code Code = C; diff --git a/test/TableGen/2006-09-18-LargeInt.td b/test/TableGen/2006-09-18-LargeInt.td index afd813f..194699a 100644 --- a/test/TableGen/2006-09-18-LargeInt.td +++ b/test/TableGen/2006-09-18-LargeInt.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep -- 4294901760 +// XFAIL: vg_leak def X { int Y = 0xFFFF0000; diff --git a/test/TableGen/2010-03-24-PrematureDefaults.td b/test/TableGen/2010-03-24-PrematureDefaults.td new file mode 100644 index 0000000..2ff2d42 --- /dev/null +++ b/test/TableGen/2010-03-24-PrematureDefaults.td @@ -0,0 +1,44 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak + +class A<int k, bits<2> x = 1> { + int K = k; + bits<2> Bits = x; +} + +// CHECK: def a1 +// CHECK: Bits = { 0, 1 } +def a1 : A<12>; + +// CHECK: def a2 +// CHECK: Bits = { 1, 0 } +def a2 : A<13, 2>; + +// Here was the bug: X.Bits would get resolved to the default a1.Bits while +// resolving the first template argument. When the second template argument +// was processed, X would be set correctly, but Bits retained the default +// value. +class B<int k, A x = a1> { + A X = x; + bits<2> Bits = X.Bits; +} + +// CHECK: def b1 +// CHECK: Bits = { 0, 1 } +def b1 : B<27>; + +// CHECK: def b2 +// CHECK: Bits = { 1, 0 } +def b2 : B<28, a2>; + +class C<A x = a1> { + bits<2> Bits = x.Bits; +} + +// CHECK: def c1 +// CHECK: Bits = { 0, 1 } +def c1 : C; + +// CHECK: def c2 +// CHECK: Bits = { 1, 0 } +def c2 : C<a2>; diff --git a/test/TableGen/AnonDefinitionOnDemand.td b/test/TableGen/AnonDefinitionOnDemand.td index d567fc8..b10ad58 100644 --- a/test/TableGen/AnonDefinitionOnDemand.td +++ b/test/TableGen/AnonDefinitionOnDemand.td @@ -1,4 +1,5 @@ // RUN: tblgen < %s +// XFAIL: vg_leak class foo<int X> { int THEVAL = X; } def foo_imp : foo<1>; diff --git a/test/TableGen/DagDefSubst.td b/test/TableGen/DagDefSubst.td index e5eebe9..92a207f 100644 --- a/test/TableGen/DagDefSubst.td +++ b/test/TableGen/DagDefSubst.td @@ -1,5 +1,6 @@ // RUN: tblgen %s | grep {dag d = (X Y)} // RUN: tblgen %s | grep {dag e = (Y X)} +// XFAIL: vg_leak def X; class yclass; diff --git a/test/TableGen/DagIntSubst.td b/test/TableGen/DagIntSubst.td index 3c1291c..00fde69 100644 --- a/test/TableGen/DagIntSubst.td +++ b/test/TableGen/DagIntSubst.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {dag d = (X 13)} +// XFAIL: vg_leak def X; class C<int N> { diff --git a/test/TableGen/DefmInherit.td b/test/TableGen/DefmInherit.td index 4f37edf..9e16670 100644 --- a/test/TableGen/DefmInherit.td +++ b/test/TableGen/DefmInherit.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {zing = 4} | count 4 +// XFAIL: vg_leak class C1<int A, string B> { int bar = A; diff --git a/test/TableGen/ForwardRef.td b/test/TableGen/ForwardRef.td index 2056b1f..955cc14 100644 --- a/test/TableGen/ForwardRef.td +++ b/test/TableGen/ForwardRef.td @@ -1,4 +1,5 @@ // RUN: tblgen %s -o - +// XFAIL: vg_leak class bar { list<bar> x; diff --git a/test/TableGen/GeneralList.td b/test/TableGen/GeneralList.td index 7f099f2..ca92a21 100644 --- a/test/TableGen/GeneralList.td +++ b/test/TableGen/GeneralList.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak // // Test to make sure that lists work with any data-type diff --git a/test/TableGen/IntBitInit.td b/test/TableGen/IntBitInit.td index b949bfe..16ac9c8 100644 --- a/test/TableGen/IntBitInit.td +++ b/test/TableGen/IntBitInit.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak def { bit A = 1; int B = A; diff --git a/test/TableGen/LazyChange.td b/test/TableGen/LazyChange.td index 145fd0b..fa53562 100644 --- a/test/TableGen/LazyChange.td +++ b/test/TableGen/LazyChange.td @@ -1,5 +1,5 @@ // RUN: tblgen %s | grep {int Y = 3} - +// XFAIL: vg_leak class C { int X = 4; diff --git a/test/TableGen/ListArgs.td b/test/TableGen/ListArgs.td index daa0de6..a513db6 100644 --- a/test/TableGen/ListArgs.td +++ b/test/TableGen/ListArgs.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak class B<list<int> v> { list<int> vals = v; diff --git a/test/TableGen/ListArgsSimple.td b/test/TableGen/ListArgsSimple.td index b3b2078..f7caed6 100644 --- a/test/TableGen/ListArgsSimple.td +++ b/test/TableGen/ListArgsSimple.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak class B<int v> { int val = v; diff --git a/test/TableGen/ListConversion.td b/test/TableGen/ListConversion.td index 773ed6e..222b614 100644 --- a/test/TableGen/ListConversion.td +++ b/test/TableGen/ListConversion.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak class A; class B : A; diff --git a/test/TableGen/ListSlices.td b/test/TableGen/ListSlices.td index be794cf..5848a4e 100644 --- a/test/TableGen/ListSlices.td +++ b/test/TableGen/ListSlices.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak def A { list<int> B = [10, 20, 30, 4, 1, 1231, 20]; diff --git a/test/TableGen/MultiClass.td b/test/TableGen/MultiClass.td index 52ba59c..9f92b73 100644 --- a/test/TableGen/MultiClass.td +++ b/test/TableGen/MultiClass.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {zing = 4} | count 2 +// XFAIL: vg_leak class C1<int A, string B> { int bar = A; diff --git a/test/TableGen/MultiClassDefName.td b/test/TableGen/MultiClassDefName.td index 2e71f7d..138c93d 100644 --- a/test/TableGen/MultiClassDefName.td +++ b/test/TableGen/MultiClassDefName.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep WorldHelloCC | count 1 +// XFAIL: vg_leak class C<string n> { string name = n; diff --git a/test/TableGen/MultiClassInherit.td b/test/TableGen/MultiClassInherit.td index d4c4ce5..9da80ba 100644 --- a/test/TableGen/MultiClassInherit.td +++ b/test/TableGen/MultiClassInherit.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {zing = 4} | count 28 +// XFAIL: vg_leak class C1<int A, string B> { int bar = A; diff --git a/test/TableGen/Slice.td b/test/TableGen/Slice.td index cd9c6da..22bf7fb 100644 --- a/test/TableGen/Slice.td +++ b/test/TableGen/Slice.td @@ -1,5 +1,6 @@ // RUN: tblgen %s | grep {\\\[(set} | count 2 // RUN: tblgen %s | grep {\\\[\\\]} | count 2 +// XFAIL: vg_leak class ValueType<int size, int value> { int Size = size; diff --git a/test/TableGen/String.td b/test/TableGen/String.td index d2ae451..fc0f5b8 100644 --- a/test/TableGen/String.td +++ b/test/TableGen/String.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak class x { string y = "missing terminating '\"' character"; } diff --git a/test/TableGen/SuperSubclassSameName.td b/test/TableGen/SuperSubclassSameName.td index 087df87..304c883 100644 --- a/test/TableGen/SuperSubclassSameName.td +++ b/test/TableGen/SuperSubclassSameName.td @@ -1,4 +1,5 @@ // RUN: tblgen < %s +// XFAIL: vg_leak // Test for template arguments that have the same name as superclass template // arguments. diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td index 8299541..2871eb8 100644 --- a/test/TableGen/TargetInstrInfo.td +++ b/test/TableGen/TargetInstrInfo.td @@ -1,6 +1,7 @@ // This test describes how we eventually want to describe instructions in // the target independent code generators. // RUN: tblgen %s +// XFAIL: vg_leak // Target indep stuff. class Instruction { // Would have other stuff eventually diff --git a/test/TableGen/TargetInstrSpec.td b/test/TableGen/TargetInstrSpec.td index 7c3dd57..a7ca902 100644 --- a/test/TableGen/TargetInstrSpec.td +++ b/test/TableGen/TargetInstrSpec.td @@ -1,5 +1,6 @@ // RUN: tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_pd VR128:\$src1, VR128:\$src2))\\\]} | count 1 // RUN: tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_ps VR128:\$src1, VR128:\$src2))\\\]} | count 1 +// XFAIL: vg_leak class ValueType<int size, int value> { int Size = size; diff --git a/test/TableGen/TemplateArgRename.td b/test/TableGen/TemplateArgRename.td index 535c2e4..ee5d2cf 100644 --- a/test/TableGen/TemplateArgRename.td +++ b/test/TableGen/TemplateArgRename.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak // Make sure there is no collision between XX and XX. def S; diff --git a/test/TableGen/Tree.td b/test/TableGen/Tree.td index f9f1f15..2796cfd 100644 --- a/test/TableGen/Tree.td +++ b/test/TableGen/Tree.td @@ -1,5 +1,6 @@ // This tests to make sure we can parse tree patterns. // RUN: tblgen %s +// XFAIL: vg_leak class TreeNode; class RegisterClass; diff --git a/test/TableGen/TreeNames.td b/test/TableGen/TreeNames.td index 05a3298..ccdeb88 100644 --- a/test/TableGen/TreeNames.td +++ b/test/TableGen/TreeNames.td @@ -1,5 +1,6 @@ // This tests to make sure we can parse tree patterns with names. // RUN: tblgen %s +// XFAIL: vg_leak class TreeNode; class RegisterClass; diff --git a/test/TableGen/UnsetBitInit.td b/test/TableGen/UnsetBitInit.td index 91342ec..ff70108 100644 --- a/test/TableGen/UnsetBitInit.td +++ b/test/TableGen/UnsetBitInit.td @@ -1,4 +1,5 @@ // RUN: tblgen %s +// XFAIL: vg_leak class x { field bits<32> A; } diff --git a/test/TableGen/cast.td b/test/TableGen/cast.td index 4a771ae..8164e74 100644 --- a/test/TableGen/cast.td +++ b/test/TableGen/cast.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {add_ps} | count 3 +// XFAIL: vg_leak class ValueType<int size, int value> { int Size = size; diff --git a/test/TableGen/eq.td b/test/TableGen/eq.td index 8ba6d7e..518a80a 100644 --- a/test/TableGen/eq.td +++ b/test/TableGen/eq.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak // CHECK: Value = 0 // CHECK: Value = 1 diff --git a/test/TableGen/foreach.td b/test/TableGen/foreach.td index acce449..d4d81f8 100644 --- a/test/TableGen/foreach.td +++ b/test/TableGen/foreach.td @@ -1,6 +1,7 @@ // RUN: tblgen %s | grep {Jr} | count 2 // RUN: tblgen %s | grep {Sr} | count 2 // RUN: tblgen %s | grep {NAME} | count 1 +// XFAIL: vg_leak // Variables for foreach class decls { diff --git a/test/TableGen/if.td b/test/TableGen/if.td index 9b24382..0bac0ba 100644 --- a/test/TableGen/if.td +++ b/test/TableGen/if.td @@ -1,5 +1,6 @@ // RUN: tblgen %s | grep {\\\[1, 2, 3\\\]} | count 4 // RUN: tblgen %s | grep {\\\[4, 5, 6\\\]} | count 2 +// XFAIL: vg_leak class A<list<list<int>> vals> { list<int> first = vals[0]; diff --git a/test/TableGen/lisp.td b/test/TableGen/lisp.td index 3e392fd..b521e04 100644 --- a/test/TableGen/lisp.td +++ b/test/TableGen/lisp.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {} +// XFAIL: vg_leak class List<list<string> n> { list<string> names = n; diff --git a/test/TableGen/nameconcat.td b/test/TableGen/nameconcat.td index fc865f9..fd2880a 100644 --- a/test/TableGen/nameconcat.td +++ b/test/TableGen/nameconcat.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep {add_ps} | count 3 +// XFAIL: vg_leak class ValueType<int size, int value> { int Size = size; diff --git a/test/TableGen/strconcat.td b/test/TableGen/strconcat.td index fc0d805..38409a9 100644 --- a/test/TableGen/strconcat.td +++ b/test/TableGen/strconcat.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | grep fufoo +// XFAIL: vg_leak class Y<string S> { string T = !strconcat(S, "foo"); diff --git a/test/TableGen/subst.td b/test/TableGen/subst.td index ce9f45d..05d424f 100644 --- a/test/TableGen/subst.td +++ b/test/TableGen/subst.td @@ -4,6 +4,7 @@ // RUN: tblgen %s | grep {LAST} | count 1 // RUN: tblgen %s | grep {TVAR} | count 2 // RUN: tblgen %s | grep {Bogus} | count 1 +// XFAIL: vg_leak class Honorific<string t> { string honorific = t; diff --git a/test/TableGen/subst2.td b/test/TableGen/subst2.td index 3366c9d..584266e 100644 --- a/test/TableGen/subst2.td +++ b/test/TableGen/subst2.td @@ -1,4 +1,5 @@ // RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak // CHECK: No subst // CHECK: No foo // CHECK: RECURSE foo diff --git a/test/Transforms/ArgumentPromotion/crash.ll b/test/Transforms/ArgumentPromotion/crash.ll new file mode 100644 index 0000000..e2d3d4d --- /dev/null +++ b/test/Transforms/ArgumentPromotion/crash.ll @@ -0,0 +1,38 @@ +; rdar://7879828 +; RUN: opt -inline -argpromotion %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define void @foo() { + invoke void @foo2() + to label %if.end432 unwind label %for.end520 + +if.end432: + unreachable + +for.end520: + unreachable +} + +define internal void @foo2() ssp { + %call7 = call fastcc i8* @foo3(i1 (i8*)* @foo4) + %call58 = call fastcc i8* @foo3(i1 (i8*)* @foo5) + unreachable +} + +define internal fastcc i8* @foo3(i1 (i8*)* %Pred) { +entry: + unreachable +} + +define internal i1 @foo4(i8* %O) nounwind { +entry: + %call = call zeroext i1 @foo5(i8* %O) ; <i1> [#uses=0] + unreachable +} + +define internal i1 @foo5(i8* %O) nounwind { +entry: + ret i1 undef +} + diff --git a/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll b/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll index f251d6c..161821f 100644 --- a/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll +++ b/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll @@ -23,4 +23,4 @@ T: ret i32 %y T2: unreachable -}
\ No newline at end of file +} diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll new file mode 100644 index 0000000..7256b93 --- /dev/null +++ b/test/Transforms/DeadArgElim/deadexternal.ll @@ -0,0 +1,13 @@ +; RUN: opt -deadargelim -S %s | FileCheck %s +; XFAIL: * + +define void @test(i32) { + ret void +} + +define void @foo() { + call void @test(i32 0) + ret void +; CHECK: @foo +; CHECK: i32 undef +} diff --git a/test/Transforms/DeadStoreElimination/crash.ll b/test/Transforms/DeadStoreElimination/crash.ll index 6d8ba71..5aac877 100644 --- a/test/Transforms/DeadStoreElimination/crash.ll +++ b/test/Transforms/DeadStoreElimination/crash.ll @@ -54,4 +54,4 @@ dead: store i32 4, i32* %P2 store i32 4, i32* %Q2 br label %dead -}
\ No newline at end of file +} diff --git a/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll b/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll new file mode 100644 index 0000000..066e303 --- /dev/null +++ b/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll @@ -0,0 +1,46 @@ +; RUN: opt < %s -gvn -enable-full-load-pre -S | FileCheck %s + +define i8* @cat(i8* %s1, ...) nounwind { +entry: + br i1 undef, label %bb, label %bb3 + +bb: ; preds = %entry + unreachable + +bb3: ; preds = %entry + store i8* undef, i8** undef, align 4 + br i1 undef, label %bb5, label %bb6 + +bb5: ; preds = %bb3 + unreachable + +bb6: ; preds = %bb3 + br label %bb12 + +bb8: ; preds = %bb12 + br i1 undef, label %bb9, label %bb10 + +bb9: ; preds = %bb8 + %0 = load i8** undef, align 4 ; <i8*> [#uses=0] + %1 = load i8** undef, align 4 ; <i8*> [#uses=0] + br label %bb11 + +bb10: ; preds = %bb8 + br label %bb11 + +bb11: ; preds = %bb10, %bb9 +; CHECK: bb11: +; CHECK: phi +; CHECK-NOT: phi + br label %bb12 + +bb12: ; preds = %bb11, %bb6 +; CHECK: bb12: +; CHECK: phi +; CHECK-NOT: phi + br i1 undef, label %bb8, label %bb13 + +bb13: ; preds = %bb12 +; CHECK: bb13: + ret i8* undef +} diff --git a/test/Transforms/GVN/invariant-simple.ll b/test/Transforms/GVN/invariant-simple.ll index 6de75f1..0a4182c 100644 --- a/test/Transforms/GVN/invariant-simple.ll +++ b/test/Transforms/GVN/invariant-simple.ll @@ -33,4 +33,4 @@ entry: declare i32 @foo(i8*) nounwind declare i32 @bar(i8*) nounwind readonly declare {}* @llvm.invariant.start(i64 %S, i8* nocapture %P) readonly -declare void @llvm.invariant.end({}* %S, i64 %SS, i8* nocapture %P)
\ No newline at end of file +declare void @llvm.invariant.end({}* %S, i64 %SS, i8* nocapture %P) diff --git a/test/Transforms/GVN/lifetime-simple.ll b/test/Transforms/GVN/lifetime-simple.ll index 8139246..48e5bc8 100644 --- a/test/Transforms/GVN/lifetime-simple.ll +++ b/test/Transforms/GVN/lifetime-simple.ll @@ -16,5 +16,5 @@ entry: ret i8 %1 } -declare {}* @llvm.lifetime.start(i64 %S, i8* nocapture %P) readonly -declare void @llvm.lifetime.end(i64 %S, i8* nocapture %P)
\ No newline at end of file +declare void @llvm.lifetime.start(i64 %S, i8* nocapture %P) readonly +declare void @llvm.lifetime.end(i64 %S, i8* nocapture %P) diff --git a/test/Transforms/GVN/rle.ll b/test/Transforms/GVN/rle.ll index d419fd2..d656c1a 100644 --- a/test/Transforms/GVN/rle.ll +++ b/test/Transforms/GVN/rle.ll @@ -531,4 +531,16 @@ out: } +; PR6642 +define i32 @memset_to_load() nounwind readnone { +entry: + %x = alloca [256 x i32], align 4 ; <[256 x i32]*> [#uses=2] + %tmp = bitcast [256 x i32]* %x to i8* ; <i8*> [#uses=1] + call void @llvm.memset.i64(i8* %tmp, i8 0, i64 1024, i32 4) + %arraydecay = getelementptr inbounds [256 x i32]* %x, i32 0, i32 0 ; <i32*> + %tmp1 = load i32* %arraydecay ; <i32> [#uses=1] + ret i32 %tmp1 +; CHECK: @memset_to_load +; CHECK: ret i32 0 +} diff --git a/test/Transforms/GlobalOpt/crash.ll b/test/Transforms/GlobalOpt/crash.ll index a45cbe9..701472c 100644 --- a/test/Transforms/GlobalOpt/crash.ll +++ b/test/Transforms/GlobalOpt/crash.ll @@ -9,8 +9,34 @@ target triple = "i386-apple-darwin9.8" @_ZL6vTwist = global %struct.btSimdScalar zeroinitializer ; <%struct.btSimdScalar*> [#uses=1] @llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev }] ; <[12 x %0]*> [#uses=0] -define internal void @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { +define internal void @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { entry: store float 1.0, float* getelementptr inbounds (%struct.btSimdScalar* @_ZL6vTwist, i32 0, i32 0, i32 0, i32 3), align 4 ret void } + + +; PR6760 +%T = type { [5 x i32] } + +@switch_inf = internal global %T* null + +define void @test(i8* %arch_file, i32 %route_type) { +entry: + %A = sext i32 1 to i64 + %B = mul i64 %A, 20 + %C = call noalias i8* @malloc(i64 %B) nounwind + %D = bitcast i8* %C to %T* + store %T* %D, %T** @switch_inf, align 8 + unreachable + +bb.nph.i: + %scevgep.i539 = getelementptr i8* %C, i64 4 + unreachable + +xx: + %E = load %T** @switch_inf, align 8 + unreachable +} + +declare noalias i8* @malloc(i64) nounwind diff --git a/test/Transforms/GlobalOpt/malloc-promote-2.ll b/test/Transforms/GlobalOpt/malloc-promote-2.ll index f989b79..6cb4481 100644 --- a/test/Transforms/GlobalOpt/malloc-promote-2.ll +++ b/test/Transforms/GlobalOpt/malloc-promote-2.ll @@ -1,24 +1,19 @@ -; RUN: opt < %s -globalopt -globaldce -S | not grep malloc +; RUN: opt < %s -globalopt -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" -@G = internal global i32* null ; <i32**> [#uses=3] +@G = internal global i32* null -define void @init() { - %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) ; <i8*> [#uses=1] - %P = bitcast i8* %malloccall to i32* ; <i32*> [#uses=1] - store i32* %P, i32** @G - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - store i32 20, i32* %GVe - ret void +define void @t() { +; CHECK: @t() +; CHECK-NOT: call i8* @malloc +; CHECK-NEXT: ret void + %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) + %P = bitcast i8* %malloccall to i32* + store i32* %P, i32** @G + %GV = load i32** @G + %GVe = getelementptr i32* %GV, i32 40 + store i32 20, i32* %GVe + ret void } declare noalias i8* @malloc(i64) - -define i32 @get() { - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - %V = load i32* %GVe ; <i32> [#uses=1] - ret i32 %V -} - diff --git a/test/Transforms/GlobalOpt/malloc-promote-3.ll b/test/Transforms/GlobalOpt/malloc-promote-3.ll deleted file mode 100644 index 57f937d..0000000 --- a/test/Transforms/GlobalOpt/malloc-promote-3.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: opt < %s -globalopt -globaldce -S | not grep malloc -target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" - -@G = internal global i32* null ; <i32**> [#uses=4] - -define void @init() { - %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) ; <i8*> [#uses=1] - %P = bitcast i8* %malloccall to i32* ; <i32*> [#uses=1] - store i32* %P, i32** @G - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - store i32 20, i32* %GVe - ret void -} - -declare noalias i8* @malloc(i64) - -define i32 @get() { - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - %V = load i32* %GVe ; <i32> [#uses=1] - ret i32 %V -} - -define i1 @check() { - %GV = load i32** @G ; <i32*> [#uses=1] - %V = icmp eq i32* %GV, null ; <i1> [#uses=1] - ret i1 %V -} - diff --git a/test/Transforms/IndVarSimplify/2008-11-17-Floating.ll b/test/Transforms/IndVarSimplify/2008-11-17-Floating.ll deleted file mode 100644 index 311d3da..0000000 --- a/test/Transforms/IndVarSimplify/2008-11-17-Floating.ll +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: opt < %s -indvars -S | grep icmp | count 2 -; RUN: opt < %s -indvars -S | grep sitofp | count 1 -; RUN: opt < %s -indvars -S | grep uitofp | count 1 - -define void @bar() nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %x.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; <double> [#uses=2] - %0 = tail call i32 @foo(double %x.0.reg2mem.0) nounwind ; <i32> [#uses=0] - %1 = fadd double %x.0.reg2mem.0, 1.0e+0 ; <double> [#uses=2] - %2 = fcmp olt double %1, 2147483646.0e+0 ; <i1> [#uses=1] - br i1 %2, label %bb, label %return - -return: ; preds = %bb - ret void -} - -define void @bar1() nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %x.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; <double> [#uses=2] - %0 = tail call i32 @foo(double %x.0.reg2mem.0) nounwind ; <i32> [#uses=0] - %1 = fadd double %x.0.reg2mem.0, 1.0e+0 ; <double> [#uses=2] - %2 = fcmp olt double %1, 2147483647.0e+0 ; <i1> [#uses=1] - br i1 %2, label %bb, label %return - -return: ; preds = %bb - ret void -} - -declare i32 @foo(double) diff --git a/test/Transforms/IndVarSimplify/casted-argument.ll b/test/Transforms/IndVarSimplify/casted-argument.ll index dfefe1d..a5e002b 100644 --- a/test/Transforms/IndVarSimplify/casted-argument.ll +++ b/test/Transforms/IndVarSimplify/casted-argument.ll @@ -47,4 +47,4 @@ if.end54: ; preds = %if.end54, %if.else declare void @bcopy(i8* nocapture) nounwind -declare void @bcopy_4038(i8*, i32) nounwind +declare void @bcopy_4038(i8*, i8*, i32) nounwind diff --git a/test/Transforms/IndVarSimplify/crash.ll b/test/Transforms/IndVarSimplify/crash.ll new file mode 100644 index 0000000..ab43833 --- /dev/null +++ b/test/Transforms/IndVarSimplify/crash.ll @@ -0,0 +1,19 @@ +; RUN: opt -indvars %s -disable-output + +declare i32 @putchar(i8) nounwind + +define void @t2(i1* %P) nounwind { +; <label>:0 + br label %1 + +; <label>:1 ; preds = %1, %0 + %2 = phi double [ 9.000000e+00, %0 ], [ %4, %1 ] ; <double> [#uses=1] + %3 = tail call i32 @putchar(i8 72) ; <i32> [#uses=0] + %4 = fadd double %2, -1.000000e+00 ; <double> [#uses=2] + %5 = fcmp ult double %4, 0.000000e+00 ; <i1> [#uses=1] + store i1 %5, i1* %P + br i1 %5, label %6, label %1 + +; <label>:6 ; preds = %1 + ret void +} diff --git a/test/Transforms/IndVarSimplify/dangling-use.ll b/test/Transforms/IndVarSimplify/dangling-use.ll new file mode 100644 index 0000000..51c3120 --- /dev/null +++ b/test/Transforms/IndVarSimplify/dangling-use.ll @@ -0,0 +1,41 @@ +; RUN: opt -indvars -disable-output < %s + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i8:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" +target triple = "powerpc-apple-darwin11" + +define void @vec_inverse_5_7_vert_loop_copyseparate(i8* %x, i32 %n, i32 %rowbytes) nounwind { +entry: + %tmp1 = sdiv i32 %n, 3 ; <i32> [#uses=1] + %tmp2 = sdiv i32 %rowbytes, 5 ; <i32> [#uses=2] + br label %bb49 + +bb49: ; preds = %bb48, %entry + %x_addr.0 = phi i8* [ %x, %entry ], [ %tmp481, %bb48 ] ; <i8*> [#uses=2] + br label %bb10 + +bb10: ; preds = %bb49 + %tmp326 = mul nsw i32 %tmp1, %tmp2 ; <i32> [#uses=1] + %tmp351 = getelementptr inbounds i8* %x_addr.0, i32 %tmp326 ; <i8*> [#uses=1] + br i1 false, label %bb.nph, label %bb48 + +bb.nph: ; preds = %bb10 + br label %bb23 + +bb23: ; preds = %bb28, %bb.nph + %pOriginHi.01 = phi i8* [ %tmp351, %bb.nph ], [ %pOriginHi.0, %bb28 ] ; <i8*> [#uses=2] + %tmp378 = bitcast i8* %pOriginHi.01 to i8* ; <i8*> [#uses=1] + store i8* %tmp378, i8** null + %tmp385 = getelementptr inbounds i8* %pOriginHi.01, i32 %tmp2 ; <i8*> [#uses=1] + br label %bb28 + +bb28: ; preds = %bb23 + %pOriginHi.0 = phi i8* [ %tmp385, %bb23 ] ; <i8*> [#uses=1] + br i1 false, label %bb23, label %bb28.bb48_crit_edge + +bb28.bb48_crit_edge: ; preds = %bb28 + br label %bb48 + +bb48: ; preds = %bb28.bb48_crit_edge, %bb10 + %tmp481 = getelementptr inbounds i8* %x_addr.0, i32 1 ; <i8*> [#uses=1] + br label %bb49 +} diff --git a/test/Transforms/IndVarSimplify/eliminate-comparison.ll b/test/Transforms/IndVarSimplify/eliminate-comparison.ll new file mode 100644 index 0000000..953bbdf --- /dev/null +++ b/test/Transforms/IndVarSimplify/eliminate-comparison.ll @@ -0,0 +1,108 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +@X = external global [0 x double] + +; Indvars should be able to simplify simple comparisons involving +; induction variables. + +; CHECK: @foo +; CHECK: %cond = and i1 %tobool.not, true + +define void @foo(i64 %n, i32* nocapture %p) nounwind { +entry: + %cmp9 = icmp sgt i64 %n, 0 + br i1 %cmp9, label %pre, label %return + +pre: + %t3 = load i32* %p + %tobool.not = icmp ne i32 %t3, 0 + br label %loop + +loop: + %i = phi i64 [ 0, %pre ], [ %inc, %for.inc ] + %cmp6 = icmp slt i64 %i, %n + %cond = and i1 %tobool.not, %cmp6 + br i1 %cond, label %if.then, label %for.inc + +if.then: + %arrayidx = getelementptr [0 x double]* @X, i64 0, i64 %i + store double 3.200000e+00, double* %arrayidx + br label %for.inc + +for.inc: + %inc = add nsw i64 %i, 1 + %exitcond = icmp sge i64 %inc, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; Don't eliminate an icmp that's contributing to the loop exit test though. + +; CHECK: @_ZNK4llvm5APInt3ultERKS0_ +; CHECK: %tmp99 = icmp sgt i32 %i, -1 + +define i32 @_ZNK4llvm5APInt3ultERKS0_(i32 %tmp2.i1, i64** %tmp65, i64** %tmp73, i64** %tmp82, i64** %tmp90) { +entry: + br label %bb18 + +bb13: + %tmp66 = load i64** %tmp65, align 4 + %tmp68 = getelementptr inbounds i64* %tmp66, i32 %i + %tmp69 = load i64* %tmp68, align 4 + %tmp74 = load i64** %tmp73, align 4 + %tmp76 = getelementptr inbounds i64* %tmp74, i32 %i + %tmp77 = load i64* %tmp76, align 4 + %tmp78 = icmp ugt i64 %tmp69, %tmp77 + br i1 %tmp78, label %bb20.loopexit, label %bb15 + +bb15: + %tmp83 = load i64** %tmp82, align 4 + %tmp85 = getelementptr inbounds i64* %tmp83, i32 %i + %tmp86 = load i64* %tmp85, align 4 + %tmp91 = load i64** %tmp90, align 4 + %tmp93 = getelementptr inbounds i64* %tmp91, i32 %i + %tmp94 = load i64* %tmp93, align 4 + %tmp95 = icmp ult i64 %tmp86, %tmp94 + br i1 %tmp95, label %bb20.loopexit, label %bb17 + +bb17: + %tmp97 = add nsw i32 %i, -1 + br label %bb18 + +bb18: + %i = phi i32 [ %tmp2.i1, %entry ], [ %tmp97, %bb17 ] + %tmp99 = icmp sgt i32 %i, -1 + br i1 %tmp99, label %bb13, label %bb20.loopexit + +bb20.loopexit: + %tmp.0.ph = phi i32 [ 0, %bb18 ], [ 1, %bb15 ], [ 0, %bb13 ] + ret i32 %tmp.0.ph +} + +; Indvars should eliminate the icmp here. + +; CHECK: @func_10 +; CHECK-NOT: icmp +; CHECK: ret void + +define void @func_10() nounwind { +entry: + br label %loop + +loop: + %i = phi i32 [ %i.next, %loop ], [ 0, %entry ] + %t0 = icmp slt i32 %i, 0 + %t1 = zext i1 %t0 to i32 + %t2 = add i32 %t1, %i + %u3 = zext i32 %t2 to i64 + store i64 %u3, i64* null + %i.next = add i32 %i, 1 + br i1 undef, label %loop, label %return + +return: + ret void +} diff --git a/test/Transforms/IndVarSimplify/eliminate-max.ll b/test/Transforms/IndVarSimplify/eliminate-max.ll new file mode 100644 index 0000000..c25bd0e --- /dev/null +++ b/test/Transforms/IndVarSimplify/eliminate-max.ll @@ -0,0 +1,52 @@ +; RUN: opt < %s -S -indvars | grep {= icmp} | count 3 +; PR4914.ll + +; Indvars should be able to do range analysis and eliminate icmps. +; There are two here which cannot be eliminated. +; There's one that icmp which can be eliminated and which indvars currently +; cannot eliminate, because it requires analyzing more than just the +; range of the induction variable. + +@0 = private constant [4 x i8] c"%d\0A\00", align 1 ; <[4 x i8]*> [#uses=1] + +define i32 @main() nounwind { +bb: + br label %bb1 + +bb1: ; preds = %bb14, %bb + %t = phi i32 [ 0, %bb ], [ %t19, %bb14 ] ; <i32> [#uses=5] + %t2 = phi i32 [ 0, %bb ], [ %t18, %bb14 ] ; <i32> [#uses=1] + %t3 = icmp slt i32 %t, 0 ; <i1> [#uses=1] + br i1 %t3, label %bb7, label %bb4 + +bb4: ; preds = %bb1 + %t5 = icmp sgt i32 %t, 255 ; <i1> [#uses=1] + %t6 = select i1 %t5, i32 255, i32 %t ; <i32> [#uses=1] + br label %bb7 + +bb7: ; preds = %bb4, %bb1 + %t8 = phi i32 [ %t6, %bb4 ], [ 0, %bb1 ] ; <i32> [#uses=1] + %t9 = sub i32 0, %t ; <i32> [#uses=3] + %t10 = icmp slt i32 %t9, 0 ; <i1> [#uses=1] + br i1 %t10, label %bb14, label %bb11 + +bb11: ; preds = %bb7 + %t12 = icmp sgt i32 %t9, 255 ; <i1> [#uses=1] + %t13 = select i1 %t12, i32 255, i32 %t9 ; <i32> [#uses=1] + br label %bb14 + +bb14: ; preds = %bb11, %bb7 + %t15 = phi i32 [ %t13, %bb11 ], [ 0, %bb7 ] ; <i32> [#uses=1] + %t16 = add nsw i32 %t2, 255 ; <i32> [#uses=1] + %t17 = add nsw i32 %t16, %t8 ; <i32> [#uses=1] + %t18 = add nsw i32 %t17, %t15 ; <i32> [#uses=2] + %t19 = add nsw i32 %t, 1 ; <i32> [#uses=2] + %t20 = icmp slt i32 %t19, 1000000000 ; <i1> [#uses=1] + br i1 %t20, label %bb1, label %bb21 + +bb21: ; preds = %bb14 + %t22 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([4 x i8]* @0, i32 0, i32 0), i32 %t18) nounwind + ret i32 0 +} + +declare i32 @printf(i8* noalias nocapture, ...) nounwind diff --git a/test/Transforms/IndVarSimplify/eliminate-rem.ll b/test/Transforms/IndVarSimplify/eliminate-rem.ll new file mode 100644 index 0000000..f756389 --- /dev/null +++ b/test/Transforms/IndVarSimplify/eliminate-rem.ll @@ -0,0 +1,121 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +; Indvars should be able to eliminate this srem. +; CHECK: @simple +; CHECK-NOT: rem +; CHECK: ret + +define void @simple(i64 %arg, double* %arg3) nounwind { +bb: + %t = icmp slt i64 0, %arg ; <i1> [#uses=1] + br i1 %t, label %bb4, label %bb12 + +bb4: ; preds = %bb + br label %bb5 + +bb5: ; preds = %bb4, %bb5 + %t6 = phi i64 [ %t9, %bb5 ], [ 0, %bb4 ] ; <i64> [#uses=2] + %t7 = srem i64 %t6, %arg ; <i64> [#uses=1] + %t8 = getelementptr inbounds double* %arg3, i64 %t7 ; <double*> [#uses=1] + store double 0.000000e+00, double* %t8 + %t9 = add nsw i64 %t6, 1 ; <i64> [#uses=2] + %t10 = icmp slt i64 %t9, %arg ; <i1> [#uses=1] + br i1 %t10, label %bb5, label %bb11 + +bb11: ; preds = %bb5 + br label %bb12 + +bb12: ; preds = %bb11, %bb + ret void +} + +; Indvars should be able to eliminate the (i+1)%n. +; CHECK: @f +; CHECK-NOT: rem +; CHECK: rem +; CHECK-NOT: rem +; CHECK: ret + +define i32 @f(i64* %arg, i64 %arg1, i64 %arg2, i64 %arg3) nounwind { +bb: + %t = icmp sgt i64 %arg1, 0 ; <i1> [#uses=1] + br i1 %t, label %bb4, label %bb54 + +bb4: ; preds = %bb + br label %bb5 + +bb5: ; preds = %bb49, %bb4 + %t6 = phi i64 [ %t51, %bb49 ], [ 0, %bb4 ] ; <i64> [#uses=4] + %t7 = phi i32 [ %t50, %bb49 ], [ 0, %bb4 ] ; <i32> [#uses=2] + %t8 = add nsw i64 %t6, %arg1 ; <i64> [#uses=1] + %t9 = add nsw i64 %t8, -2 ; <i64> [#uses=1] + %t10 = srem i64 %t9, %arg1 ; <i64> [#uses=1] + %t11 = add nsw i64 %t10, 1 ; <i64> [#uses=1] + %t12 = add nsw i64 %t6, 1 ; <i64> [#uses=1] + %t13 = srem i64 %t12, %arg1 ; <i64> [#uses=1] + %t14 = icmp sgt i64 %arg1, 0 ; <i1> [#uses=1] + br i1 %t14, label %bb15, label %bb49 + +bb15: ; preds = %bb5 + br label %bb16 + +bb16: ; preds = %bb44, %bb15 + %t17 = phi i64 [ %t46, %bb44 ], [ 0, %bb15 ] ; <i64> [#uses=1] + %t18 = phi i32 [ %t45, %bb44 ], [ %t7, %bb15 ] ; <i32> [#uses=2] + %t19 = icmp sgt i64 %arg1, 0 ; <i1> [#uses=1] + br i1 %t19, label %bb20, label %bb44 + +bb20: ; preds = %bb16 + br label %bb21 + +bb21: ; preds = %bb21, %bb20 + %t22 = phi i64 [ %t41, %bb21 ], [ 0, %bb20 ] ; <i64> [#uses=4] + %t23 = phi i32 [ %t40, %bb21 ], [ %t18, %bb20 ] ; <i32> [#uses=1] + %t24 = mul i64 %t6, %arg1 ; <i64> [#uses=1] + %t25 = mul i64 %t13, %arg1 ; <i64> [#uses=1] + %t26 = add nsw i64 %t24, %t22 ; <i64> [#uses=1] + %t27 = mul i64 %t11, %arg1 ; <i64> [#uses=1] + %t28 = add nsw i64 %t25, %t22 ; <i64> [#uses=1] + %t29 = getelementptr inbounds i64* %arg, i64 %t26 ; <i64*> [#uses=1] + %t30 = add nsw i64 %t27, %t22 ; <i64> [#uses=1] + %t31 = getelementptr inbounds i64* %arg, i64 %t28 ; <i64*> [#uses=1] + %t32 = zext i32 %t23 to i64 ; <i64> [#uses=1] + %t33 = load i64* %t29 ; <i64> [#uses=1] + %t34 = getelementptr inbounds i64* %arg, i64 %t30 ; <i64*> [#uses=1] + %t35 = load i64* %t31 ; <i64> [#uses=1] + %t36 = add nsw i64 %t32, %t33 ; <i64> [#uses=1] + %t37 = add nsw i64 %t36, %t35 ; <i64> [#uses=1] + %t38 = load i64* %t34 ; <i64> [#uses=1] + %t39 = add nsw i64 %t37, %t38 ; <i64> [#uses=1] + %t40 = trunc i64 %t39 to i32 ; <i32> [#uses=2] + %t41 = add nsw i64 %t22, 1 ; <i64> [#uses=2] + %t42 = icmp slt i64 %t41, %arg1 ; <i1> [#uses=1] + br i1 %t42, label %bb21, label %bb43 + +bb43: ; preds = %bb21 + br label %bb44 + +bb44: ; preds = %bb43, %bb16 + %t45 = phi i32 [ %t18, %bb16 ], [ %t40, %bb43 ] ; <i32> [#uses=2] + %t46 = add nsw i64 %t17, 1 ; <i64> [#uses=2] + %t47 = icmp slt i64 %t46, %arg1 ; <i1> [#uses=1] + br i1 %t47, label %bb16, label %bb48 + +bb48: ; preds = %bb44 + br label %bb49 + +bb49: ; preds = %bb48, %bb5 + %t50 = phi i32 [ %t7, %bb5 ], [ %t45, %bb48 ] ; <i32> [#uses=2] + %t51 = add nsw i64 %t6, 1 ; <i64> [#uses=2] + %t52 = icmp slt i64 %t51, %arg1 ; <i1> [#uses=1] + br i1 %t52, label %bb5, label %bb53 + +bb53: ; preds = %bb49 + br label %bb54 + +bb54: ; preds = %bb53, %bb + %t55 = phi i32 [ 0, %bb ], [ %t50, %bb53 ] ; <i32> [#uses=1] + ret i32 %t55 +} diff --git a/test/Transforms/IndVarSimplify/2008-11-03-Floating.ll b/test/Transforms/IndVarSimplify/floating-point-iv.ll index 7b4032b..8f4b870 100644 --- a/test/Transforms/IndVarSimplify/2008-11-03-Floating.ll +++ b/test/Transforms/IndVarSimplify/floating-point-iv.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -indvars -S | grep icmp | count 4 -define void @bar() nounwind { +; RUN: opt < %s -indvars -S | FileCheck %s +define void @test1() nounwind { entry: br label %bb @@ -12,11 +12,13 @@ bb: ; preds = %bb, %entry return: ; preds = %bb ret void +; CHECK: @test1 +; CHECK: icmp } declare i32 @foo(double) -define void @bar2() nounwind { +define void @test2() nounwind { entry: br label %bb @@ -29,25 +31,29 @@ bb: ; preds = %bb, %entry return: ; preds = %bb ret void +; CHECK: @test2 +; CHECK: icmp } -define void @bar3() nounwind { +define void @test3() nounwind { entry: br label %bb bb: ; preds = %bb, %entry - %x.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; <double> [#uses=2] - %0 = tail call i32 @foo(double %x.0.reg2mem.0) nounwind ; <i32> [#uses=0] - %1 = fadd double %x.0.reg2mem.0, 1.000000e+00 ; <double> [#uses=2] - %2 = fcmp olt double %1, -1.000000e+00 ; <i1> [#uses=1] + %x.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] + %0 = tail call i32 @foo(double %x.0.reg2mem.0) nounwind + %1 = fadd double %x.0.reg2mem.0, 1.000000e+00 + %2 = fcmp olt double %1, -1.000000e+00 br i1 %2, label %bb, label %return -return: ; preds = %bb +return: ret void +; CHECK: @test3 +; CHECK: fcmp } -define void @bar4() nounwind { +define void @test4() nounwind { entry: br label %bb @@ -58,8 +64,29 @@ bb: ; preds = %bb, %entry %2 = fcmp olt double %1, 1.000000e+00 ; <i1> [#uses=1] br i1 %2, label %bb, label %return -return: ; preds = %bb +return: ret void +; CHECK: @test4 +; CHECK: fcmp } +; PR6761 +define void @test5() nounwind { +; <label>:0 + br label %1 + +; <label>:1 ; preds = %1, %0 + %2 = phi double [ 9.000000e+00, %0 ], [ %4, %1 ] ; <double> [#uses=1] + %3 = tail call i32 @foo(double 0.0) ; <i32> [#uses=0] + %4 = fadd double %2, -1.000000e+00 ; <double> [#uses=2] + %5 = fcmp ult double %4, 0.000000e+00 ; <i1> [#uses=1] + br i1 %5, label %exit, label %1 + +exit: + ret void + +; CHECK: @test5 +; CHECK: icmp eq i32 {{.*}}, 10 +; CHECK-NEXT: br i1 +} diff --git a/test/Transforms/IndVarSimplify/udiv.ll b/test/Transforms/IndVarSimplify/udiv.ll new file mode 100644 index 0000000..8260093 --- /dev/null +++ b/test/Transforms/IndVarSimplify/udiv.ll @@ -0,0 +1,162 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +@main.flags = internal global [8193 x i8] zeroinitializer, align 1 ; <[8193 x i8]*> [#uses=5] +@.str = private constant [11 x i8] c"Count: %d\0A\00" ; <[11 x i8]*> [#uses=1] + +; Indvars shouldn't emit a udiv here, because there's no udiv in the +; original code. This comes from SingleSource/Benchmarks/Shootout/sieve.c. + +; CHECK: @main +; CHECK-NOT: div + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + %cmp = icmp eq i32 %argc, 2 ; <i1> [#uses=1] + br i1 %cmp, label %cond.true, label %while.cond.preheader + +cond.true: ; preds = %entry + %arrayidx = getelementptr inbounds i8** %argv, i64 1 ; <i8**> [#uses=1] + %tmp2 = load i8** %arrayidx ; <i8*> [#uses=1] + %call = tail call i32 @atoi(i8* %tmp2) nounwind readonly ; <i32> [#uses=1] + br label %while.cond.preheader + +while.cond.preheader: ; preds = %entry, %cond.true + %NUM.0.ph = phi i32 [ %call, %cond.true ], [ 170000, %entry ] ; <i32> [#uses=2] + %tobool18 = icmp eq i32 %NUM.0.ph, 0 ; <i1> [#uses=1] + br i1 %tobool18, label %while.end, label %bb.nph30 + +while.cond.loopexit: ; preds = %for.cond12.while.cond.loopexit_crit_edge, %for.cond12.loopexit + %count.2.lcssa = phi i32 [ %count.1.lcssa, %for.cond12.while.cond.loopexit_crit_edge ], [ 0, %for.cond12.loopexit ] ; <i32> [#uses=1] + br label %while.cond + +while.cond: ; preds = %while.cond.loopexit + %tobool = icmp eq i32 %dec19, 0 ; <i1> [#uses=1] + br i1 %tobool, label %while.cond.while.end_crit_edge, label %for.cond.preheader + +while.cond.while.end_crit_edge: ; preds = %while.cond + %count.2.lcssa.lcssa = phi i32 [ %count.2.lcssa, %while.cond ] ; <i32> [#uses=1] + br label %while.end + +bb.nph30: ; preds = %while.cond.preheader + br label %for.cond.preheader + +for.cond.preheader: ; preds = %bb.nph30, %while.cond + %dec19.in = phi i32 [ %NUM.0.ph, %bb.nph30 ], [ %dec19, %while.cond ] ; <i32> [#uses=1] + %dec19 = add i32 %dec19.in, -1 ; <i32> [#uses=2] + br i1 true, label %bb.nph, label %for.cond12.loopexit + +for.cond: ; preds = %for.body + %cmp8 = icmp slt i64 %inc, 8193 ; <i1> [#uses=1] + br i1 %cmp8, label %for.body, label %for.cond.for.cond12.loopexit_crit_edge + +for.cond.for.cond12.loopexit_crit_edge: ; preds = %for.cond + br label %for.cond12.loopexit + +bb.nph: ; preds = %for.cond.preheader + br label %for.body + +for.body: ; preds = %bb.nph, %for.cond + %i.02 = phi i64 [ 2, %bb.nph ], [ %inc, %for.cond ] ; <i64> [#uses=2] + %arrayidx10 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %i.02 ; <i8*> [#uses=1] + store i8 1, i8* %arrayidx10 + %inc = add nsw i64 %i.02, 1 ; <i64> [#uses=2] + br label %for.cond + +for.cond12.loopexit: ; preds = %for.cond.for.cond12.loopexit_crit_edge, %for.cond.preheader + br i1 true, label %bb.nph16, label %while.cond.loopexit + +for.cond12: ; preds = %for.inc35 + %cmp14 = icmp slt i64 %inc37, 8193 ; <i1> [#uses=1] + br i1 %cmp14, label %for.body15, label %for.cond12.while.cond.loopexit_crit_edge + +for.cond12.while.cond.loopexit_crit_edge: ; preds = %for.cond12 + %count.1.lcssa = phi i32 [ %count.1, %for.cond12 ] ; <i32> [#uses=1] + br label %while.cond.loopexit + +bb.nph16: ; preds = %for.cond12.loopexit + br label %for.body15 + +for.body15: ; preds = %bb.nph16, %for.cond12 + %count.212 = phi i32 [ 0, %bb.nph16 ], [ %count.1, %for.cond12 ] ; <i32> [#uses=2] + %i.17 = phi i64 [ 2, %bb.nph16 ], [ %inc37, %for.cond12 ] ; <i64> [#uses=4] + %arrayidx17 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %i.17 ; <i8*> [#uses=1] + %tmp18 = load i8* %arrayidx17 ; <i8> [#uses=1] + %tobool19 = icmp eq i8 %tmp18, 0 ; <i1> [#uses=1] + br i1 %tobool19, label %for.inc35, label %if.then + +if.then: ; preds = %for.body15 + %add = shl i64 %i.17, 1 ; <i64> [#uses=2] + %cmp243 = icmp slt i64 %add, 8193 ; <i1> [#uses=1] + br i1 %cmp243, label %bb.nph5, label %for.end32 + +for.cond22: ; preds = %for.body25 + %cmp24 = icmp slt i64 %add31, 8193 ; <i1> [#uses=1] + br i1 %cmp24, label %for.body25, label %for.cond22.for.end32_crit_edge + +for.cond22.for.end32_crit_edge: ; preds = %for.cond22 + br label %for.end32 + +bb.nph5: ; preds = %if.then + br label %for.body25 + +for.body25: ; preds = %bb.nph5, %for.cond22 + %k.04 = phi i64 [ %add, %bb.nph5 ], [ %add31, %for.cond22 ] ; <i64> [#uses=2] + %arrayidx27 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %k.04 ; <i8*> [#uses=1] + store i8 0, i8* %arrayidx27 + %add31 = add nsw i64 %k.04, %i.17 ; <i64> [#uses=2] + br label %for.cond22 + +for.end32: ; preds = %for.cond22.for.end32_crit_edge, %if.then + %inc34 = add nsw i32 %count.212, 1 ; <i32> [#uses=1] + br label %for.inc35 + +for.inc35: ; preds = %for.body15, %for.end32 + %count.1 = phi i32 [ %inc34, %for.end32 ], [ %count.212, %for.body15 ] ; <i32> [#uses=2] + %inc37 = add nsw i64 %i.17, 1 ; <i64> [#uses=2] + br label %for.cond12 + +while.end: ; preds = %while.cond.while.end_crit_edge, %while.cond.preheader + %count.0.lcssa = phi i32 [ %count.2.lcssa.lcssa, %while.cond.while.end_crit_edge ], [ 0, %while.cond.preheader ] ; <i32> [#uses=1] + %call40 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @atoi(i8* nocapture) nounwind readonly + +declare i32 @printf(i8* nocapture, ...) nounwind + +; IndVars shouldn't be afraid to emit a udiv here, since there's a udiv in +; the original code. + +; CHECK: @foo +; CHECK: for.body.preheader: +; CHECK-NEXT: udiv + +define void @foo(double* %p, i64 %n) nounwind { +entry: + %div0 = udiv i64 %n, 7 ; <i64> [#uses=1] + %div1 = add i64 %div0, 1 + %cmp2 = icmp ult i64 0, %div1 ; <i1> [#uses=1] + br i1 %cmp2, label %for.body.preheader, label %for.end + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2] + %arrayidx = getelementptr inbounds double* %p, i64 %i.03 ; <double*> [#uses=1] + store double 0.000000e+00, double* %arrayidx + %inc = add i64 %i.03, 1 ; <i64> [#uses=2] + %divx = udiv i64 %n, 7 ; <i64> [#uses=1] + %div = add i64 %divx, 1 + %cmp = icmp ult i64 %inc, %div ; <i1> [#uses=1] + br i1 %cmp, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void +} diff --git a/test/Transforms/Inline/crash.ll b/test/Transforms/Inline/crash.ll index f34b44c..1df4d60 100644 --- a/test/Transforms/Inline/crash.ll +++ b/test/Transforms/Inline/crash.ll @@ -86,3 +86,34 @@ bb260: lpad: unwind } + + + +;; This exposed a crash handling devirtualized calls. +define void @f1(void ()* %f) ssp { +entry: + call void %f() + ret void +} + +define void @f4(i32 %size) ssp { +entry: + invoke void @f1(void ()* @f3) + to label %invcont3 unwind label %lpad18 + +invcont3: ; preds = %bb1 + ret void + +lpad18: ; preds = %invcont3, %bb1 + unreachable +} + +define void @f3() ssp { +entry: + unreachable +} + +declare void @f5() ssp + + + diff --git a/test/Transforms/Inline/crash2.ll b/test/Transforms/Inline/crash2.ll new file mode 100644 index 0000000..cb1f44d --- /dev/null +++ b/test/Transforms/Inline/crash2.ll @@ -0,0 +1,29 @@ +; RUN: opt -inline -scalarrepl -max-cg-scc-iterations=1 %s -disable-output +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.3" + +declare i8* @f1(i8*) ssp align 2 + +define linkonce_odr void @f2(i8* %t) inlinehint ssp { +entry: + unreachable +} + +define linkonce_odr void @f3(void (i8*)* %__f) ssp { +entry: + %__f_addr = alloca void (i8*)*, align 8 + store void (i8*)* %__f, void (i8*)** %__f_addr + + %0 = load void (i8*)** %__f_addr, align 8 + call void %0(i8* undef) + call i8* @f1(i8* undef) ssp + unreachable +} + +define linkonce_odr void @f4(i8* %this) ssp align 2 { +entry: + %0 = alloca i32 + call void @f3(void (i8*)* @f2) ssp + ret void +} + diff --git a/test/Transforms/Inline/externally_available.ll b/test/Transforms/Inline/externally_available.ll index 43fe5d3..08b5638 100644 --- a/test/Transforms/Inline/externally_available.ll +++ b/test/Transforms/Inline/externally_available.ll @@ -13,4 +13,4 @@ define i32 @result() { %A = call i32 @test_function() %B = add i32 %A, 1 ret i32 %B -}
\ No newline at end of file +} diff --git a/test/Transforms/Inline/gvn-inline-iteration.ll b/test/Transforms/Inline/gvn-inline-iteration.ll new file mode 100644 index 0000000..32144d4 --- /dev/null +++ b/test/Transforms/Inline/gvn-inline-iteration.ll @@ -0,0 +1,23 @@ +; RUN: opt -inline -gvn %s -S -max-cg-scc-iterations=1 | FileCheck %s +; rdar://6295824 and PR6724 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @foo(i32 ()** noalias nocapture %p, i64* noalias nocapture %q) nounwind ssp { +entry: + store i32 ()* @bar, i32 ()** %p + store i64 0, i64* %q + %tmp3 = load i32 ()** %p ; <i32 ()*> [#uses=1] + %call = tail call i32 %tmp3() nounwind ; <i32> [#uses=1] + ret i32 %call +} +; CHECK: @foo +; CHECK: ret i32 7 +; CHECK: @bar +; CHECK: ret i32 7 + +define internal i32 @bar() nounwind readnone ssp { +entry: + ret i32 7 +} diff --git a/test/Transforms/Inline/indirect_resolve.ll b/test/Transforms/Inline/indirect_resolve.ll index 76182e2..02ff767 100644 --- a/test/Transforms/Inline/indirect_resolve.ll +++ b/test/Transforms/Inline/indirect_resolve.ll @@ -1,7 +1,7 @@ -; RUN: opt < %s -inline | llvm-dis +; RUN: opt < %s -inline -S | FileCheck %s ; PR4834 -define i32 @main() { +define i32 @test1() { %funcall1_ = call fastcc i32 ()* ()* @f1() %executecommandptr1_ = call i32 %funcall1_() ret i32 %executecommandptr1_ @@ -14,3 +14,31 @@ define internal fastcc i32 ()* @f1() nounwind readnone { define internal i32 @f2() nounwind readnone { ret i32 1 } + +; CHECK: @test1() +; CHECK-NEXT: ret i32 1 + + + + + +declare i8* @f1a(i8*) ssp align 2 + +define internal i32 @f2a(i8* %t) inlinehint ssp { +entry: + ret i32 41 +} + +define internal i32 @f3a(i32 (i8*)* %__f) ssp { +entry: + %A = call i32 %__f(i8* undef) + ret i32 %A +} + +define i32 @test2(i8* %this) ssp align 2 { + %X = call i32 @f3a(i32 (i8*)* @f2a) ssp + ret i32 %X +} + +; CHECK: @test2 +; CHECK-NEXT: ret i32 41 diff --git a/test/Transforms/Inline/noinline.ll b/test/Transforms/Inline/noinline.ll new file mode 100644 index 0000000..dc3f6e0 --- /dev/null +++ b/test/Transforms/Inline/noinline.ll @@ -0,0 +1,18 @@ +; RUN: opt %s -inline -S | FileCheck %s +; PR6682 +declare void @foo() nounwind + +define void @bar() nounwind { +entry: + tail call void @foo() nounwind + ret void +} + +define void @bazz() nounwind { +entry: + tail call void @bar() nounwind noinline + ret void +} + +; CHECK: define void @bazz() +; CHECK: call void @bar() diff --git a/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll b/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll index b59548f..8721c83 100644 --- a/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll +++ b/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll @@ -86,4 +86,4 @@ entry: %cmp = icmp ne i32 %sub, 0 %retval = select i1 %cmp, i32 1, i32 0 ret i32 %retval -}
\ No newline at end of file +} diff --git a/test/Transforms/InstCombine/gepgep.ll b/test/Transforms/InstCombine/gepgep.ll new file mode 100644 index 0000000..9e681d2 --- /dev/null +++ b/test/Transforms/InstCombine/gepgep.ll @@ -0,0 +1,13 @@ +; RUN: opt < %s -instcombine -disable-output + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +@buffer = external global [64 x float] + +declare void @use(i8*) + +define void @f() { + call void @use(i8* getelementptr (i8* getelementptr (i8* bitcast ([64 x float]* @buffer to i8*), i64 and (i64 sub (i64 0, i64 ptrtoint ([64 x float]* @buffer to i64)), i64 63)), i64 64)) + ret void +} diff --git a/test/Transforms/InstCombine/invariant.ll b/test/Transforms/InstCombine/invariant.ll index c67ad33..3832380 100644 --- a/test/Transforms/InstCombine/invariant.ll +++ b/test/Transforms/InstCombine/invariant.ll @@ -3,13 +3,13 @@ declare void @g(i8*) -declare { }* @llvm.invariant.start(i64, i8* nocapture) nounwind readonly +declare {}* @llvm.invariant.start(i64, i8* nocapture) nounwind readonly define i8 @f() { %a = alloca i8 ; <i8*> [#uses=4] store i8 0, i8* %a - %i = call { }* @llvm.invariant.start(i64 1, i8* %a) ; <{ }*> [#uses=0] - ; CHECK: call { }* @llvm.invariant.start + %i = call {}* @llvm.invariant.start(i64 1, i8* %a) ; <{}*> [#uses=0] + ; CHECK: call {}* @llvm.invariant.start call void @g(i8* %a) %r = load i8* %a ; <i8> [#uses=1] ret i8 %r diff --git a/test/Transforms/InstCombine/memset_chk.ll b/test/Transforms/InstCombine/memset_chk.ll index 5a4e6d9..58ecda5 100644 --- a/test/Transforms/InstCombine/memset_chk.ll +++ b/test/Transforms/InstCombine/memset_chk.ll @@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 define i32 @t() nounwind ssp { ; CHECK: @t -; CHECK: @llvm.memset.i64 +; CHECK: @llvm.memset.p0i8.i64 entry: %0 = alloca %struct.data, align 8 ; <%struct.data*> [#uses=1] %1 = bitcast %struct.data* %0 to i8* ; <i8*> [#uses=1] diff --git a/test/Transforms/InstCombine/objsize.ll b/test/Transforms/InstCombine/objsize.ll index 57dc2fd..664701b 100644 --- a/test/Transforms/InstCombine/objsize.ll +++ b/test/Transforms/InstCombine/objsize.ll @@ -111,15 +111,42 @@ define i32 @test4() nounwind ssp { entry: %0 = alloca %struct.data, align 8 %1 = bitcast %struct.data* %0 to i8* - %2 = call i64 @llvm.objectsize.i64(i8* %1, i1 false) nounwind + %2 = call i32 @llvm.objectsize.i32(i8* %1, i1 false) nounwind ; CHECK-NOT: @llvm.objectsize -; CHECK: @llvm.memset.i64(i8* %1, i8 0, i64 1824, i32 8) - %3 = call i8* @__memset_chk(i8* %1, i32 0, i64 1824, i64 %2) nounwind +; CHECK: @llvm.memset.p0i8.i32(i8* %1, i8 0, i32 1824, i32 8, i1 false) + %3 = call i8* @__memset_chk(i8* %1, i32 0, i32 1824, i32 %2) nounwind ret i32 0 } -declare i8* @__memset_chk(i8*, i32, i64, i64) nounwind +; rdar://7782496 +@s = external global i8* -declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly +define void @test5(i32 %n) nounwind ssp { +; CHECK: @test5 +entry: + %0 = tail call noalias i8* @malloc(i32 20) nounwind + %1 = tail call i32 @llvm.objectsize.i32(i8* %0, i1 false) + %2 = load i8** @s, align 8 +; CHECK-NOT: @llvm.objectsize +; CHECK: @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 10, i32 1, i1 false) + %3 = tail call i8* @__memcpy_chk(i8* %0, i8* %2, i32 10, i32 %1) nounwind + ret void +} -declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readonly +define void @test6(i32 %n) nounwind ssp { +; CHECK: @test6 +entry: + %0 = tail call noalias i8* @malloc(i32 20) nounwind + %1 = tail call i32 @llvm.objectsize.i32(i8* %0, i1 false) + %2 = load i8** @s, align 8 +; CHECK-NOT: @llvm.objectsize +; CHECK: @__memcpy_chk(i8* %0, i8* %1, i32 30, i32 20) + %3 = tail call i8* @__memcpy_chk(i8* %0, i8* %2, i32 30, i32 %1) nounwind + ret void +} + +declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind + +declare noalias i8* @malloc(i32) nounwind + +declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly diff --git a/test/Transforms/InstCombine/odr-linkage.ll b/test/Transforms/InstCombine/odr-linkage.ll index a64ef28..61365b4 100644 --- a/test/Transforms/InstCombine/odr-linkage.ll +++ b/test/Transforms/InstCombine/odr-linkage.ll @@ -16,4 +16,4 @@ define i32 @test() { %c = add i32 %b, %D ret i32 %c } -
\ No newline at end of file + diff --git a/test/Transforms/InstCombine/shift-sra.ll b/test/Transforms/InstCombine/shift-sra.ll index 58f3226..a578bbe 100644 --- a/test/Transforms/InstCombine/shift-sra.ll +++ b/test/Transforms/InstCombine/shift-sra.ll @@ -56,3 +56,23 @@ C: ; CHECK: %P = phi i64 ; CHECK-NEXT: ret i64 %P } + +; rdar://7732987 +define i32 @test5(i32 %Y) { + br i1 undef, label %A, label %C +A: + br i1 undef, label %B, label %D +B: + br label %D +C: + br i1 undef, label %D, label %E +D: + %P = phi i32 [0, %A], [0, %B], [%Y, %C] + %S = ashr i32 %P, 16 + ret i32 %S +; CHECK: @test5 +; CHECK: %P = phi i32 +; CHECK-NEXT: ashr i32 %P, 16 +E: + ret i32 0 +} diff --git a/test/Transforms/InstCombine/strcpy_chk.ll b/test/Transforms/InstCombine/strcpy_chk.ll index a20a13c..8835a0b 100644 --- a/test/Transforms/InstCombine/strcpy_chk.ll +++ b/test/Transforms/InstCombine/strcpy_chk.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @a = common global [60 x i8] zeroinitializer, align 1 ; <[60 x i8]*> [#uses=1] @.str = private constant [8 x i8] c"abcdefg\00" ; <[8 x i8]*> [#uses=1] diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll index 29adc1e..5132a8f 100644 --- a/test/Transforms/InstCombine/vec_shuffle.ll +++ b/test/Transforms/InstCombine/vec_shuffle.ll @@ -86,4 +86,4 @@ define <4 x i8> @test9(<16 x i8> %tmp6) nounwind { %tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 > ; <<4 x i8>> [#uses=1] %tmp9 = shufflevector <4 x i8> %tmp7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 > ; <<4 x i8>> [#uses=1] ret <4 x i8> %tmp9 -}
\ No newline at end of file +} diff --git a/test/Transforms/JumpThreading/crash.ll b/test/Transforms/JumpThreading/crash.ll index c65fd10..21620be 100644 --- a/test/Transforms/JumpThreading/crash.ll +++ b/test/Transforms/JumpThreading/crash.ll @@ -324,3 +324,20 @@ A: ; preds = %entry call void undef(i64 ptrtoint (i8* blockaddress(@test11, %A) to i64)) nounwind unreachable } + +; PR6743 +define void @test12() nounwind ssp { +entry: + br label %lbl_51 + +lbl_51: ; preds = %if.then, %entry + %tmp3 = phi i1 [ false, %if.then ], [ undef, %entry ] ; <i1> [#uses=2] + br i1 %tmp3, label %if.end12, label %if.then + +if.then: ; preds = %lbl_51 + br i1 %tmp3, label %lbl_51, label %if.end12 + +if.end12: ; preds = %if.then, %lbl_51 + ret void +} + diff --git a/test/Transforms/LCSSA/unreachable-use.ll b/test/Transforms/LCSSA/unreachable-use.ll new file mode 100644 index 0000000..c389c9c --- /dev/null +++ b/test/Transforms/LCSSA/unreachable-use.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -lcssa -S -verify-loop-info | grep {\[%\]tmp33 = load i1\\*\\* \[%\]tmp} +; PR6546 + +; LCSSA doesn't need to transform uses in blocks not reachable +; from the entry block. + +define fastcc void @dfs() nounwind { +bb: + br label %bb44 + +bb44: + br i1 undef, label %bb7, label %bb45 + +bb7: + %tmp = bitcast i1** undef to i1** + br label %bb15 + +bb15: + br label %bb44 + +bb32: + %tmp33 = load i1** %tmp, align 8 + br label %bb45 + +bb45: + unreachable +} diff --git a/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll b/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll index 0847464..3cfd6c9 100644 --- a/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll +++ b/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll @@ -45,4 +45,4 @@ bb39: ; preds = %bb12, %bb3, %bb17 return: ; preds = %bb39 ret void -}
\ No newline at end of file +} diff --git a/test/Transforms/LoopStrengthReduce/insert-positions.ll b/test/Transforms/LoopStrengthReduce/insert-positions.ll new file mode 100644 index 0000000..1a695f3 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/insert-positions.ll @@ -0,0 +1,69 @@ +; RUN: llc < %s -march=x86-64 >/dev/null + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @test0() nounwind { +if.end90.i.i: + br label %while.body.i.i221.i + +while.body.i.i221.i: ; preds = %while.cond.backedge.i.i.i, %if.end90.i.i + br i1 undef, label %if.then.i.i224.i, label %while.cond.backedge.i.i.i + +while.cond.backedge.i.i.i: ; preds = %for.end.i.i.i, %while.body.i.i221.i + br label %while.body.i.i221.i + +if.then.i.i224.i: ; preds = %while.body.i.i221.i + switch i32 undef, label %for.cond.i.i226.i [ + i32 92, label %sw.bb.i.i225.i + i32 34, label %sw.bb.i.i225.i + i32 110, label %sw.bb21.i.i.i + ] + +sw.bb.i.i225.i: ; preds = %if.then.i.i224.i, %if.then.i.i224.i + unreachable + +sw.bb21.i.i.i: ; preds = %if.then.i.i224.i + unreachable + +for.cond.i.i226.i: ; preds = %for.body.i.i.i, %if.then.i.i224.i + %0 = phi i64 [ %tmp154.i.i.i, %for.body.i.i.i ], [ 0, %if.then.i.i224.i ] ; <i64> [#uses=2] + %tmp154.i.i.i = add i64 %0, 1 ; <i64> [#uses=2] + %i.0.i.i.i = trunc i64 %0 to i32 ; <i32> [#uses=1] + br i1 undef, label %land.rhs.i.i.i, label %for.end.i.i.i + +land.rhs.i.i.i: ; preds = %for.cond.i.i226.i + br i1 undef, label %for.body.i.i.i, label %for.end.i.i.i + +for.body.i.i.i: ; preds = %land.rhs.i.i.i + br label %for.cond.i.i226.i + +for.end.i.i.i: ; preds = %land.rhs.i.i.i, %for.cond.i.i226.i + %idx.ext.i.i.i = sext i32 %i.0.i.i.i to i64 ; <i64> [#uses=1] + %sub.ptr72.sum.i.i.i = xor i64 %idx.ext.i.i.i, -1 ; <i64> [#uses=1] + %pos.addr.1.sum155.i.i.i = add i64 %tmp154.i.i.i, %sub.ptr72.sum.i.i.i ; <i64> [#uses=1] + %arrayidx76.i.i.i = getelementptr inbounds i8* undef, i64 %pos.addr.1.sum155.i.i.i ; <i8*> [#uses=0] + br label %while.cond.backedge.i.i.i +} + +define void @test1() nounwind { +entry: + %t = shl i32 undef, undef ; <i32> [#uses=1] + %t9 = sub nsw i32 0, %t ; <i32> [#uses=1] + br label %outer + +outer: ; preds = %bb18, %bb + %i12 = phi i32 [ %t21, %bb18 ], [ 0, %entry ] ; <i32> [#uses=2] + %i13 = phi i32 [ %t20, %bb18 ], [ 0, %entry ] ; <i32> [#uses=2] + br label %inner + +inner: ; preds = %bb16, %bb11 + %t17 = phi i32 [ %i13, %outer ], [ undef, %inner ] ; <i32> [#uses=1] + store i32 %t17, i32* undef + br i1 undef, label %bb18, label %inner + +bb18: ; preds = %bb16 + %t19 = add i32 %i13, %t9 ; <i32> [#uses=1] + %t20 = add i32 %t19, %i12 ; <i32> [#uses=1] + %t21 = add i32 %i12, 1 ; <i32> [#uses=1] + br label %outer +} diff --git a/test/Transforms/LoopStrengthReduce/pr2537.ll b/test/Transforms/LoopStrengthReduce/pr2537.ll index 73c3152..46ad70e 100644 --- a/test/Transforms/LoopStrengthReduce/pr2537.ll +++ b/test/Transforms/LoopStrengthReduce/pr2537.ll @@ -18,4 +18,4 @@ afterdo: ; preds = %dobody ret void } -declare void @b(i128 %add)
\ No newline at end of file +declare void @b(i128 %add) diff --git a/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll b/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll index 8959c17..59f14fc 100644 --- a/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll +++ b/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -iv-users | grep {\{1,+,3,+,2\}<%loop> (post-inc)} +; RUN: opt < %s -analyze -iv-users | grep {\{1,+,3,+,2\}<%loop> (post-inc with loop %loop)} ; The value of %r is dependent on a polynomial iteration expression. diff --git a/test/Transforms/LoopStrengthReduce/uglygep.ll b/test/Transforms/LoopStrengthReduce/uglygep.ll new file mode 100644 index 0000000..dca97e9 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/uglygep.ll @@ -0,0 +1,67 @@ +; RUN: opt < %s -loop-reduce -S | not grep uglygep + +; LSR shouldn't consider %t8 to be an interesting user of %t6, and it +; should be able to form pretty GEPs. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define void @Z4() nounwind { +bb: + br label %bb3 + +bb1: ; preds = %bb3 + br i1 undef, label %bb10, label %bb2 + +bb2: ; preds = %bb1 + %t = add i64 %t4, 1 ; <i64> [#uses=1] + br label %bb3 + +bb3: ; preds = %bb2, %bb + %t4 = phi i64 [ %t, %bb2 ], [ 0, %bb ] ; <i64> [#uses=3] + br label %bb1 + +bb10: ; preds = %bb9 + %t7 = icmp eq i64 %t4, 0 ; <i1> [#uses=1] + %t3 = add i64 %t4, 16 ; <i64> [#uses=1] + br label %bb14 + +bb14: ; preds = %bb14, %bb10 + %t2 = getelementptr inbounds i8* undef, i64 %t4 ; <i8*> [#uses=1] + store i8 undef, i8* %t2 + %t6 = load float** undef + %t8 = bitcast float* %t6 to i8* ; <i8*> [#uses=1] + %t9 = getelementptr inbounds i8* %t8, i64 %t3 ; <i8*> [#uses=1] + store i8 undef, i8* %t9 + br label %bb14 +} + +define fastcc void @TransformLine() nounwind { +bb: + br label %loop0 + +loop0: ; preds = %loop0, %bb + %i0 = phi i32 [ %i0.next, %loop0 ], [ 0, %bb ] ; <i32> [#uses=2] + %i0.next = add i32 %i0, 1 ; <i32> [#uses=1] + br i1 false, label %loop0, label %bb0 + +bb0: ; preds = %loop0 + br label %loop1 + +loop1: ; preds = %bb5, %bb0 + %i1 = phi i32 [ 0, %bb0 ], [ %i1.next, %bb5 ] ; <i32> [#uses=4] + %t0 = add i32 %i0, %i1 ; <i32> [#uses=1] + br i1 false, label %bb2, label %bb6 + +bb2: ; preds = %loop1 + br i1 true, label %bb6, label %bb5 + +bb5: ; preds = %bb2 + %i1.next = add i32 %i1, 1 ; <i32> [#uses=1] + br i1 true, label %bb6, label %loop1 + +bb6: ; preds = %bb5, %bb2, %loop1 + %p8 = phi i32 [ %t0, %bb5 ], [ undef, %loop1 ], [ undef, %bb2 ] ; <i32> [#uses=0] + %p9 = phi i32 [ undef, %bb5 ], [ %i1, %loop1 ], [ %i1, %bb2 ] ; <i32> [#uses=0] + unreachable +} diff --git a/test/Transforms/LoopUnswitch/crash.ll b/test/Transforms/LoopUnswitch/crash.ll index fac55a6..101fb7a 100644 --- a/test/Transforms/LoopUnswitch/crash.ll +++ b/test/Transforms/LoopUnswitch/crash.ll @@ -45,3 +45,22 @@ for.body: ; preds = %for.body, %bb.nph for.end: ; preds = %for.body, %entry ret void } + +; PR6879 +define i32* @test3(i32** %p_45, i16 zeroext %p_46, i64 %p_47, i64 %p_48, i16 signext %p_49) nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %for.cond4, %entry + br i1 false, label %for.cond4, label %for.end88 + +for.cond4: ; preds = %for.cond + %conv46 = trunc i32 0 to i8 ; <i8> [#uses=2] + %cmp60 = icmp sgt i8 %conv46, 124 ; <i1> [#uses=1] + %or.cond = and i1 undef, %cmp60 ; <i1> [#uses=1] + %cond = select i1 %or.cond, i8 %conv46, i8 undef ; <i8> [#uses=0] + br label %for.cond + +for.end88: ; preds = %for.cond + ret i32* undef +} diff --git a/test/Transforms/MemCpyOpt/align.ll b/test/Transforms/MemCpyOpt/align.ll index 47df380..b0ae5f4 100644 --- a/test/Transforms/MemCpyOpt/align.ll +++ b/test/Transforms/MemCpyOpt/align.ll @@ -4,7 +4,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 ; The resulting memset is only 4-byte aligned, despite containing ; a 16-byte alignmed store in the middle. -; CHECK: call void @llvm.memset.i64(i8* %a01, i8 0, i64 16, i32 4) +; CHECK: call void @llvm.memset.p0i8.i64(i8* %a01, i8 0, i64 16, i32 4, i1 false) define void @foo(i32* %p) { %a0 = getelementptr i32* %p, i64 0 diff --git a/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll b/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll index 347af8f..33e0cfa 100644 --- a/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll +++ b/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -prune-eh -inline -print-callgraph \ ; RUN: -disable-output |& \ -; RUN: grep {Calls.*ce3806g__fxio__put__put_int64__4.1339} | count 2 +; RUN: grep {calls.*ce3806g__fxio__put__put_int64__4.1339} | count 2 %struct.FRAME.ce3806g = type { %struct.string___XUB, %struct.string___XUB, %struct.string___XUB, %struct.string___XUB } %struct.FRAME.ce3806g__fxio__put__4 = type { i32, i32, i32, %struct.system__file_control_block__pstring*, i32, i32, i8 } %struct.RETURN = type { i8, i32 } diff --git a/test/Transforms/SCCP/ipsccp-basic.ll b/test/Transforms/SCCP/ipsccp-basic.ll index e369920..a3c7637 100644 --- a/test/Transforms/SCCP/ipsccp-basic.ll +++ b/test/Transforms/SCCP/ipsccp-basic.ll @@ -188,7 +188,7 @@ define void @test8b(i32* %P) { %X = call {} @test8a(i32 5, i32* %P) ret void ; CHECK: define void @test8b -; CHECK-NEXT: call { } @test8a +; CHECK-NEXT: call {} @test8a ; CHECK-NEXT: ret void } diff --git a/test/Transforms/SCCP/undef-resolve.ll b/test/Transforms/SCCP/undef-resolve.ll new file mode 100644 index 0000000..bed561c --- /dev/null +++ b/test/Transforms/SCCP/undef-resolve.ll @@ -0,0 +1,106 @@ +; RUN: opt %s -sccp -S | FileCheck %s + + +; PR6940 +define double @test1() { + %t = sitofp i32 undef to double + ret double %t +; CHECK: @test1 +; CHECK: ret double 0.0 +} + + +; rdar://7832370 +; Check that lots of stuff doesn't get turned into undef. +define i32 @test2() nounwind readnone ssp { +; CHECK: @test2 +init: + br label %control.outer.outer + +control.outer.loopexit.us-lcssa: ; preds = %control + br label %control.outer.loopexit + +control.outer.loopexit: ; preds = %control.outer.loopexit.us-lcssa.us, %control.outer.loopexit.us-lcssa + br label %control.outer.outer.backedge + +control.outer.outer: ; preds = %control.outer.outer.backedge, %init + %switchCond.0.ph.ph = phi i32 [ 2, %init ], [ 3, %control.outer.outer.backedge ] ; <i32> [#uses=2] + %i.0.ph.ph = phi i32 [ undef, %init ], [ %i.0.ph.ph.be, %control.outer.outer.backedge ] ; <i32> [#uses=1] + %tmp4 = icmp eq i32 %i.0.ph.ph, 0 ; <i1> [#uses=1] + br i1 %tmp4, label %control.outer.outer.split.us, label %control.outer.outer.control.outer.outer.split_crit_edge + +control.outer.outer.control.outer.outer.split_crit_edge: ; preds = %control.outer.outer + br label %control.outer + +control.outer.outer.split.us: ; preds = %control.outer.outer + br label %control.outer.us + +control.outer.us: ; preds = %bb3.us, %control.outer.outer.split.us + %A.0.ph.us = phi i32 [ %switchCond.0.us, %bb3.us ], [ 4, %control.outer.outer.split.us ] ; <i32> [#uses=2] + %switchCond.0.ph.us = phi i32 [ %A.0.ph.us, %bb3.us ], [ %switchCond.0.ph.ph, %control.outer.outer.split.us ] ; <i32> [#uses=1] + br label %control.us + +bb3.us: ; preds = %control.us + br label %control.outer.us + +bb0.us: ; preds = %control.us + br label %control.us + +; CHECK: control.us: ; preds = %bb0.us, %control.outer.us +; CHECK-NEXT: %switchCond.0.us = phi i32 +; CHECK-NEXT: switch i32 %switchCond.0.us +control.us: ; preds = %bb0.us, %control.outer.us + %switchCond.0.us = phi i32 [ %A.0.ph.us, %bb0.us ], [ %switchCond.0.ph.us, %control.outer.us ] ; <i32> [#uses=2] + switch i32 %switchCond.0.us, label %control.outer.loopexit.us-lcssa.us [ + i32 0, label %bb0.us + i32 1, label %bb1.us-lcssa.us + i32 3, label %bb3.us + i32 4, label %bb4.us-lcssa.us + ] + +control.outer.loopexit.us-lcssa.us: ; preds = %control.us + br label %control.outer.loopexit + +bb1.us-lcssa.us: ; preds = %control.us + br label %bb1 + +bb4.us-lcssa.us: ; preds = %control.us + br label %bb4 + +control.outer: ; preds = %bb3, %control.outer.outer.control.outer.outer.split_crit_edge + %A.0.ph = phi i32 [ %nextId17, %bb3 ], [ 4, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1] + %switchCond.0.ph = phi i32 [ 0, %bb3 ], [ %switchCond.0.ph.ph, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1] + br label %control + +control: ; preds = %bb0, %control.outer + %switchCond.0 = phi i32 [ %A.0.ph, %bb0 ], [ %switchCond.0.ph, %control.outer ] ; <i32> [#uses=2] + switch i32 %switchCond.0, label %control.outer.loopexit.us-lcssa [ + i32 0, label %bb0 + i32 1, label %bb1.us-lcssa + i32 3, label %bb3 + i32 4, label %bb4.us-lcssa + ] + +bb4.us-lcssa: ; preds = %control + br label %bb4 + +bb4: ; preds = %bb4.us-lcssa, %bb4.us-lcssa.us + br label %control.outer.outer.backedge + +control.outer.outer.backedge: ; preds = %bb4, %control.outer.loopexit + %i.0.ph.ph.be = phi i32 [ 1, %bb4 ], [ 0, %control.outer.loopexit ] ; <i32> [#uses=1] + br label %control.outer.outer + +bb3: ; preds = %control + %nextId17 = add i32 %switchCond.0, -2 ; <i32> [#uses=1] + br label %control.outer + +bb0: ; preds = %control + br label %control + +bb1.us-lcssa: ; preds = %control + br label %bb1 + +bb1: ; preds = %bb1.us-lcssa, %bb1.us-lcssa.us + ret i32 0 +} diff --git a/test/Transforms/ScalarRepl/memcpy-align.ll b/test/Transforms/ScalarRepl/memcpy-align.ll new file mode 100644 index 0000000..91d354d --- /dev/null +++ b/test/Transforms/ScalarRepl/memcpy-align.ll @@ -0,0 +1,32 @@ +; RUN: opt %s -scalarrepl -S | FileCheck %s +; PR6832 +target datalayout = +"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "arm-u-u" + +%0 = type { %struct.anon, %struct.anon } +%struct.anon = type { [4 x i8] } + +@c = external global %0 ; <%0*> [#uses=1] + +define arm_aapcscc void @good() nounwind { +entry: + %x0 = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=2] + %tmp = bitcast %struct.anon* %x0 to i8* ; <i8*> [#uses=1] + call void @llvm.memset.p0i8.i32(i8* %tmp, i8 0, i32 4, i32 4, i1 false) + %tmp1 = bitcast %struct.anon* %x0 to i8* ; <i8*> [#uses=1] + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%0* @c, i32 +0, i32 0, i32 0, i32 0), i8* %tmp1, i32 4, i32 4, i1 false) + ret void + +; CHECK: store i8 0, i8*{{.*}}, align 4 +; CHECK: store i8 0, i8*{{.*}}, align 1 +; CHECK: store i8 0, i8*{{.*}}, align 2 +; CHECK: store i8 0, i8*{{.*}}, align 1 +} + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, +i1) nounwind + diff --git a/test/Transforms/SimplifyCFG/2010-03-30-InvokeCrash.ll b/test/Transforms/SimplifyCFG/2010-03-30-InvokeCrash.ll new file mode 100644 index 0000000..ced89cf --- /dev/null +++ b/test/Transforms/SimplifyCFG/2010-03-30-InvokeCrash.ll @@ -0,0 +1,18 @@ +; RUN: opt %s -simplifycfg -disable-output +; END. +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +declare void @bar(i32) + +define void @foo() { +entry: + invoke void @bar(i32 undef) + to label %r unwind label %u + +r: ; preds = %entry + ret void + +u: ; preds = %entry + unwind +} diff --git a/test/Transforms/SimplifyLibCalls/StrCpy.ll b/test/Transforms/SimplifyLibCalls/StrCpy.ll index 7542984..83406ff 100644 --- a/test/Transforms/SimplifyLibCalls/StrCpy.ll +++ b/test/Transforms/SimplifyLibCalls/StrCpy.ll @@ -1,30 +1,37 @@ ; Test that the StrCpyOptimizer works correctly -; RUN: opt < %s -simplify-libcalls -S | \ -; RUN: not grep {call.*strcpy} +; RUN: opt < %s -simplify-libcalls -S | FileCheck %s ; This transformation requires the pointer size, as it assumes that size_t is ; the size of a pointer. -target datalayout = "-p:64:64:64" +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" -@hello = constant [6 x i8] c"hello\00" ; <[6 x i8]*> [#uses=1] -@null = constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1] -@null_hello = constant [7 x i8] c"\00hello\00" ; <[7 x i8]*> [#uses=1] +@hello = constant [6 x i8] c"hello\00" declare i8* @strcpy(i8*, i8*) -declare i32 @puts(i8*) - -define i32 @main() { - %target = alloca [1024 x i8] ; <[1024 x i8]*> [#uses=1] - %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0 ; <i8*> [#uses=2] - store i8 0, i8* %arg1 - %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0 ; <i8*> [#uses=1] - %rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 ) ; <i8*> [#uses=1] - %arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0 ; <i8*> [#uses=1] - %rslt2 = call i8* @strcpy( i8* %rslt1, i8* %arg3 ) ; <i8*> [#uses=1] - %arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0 ; <i8*> [#uses=1] - %rslt3 = call i8* @strcpy( i8* %rslt2, i8* %arg4 ) ; <i8*> [#uses=1] - call i32 @puts( i8* %rslt3 ) ; <i32>:1 [#uses=0] - ret i32 0 +declare i8* @__strcpy_chk(i8*, i8*, i32) nounwind + +declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly + +; rdar://6839935 + +define i32 @t1() { +; CHECK: @t1 + %target = alloca [1024 x i8] + %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0 + %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0 + %rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 ) +; CHECK: @llvm.memcpy.p0i8.p0i8.i32 + ret i32 0 } +define i32 @t2() { +; CHECK: @t2 + %target = alloca [1024 x i8] + %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0 + %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0 + %tmp1 = call i32 @llvm.objectsize.i32(i8* %arg1, i1 false) + %rslt1 = call i8* @__strcpy_chk(i8* %arg1, i8* %arg2, i32 %tmp1) +; CHECK: @__memcpy_chk + ret i32 0 +} diff --git a/test/Transforms/TailCallElim/inf-recursion.ll b/test/Transforms/TailCallElim/inf-recursion.ll index a5f246d..e4ac928 100644 --- a/test/Transforms/TailCallElim/inf-recursion.ll +++ b/test/Transforms/TailCallElim/inf-recursion.ll @@ -1,6 +1,10 @@ -; RUN: opt < %s -tailcallelim -S | grep call +; RUN: opt < %s -tailcallelim -S | FileCheck %s + ; Don't turn this into an infinite loop, this is probably the implementation ; of fabs and we expect the codegen to lower fabs. +; CHECK: @fabs(double %f) +; CHECK: call +; CHECK: ret define double @fabs(double %f) { entry: @@ -8,3 +12,23 @@ entry: ret double %tmp2 } +; Do turn other calls into infinite loops though. + +; CHECK: define double @foo +; CHECK-NOT: call +; CHECK: } +define double @foo(double %f) { + %t= call double @foo(double %f) + ret double %t +} + +; CHECK: define float @fabsf +; CHECK-NOT: call +; CHECK: } +define float @fabsf(float %f) { + %t= call float @fabsf(float 2.0) + ret float %t +} + +declare float @fabsf(float %f) +declare x86_fp80 @fabsl(x86_fp80 %f) diff --git a/test/Verifier/2006-12-12-IntrinsicDefine.ll b/test/Verifier/2006-12-12-IntrinsicDefine.ll index b63ae65..8d09b51 100644 --- a/test/Verifier/2006-12-12-IntrinsicDefine.ll +++ b/test/Verifier/2006-12-12-IntrinsicDefine.ll @@ -1,7 +1,7 @@ ; RUN: not llvm-as < %s |& grep {llvm intrinsics cannot be defined} ; PR1047 -define void @llvm.memcpy.i32(i8*, i8*, i32, i32) { +define void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) { entry: ret void } diff --git a/test/lit.cfg b/test/lit.cfg index b4aec5a..fd3120a 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -128,6 +128,10 @@ excludes = [] # Provide target_triple for use in XFAIL and XTARGET. config.target_triple = site_exp['target_triplet'] +# When running under valgrind, we mangle '-vg' or '-vg_leak' onto the end of the +# triple so we can check it with XFAIL and XTARGET. +config.target_triple += lit.valgrindTriple + # Provide llvm_supports_target for use in local configs. targets = set(site_exp["TARGETS_TO_BUILD"].split()) def llvm_supports_target(name): @@ -144,9 +148,6 @@ bindings = set(site_exp['llvm_bindings'].split(',')) def llvm_supports_binding(name): return name in bindings -config.conditions["TARGET"] = llvm_supports_target -config.conditions["BINDING"] = llvm_supports_binding - # Provide on_clone hook for reading 'dg.exp'. import os simpleLibData = re.compile(r"""load_lib llvm.exp |