Convert this test to .s form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117682 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 36 insertions, 143 deletions

diff --git a/test/MC/ARM/neon-bitwise-encoding.ll b/test/MC/ARM/neon-bitwise-encoding.ll
deleted file mode 100644
index ebfff60..0000000
--- a/test/MC/ARM/neon-bitwise-encoding.ll
+++ /dev/null
@@ -1,143 +0,0 @@
-; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
-
-; XFAIL: *
-
-; FIXME: The following instructions still require testing:
-;  - vand with immediate, vorr with immediate
-;  - both vbit and vbif
-
-; CHECK: vand_8xi8
-define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-; CHECK: vand	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf2]
-	%tmp3 = and <8 x i8> %tmp1, %tmp2
-	ret <8 x i8> %tmp3
-}
-
-; CHECK: vand_16xi8
-define <16 x i8> @vand_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-; CHECK: vand	q8, q8, q9              @ encoding: [0xf2,0x01,0x40,0xf2]
-	%tmp3 = and <16 x i8> %tmp1, %tmp2
-	ret <16 x i8> %tmp3
-}
-
-; CHECK: veor_8xi8
-define <8 x i8> @veor_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-; CHECK: veor	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf3]
-	%tmp3 = xor <8 x i8> %tmp1, %tmp2
-	ret <8 x i8> %tmp3
-}
-
-; CHECK: veor_16xi8
-define <16 x i8> @veor_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-; CHECK: veor	q8, q8, q9              @ encoding: [0xf2,0x01,0x40,0xf3]
-	%tmp3 = xor <16 x i8> %tmp1, %tmp2
-	ret <16 x i8> %tmp3
-}
-
-; CHECK: vorr_8xi8
-define <8 x i8> @vorr_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-; CHECK: vorr	d16, d17, d16           @ encoding: [0xb0,0x01,0x61,0xf2]
-	%tmp3 = or <8 x i8> %tmp1, %tmp2
-	ret <8 x i8> %tmp3
-}
-
-; CHECK: vorr_16xi8
-define <16 x i8> @vorr_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-; CHECK: vorr	q8, q8, q9              @ encoding: [0xf2,0x01,0x60,0xf2]
-	%tmp3 = or <16 x i8> %tmp1, %tmp2
-	ret <16 x i8> %tmp3
-}
-
-; CHECK: vbic_8xi8
-define <8 x i8> @vbic_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-; CHECK: vbic	d16, d17, d16           @ encoding: [0xb0,0x01,0x51,0xf2]
-	%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	%tmp4 = and <8 x i8> %tmp1, %tmp3
-	ret <8 x i8> %tmp4
-}
-
-; CHECK: vbic_16xi8
-define <16 x i8> @vbic_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-; CHECK: vbic	q8, q8, q9              @ encoding: [0xf2,0x01,0x50,0xf2]
-	%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	%tmp4 = and <16 x i8> %tmp1, %tmp3
-	ret <16 x i8> %tmp4
-}
-
-; CHECK: vorn_8xi8
-define <8 x i8> @vorn_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-; CHECK: vorn	d16, d17, d16           @ encoding: [0xb0,0x01,0x71,0xf2]
-	%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	%tmp4 = or <8 x i8> %tmp1, %tmp3
-	ret <8 x i8> %tmp4
-}
-
-; CHECK: vorn_16xi8
-define <16 x i8> @vorn_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-; CHECK: vorn	q8, q8, q9              @ encoding: [0xf2,0x01,0x70,0xf2]
-	%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	%tmp4 = or <16 x i8> %tmp1, %tmp3
-	ret <16 x i8> %tmp4
-}
-
-; CHECK: vmvn_8xi8
-define <8 x i8> @vmvn_8xi8(<8 x i8>* %A) nounwind {
-	%tmp1 = load <8 x i8>* %A
-; CHECK: vmvn	d16, d16                @ encoding: [0xa0,0x05,0xf0,0xf3]
-	%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	ret <8 x i8> %tmp2
-}
-
-; CHECK: vmvn_16xi8
-define <16 x i8> @vmvn_16xi8(<16 x i8>* %A) nounwind {
-	%tmp1 = load <16 x i8>* %A
-; CHECK: vmvn	q8, q8                  @ encoding: [0xe0,0x05,0xf0,0xf3]
-	%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	ret <16 x i8> %tmp2
-}
-
-; CHECK: vbsl_8xi8
-define <8 x i8> @vbsl_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
-; CHECK: vbsl	d18, d17, d16           @ encoding: [0xb0,0x21,0x51,0xf3]
-	%tmp4 = and <8 x i8> %tmp1, %tmp2
-	%tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	%tmp6 = and <8 x i8> %tmp5, %tmp3
-	%tmp7 = or <8 x i8> %tmp4, %tmp6
-	ret <8 x i8> %tmp7
-}
-
-; CHECK: vbsl_16xi8
-define <16 x i8> @vbsl_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
-; CHECK: vbsl	q8, q10, q9             @ encoding: [0xf2,0x01,0x54,0xf3]
-	%tmp4 = and <16 x i8> %tmp1, %tmp2
-	%tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
-	%tmp6 = and <16 x i8> %tmp5, %tmp3
-	%tmp7 = or <16 x i8> %tmp4, %tmp6
-	ret <16 x i8> %tmp7
-}
diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s
new file mode 100644
index 0000000..da7ae64
--- /dev/null
+++ b/test/MC/ARM/neon-bitwise-encoding.s
@@ -0,0 +1,36 @@
+// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+
+// CHECK: vand	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf2]
+	vand	d16, d17, d16
+// CHECK: vand	q8, q8, q9              @ encoding: [0xf2,0x01,0x40,0xf2]
+	vand	q8, q8, q9
+
+// CHECK: veor	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf3]
+	veor	d16, d17, d16
+// CHECK: veor	q8, q8, q9              @ encoding: [0xf2,0x01,0x40,0xf3]
+	veor	q8, q8, q9
+
+// CHECK: vorr	d16, d17, d16           @ encoding: [0xb0,0x01,0x61,0xf2]
+	vorr	d16, d17, d16
+// CHECK: vorr	q8, q8, q9              @ encoding: [0xf2,0x01,0x60,0xf2]
+	vorr	q8, q8, q9
+
+// CHECK: vbic	d16, d17, d16           @ encoding: [0xb0,0x01,0x51,0xf2]
+	vbic	d16, d17, d16
+// CHECK: vbic	q8, q8, q9              @ encoding: [0xf2,0x01,0x50,0xf2]
+	vbic	q8, q8, q9
+
+// CHECK: vorn	d16, d17, d16           @ encoding: [0xb0,0x01,0x71,0xf2]
+	vorn	d16, d17, d16
+// CHECK: vorn	q8, q8, q9              @ encoding: [0xf2,0x01,0x70,0xf2]
+	vorn	q8, q8, q9
+
+// CHECK: vmvn	d16, d16                @ encoding: [0xa0,0x05,0xf0,0xf3]
+	vmvn	d16, d16
+// CHECK: vmvn	q8, q8                  @ encoding: [0xe0,0x05,0xf0,0xf3]
+	vmvn	q8, q8
+
+// CHECK: vbsl	d18, d17, d16           @ encoding: [0xb0,0x21,0x51,0xf3]
+	vbsl	d18, d17, d16
+// CHECK: vbsl	q8, q10, q9             @ encoding: [0xf2,0x01,0x54,0xf3]
+	vbsl	q8, q10, q9