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| author | Tim Northover <Tim.Northover@arm.com> | 2012-09-05 18:37:53 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2012-09-05 18:37:53 +0000 |
| commit | 7bebddf55ece46995f310d79195afb4e5b239886 (patch) | |
| tree | 90b2316e8ee16bbf80b7a323b1db4f52a0440fc8 /test | |
| parent | b985e9aacdd604a5a503496a1633fa9c6ef7235c (diff) | |
| download | external_llvm-7bebddf55ece46995f310d79195afb4e5b239886.zip external_llvm-7bebddf55ece46995f310d79195afb4e5b239886.tar.gz external_llvm-7bebddf55ece46995f310d79195afb4e5b239886.tar.bz2 | |
Strip old MachineInstrs *after* we know we can put them back.
Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163230 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/domain-conv-vmovs.ll | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/domain-conv-vmovs.ll b/test/CodeGen/ARM/domain-conv-vmovs.ll index f1cd9f58..e19185b 100644 --- a/test/CodeGen/ARM/domain-conv-vmovs.ll +++ b/test/CodeGen/ARM/domain-conv-vmovs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) { ; CHECK: test_vmovs_via_vext_lane0to0: @@ -62,3 +62,23 @@ define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) { ret float %res } +declare float @llvm.sqrt.f32(float) + +declare void @bar() + +; This is a comp +define float @test_ineligible(float, float %in) { +; CHECK: test_ineligible: + + %sqrt = call float @llvm.sqrt.f32(float %in) + %val = fadd float %sqrt, %sqrt + + ; This call forces a move from a callee-saved register to the return-reg. That + ; move is not eligible for conversion to a d-register instructions because the + ; use-def chains would be messed up. Primarily a compile-test (we used to + ; internal fault). + call void @bar() +; CHECL: bl bar +; CHECK: vmov.f32 {{s[0-9]+}}, {{s[0-9]+}} + ret float %val +}
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